SuccessChanges

Changes from Git (git http://labmaster3.local/git/llvm-project.git)

Summary

  1. [LegalizeIntegerTypes] Improve ExpandIntRes_SADDSUBO codegen on targets without SADDO/SSUBO. (details)
  2. Revert "Module: Use FileEntryRef and DirectoryEntryRef in Umbrella, Header, and DirectoryName, NFC" (details)
  3. [InstructionSimplify] SimplifyShift - rename shift amount KnownBits. NFCI. (details)
  4. make Affine parallel and yield ops MemRefsNormalizable (details)
  5. [OpenMP][NVPTX] Fixed a compilation error in deviceRTLs caused by unsupported feature in release verion of LLVM (details)
  6. [flang][test] Share all driver test dirs between `f18` and `flang-new` (details)
  7. [AMDGPU] Set threshold for regbanks reassign pass (details)
  8. [InstSimplify] Handle nsw shl -> poison patterns (details)
  9. [clang-tidy] Add cppcoreguidelines-prefer-member-initializer to ReleaseNotes (details)
  10. [LV] Ensure fixNonInductionPHIs uses a valid insertion point. (details)
  11. [NFC][VPlan] Use VPUser to store block's predicate (details)
  12. [AArch64] Regenerate check lines for neon-compare-instructions.ll. (details)
  13. [AArch64][GlobalISel] Lower G_USUBSAT and G_UADDSAT for scalars. (details)
  14. Recommit "[AArch64][GlobalISel] Match G_SHUFFLE_VECTOR -> insert elt + extract elt" (details)
  15. [RISCV] Use a different constant in one of the smulo test cases to avoid converting the mul to an add. (details)
  16. Revert "[docs][ORC] Fix section title and reference." (details)
  17. [AArch64] Introduce UDOT/SDOT DAG nodes (details)
  18. [llvm-profdata] Emit Error when Invalid MemOpSize Section is Created by llvm-profdata (details)
  19. [flang][fir][NFC] remove dead code (details)
  20. [mlir][sparse] incorporate vector index into address computation (details)
  21. Defer the decision whether to use the CU or TU index until after reading the unit header. (details)
  22. [Driver][Windows] Support per-target runtimes dir layout for profile instr generate (details)
  23. [SEMA] Added warn_decl_shadow support for structured bindings (details)
  24. AMDGPU: Use aligned vgprs/agprs in gfx90a mir tests (details)
  25. [ARM] Mir test for pre/postinc ldstopt combines. NFC (details)
  26. [mlir] Refactor InterfaceMap to use a sorted vector of interfaces, as opposed to a DenseMap (details)
  27. [mlir][Inliner] Use llvm::parallelForEach instead of llvm::parallelTransformReduce (details)
  28. [WebAssembly] Disable wasm.lsda() optimization in WasmEHPrepare (details)
  29. Fix a range-loop-analysis warning. (details)
  30. [scan-build-py] Add sarif-html support in scan-build-py (details)
  31. [WebAssembly] Fix incorrect grouping and sorting of exceptions (details)
  32. [LTO] Fix test failures caused by 6da7d3141651 (details)
  33. [dfsan] Update memset and dfsan_(set|add)_label with origin tracking (details)
  34. [libc] Add exhaustive test for sqrtf. (details)
  35. [libc] Add a standalone flavor of an equivalent of std::string_view. (details)
  36. [RISCV] Add vadd with mask and without mask builtin. (details)
  37. [WPD] Fix handling of pure virtual base class (details)
  38. [ThinLTO] Make cloneUsedGlobalVariables deterministic (details)
  39. Fix unstable SmallPtrSet iteration issues due to collectUsedGlobalVariables (details)
  40. collectUsedGlobalVariables: migrate SmallPtrSetImpl overload to SmallVecImpl overload after D97128 (details)
  41. [AArch64][GlobalISel] Correct function evaluation order in applyINS (details)
  42. [NFC] Make TrailingObjects non-copyable/non-movable (details)
  43. [mlir][Inliner] Keep the number of async pass managers constant (details)
  44. [mlir] ExecutionEngine needs special handling for COFF binaries (details)
  45. Revert "[Driver][Windows] Support per-target runtimes dir layout for profile instr generate" (details)
  46. [SimplifyCFG] Update passingValueIsAlwaysUndefined to check more attributes (details)
  47. [LoopNest] Use `getUniqueSuccessor()` instead when checking empty blocks (details)
  48. Add more historic DWARF vendor extensions (details)
  49. [Debug-Info][NFC] move emitDwarfUnitLength to MCStreamer class (details)
  50. [mlir][Inliner] Don't optimize callees in async mode if there is only one to optimize (details)
  51. [lld-macho] Use full input file name in invalid relocation error message (details)
  52. [lld-macho] Fix semantics & add tests for ARM64 GOT/TLV relocs (details)
  53. [lld-macho] Check for arch compatibility when loading ObjFiles and TBDs (details)
  54. [lld-macho] Better deduplication of personality pointers (details)
  55. Revert "Add more historic DWARF vendor extensions" (details)
  56. [XCOFF] add C_FILE symbol at index 0 of symbol table. (details)
  57. [AArch64][GlobalISel][PostSelectOpt] Constrain reg operands after mutating instructions. (details)
  58. [HIP] Fix managed variable linkage (details)
Commit eb165090bb063cb6b73433c30adeed6fef995108 by craig.topper
[LegalizeIntegerTypes] Improve ExpandIntRes_SADDSUBO codegen on targets without SADDO/SSUBO.

This code creates 3 setccs that need to be expanded. It was
creating a sign bit test as setge X, 0 which is non-canonical.
Canonical would be setgt X, -1. This misses the special case in
IntegerExpandSetCCOperands for sign bit tests that assumes
canonical form. If we don't hit this special case we end up
with a multipart setcc instead of just checking the sign of
the high part.

To fix this I've reversed the polarity of all of the setccs to
setlt X, 0 which is canonical. The rest of the logic should
still work. This seems to produce better code on RISCV which
lacks a setgt instruction.

This probably still isn't the best code sequence we could use here.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D97181
The file was modifiedllvm/test/CodeGen/RISCV/ssub_sat_plus.ll
The file was modifiedllvm/test/CodeGen/ARM/ssub_sat_plus.ll
The file was modifiedllvm/test/CodeGen/RISCV/sadd_sat.ll
The file was modifiedllvm/test/CodeGen/RISCV/xaluo.ll
The file was modifiedllvm/test/CodeGen/ARM/sadd_sat.ll
The file was modifiedllvm/test/CodeGen/AArch64/ssub_sat_vec.ll
The file was modifiedllvm/test/CodeGen/Thumb2/mve-saturating-arith.ll
The file was modifiedllvm/test/CodeGen/ARM/sadd_sat_plus.ll
The file was modifiedllvm/test/CodeGen/ARM/ssub_sat.ll
The file was modifiedllvm/test/CodeGen/RISCV/sadd_sat_plus.ll
The file was modifiedllvm/test/CodeGen/RISCV/ssub_sat.ll
The file was modifiedllvm/test/CodeGen/AArch64/sadd_sat_vec.ll
The file was modifiedllvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
Commit 64d8c7818db2bd428d4e2a9f27661ee49225477f by Duncan P. N. Exon Smith
Revert "Module: Use FileEntryRef and DirectoryEntryRef in Umbrella, Header, and DirectoryName, NFC"

This (mostly) reverts 32c501dd88b62787d3a5ffda7aabcf4650dbe3cd.  Hit a
case where this causes a behaviour change, perhaps the same root cause
that triggered the revert of a40db5502b2515a6f2f1676b5d7a655ae0f41179 in
7799ef7121aa7d59f4bd95cdf70035de724ead6f.

(The API changes in DirectoryEntry.h have NOT been reverted as a number
of subsequent commits depend on those.)

https://reviews.llvm.org/D90497#2582166
The file was modifiedclang/include/clang/Basic/Module.h
The file was modifiedclang/include/clang/Lex/ModuleMap.h
The file was modifiedclang/lib/Basic/Module.cpp
The file was modifiedclang/lib/Frontend/FrontendActions.cpp
The file was modifiedclang/lib/Lex/ModuleMap.cpp
The file was modifiedclang/lib/Serialization/ASTReader.cpp
Commit 18b9fc48f1b64061699533740dd6218c982f5b58 by llvm-dev
[InstructionSimplify] SimplifyShift - rename shift amount KnownBits. NFCI.

As suggested on D97305.
The file was modifiedllvm/lib/Analysis/InstructionSimplify.cpp
Commit af8adea155a14b99381532fc22122b7218e65db4 by jeremy.bruestle
make Affine parallel and yield ops MemRefsNormalizable

Affine parallel ops may contain and yield results from MemRefsNormalizable ops in the loop body.  Thus, both affine.parallel and affine.yield should have the MemRefsNormalizable trait.

Reviewed By: bondhugula

Differential Revision: https://reviews.llvm.org/D96821
The file was modifiedmlir/include/mlir/Dialect/Affine/IR/AffineOps.td
The file was modifiedmlir/test/Transforms/normalize-memrefs.mlir
The file was modifiedmlir/lib/Transforms/NormalizeMemRefs.cpp
Commit f6c2984a090e78947f75e096d43b476bf2ae73eb by tianshilei1992
[OpenMP][NVPTX] Fixed a compilation error in deviceRTLs caused by unsupported feature in release verion of LLVM

`ptx71` is not supported in release version of LLVM yet. As a result,
the support of CUDA 11.2 and CUDA 11.1 caused a compilation error as mentioned
in D97004. Since the support in D97004 is just a WA for releease, and we'll not
use it in the near future, using `ptx70` for CUDA 11 is feasible.

Reviewed By: jdoerfert

Differential Revision: https://reviews.llvm.org/D97195
The file was modifiedopenmp/libomptarget/deviceRTLs/nvptx/CMakeLists.txt
Commit 5e54bef4d291d4353bb26e0782539b6f79625f68 by andrzej.warzynski
[flang][test] Share all driver test dirs between `f18` and `flang-new`

Originally, when we added the new driver, we created dedicated test
directories for `flang-new`. This way we separated the tests for the
`throwaway` and the new driver.

As we are increasing test coverage and starting to share tests between
the two drivers, it makes sense to share all directories and instead
rely on:
```
! REQUIRES: new-flang-driver
```
to mark tests as exclusively for the new driver.

Differential Revision: https://reviews.llvm.org/D97207
The file was modifiedflang/test/lit.cfg.py
The file was modifiedflang/test/Frontend/prescanner-diag.f90
Commit d1b92c91afd0be8939bddbf04f55ec53cf29227a by Stanislav.Mekhanoshin
[AMDGPU] Set threshold for regbanks reassign pass

This is to limit compile time. I did experiments with some
inputs and found that compile time keeps reasonable for this
pass if we have less than 100000 virtual registers and then
starts to explode somewhere between 100000 and 150000.

Differential Revision: https://reviews.llvm.org/D97218
The file was modifiedllvm/lib/Target/AMDGPU/GCNRegBankReassign.cpp
Commit 1020d161565df48ec454509724e60ab8fbbdfd66 by llvm-dev
[InstSimplify] Handle nsw shl -> poison patterns

Pulled out from D90479 - this recognises invalid nsw shl patterns with signbit changes that result in poison.

Differential Revision: https://reviews.llvm.org/D97305
The file was modifiedllvm/test/Transforms/InstCombine/known-signbit-shift.ll
The file was modifiedllvm/lib/Analysis/InstructionSimplify.cpp
The file was modifiedllvm/test/Transforms/InstSimplify/icmp-constant.ll
Commit 2af5275f72dad18b76d4db641c3c861d76aa29be by n.james93
[clang-tidy] Add cppcoreguidelines-prefer-member-initializer to ReleaseNotes

Following a discussion about the current state of this check on the 12.X branch, it was decided to purge the check as it wasn't in a fit to release state, see https://llvm.org/PR49318.
This check has since had some of those issues addressed and should be good for the next release cycle now, pending any more bug reports about it.

Reviewed By: aaron.ballman

Differential Revision: https://reviews.llvm.org/D97275
The file was modifiedclang-tools-extra/docs/ReleaseNotes.rst
Commit de40423c8512c9cfa0b244314b5e342056ec6d49 by flo
[LV] Ensure fixNonInductionPHIs uses a valid insertion point.

In some cases, Builder's insertion point may be invalidated before using
it in VPTransformState::get. Make sure the insertion point is
up-to-date.

This should fix various sanitizer errors, like
https://lab.llvm.org/buildbot/#/builders/5/builds/4933/steps/9/logs/stdio
The file was modifiedllvm/lib/Transforms/Vectorize/LoopVectorize.cpp
Commit 3605b873f6f0df36037f418974433e2c759e978b by andrei.elovikov
[NFC][VPlan] Use VPUser to store block's predicate

Reviewed By: fhahn

Differential Revision: https://reviews.llvm.org/D96529
The file was modifiedllvm/lib/Transforms/Vectorize/VPlan.h
The file was modifiedllvm/lib/Transforms/Vectorize/VPlan.cpp
Commit fd03e359ddbb47fd06dc1d37777434e43b85480d by flo
[AArch64] Regenerate check lines for neon-compare-instructions.ll.

Auto-generate tests so they can be updated more easily, e.g. for D97303.
The file was modifiedllvm/test/CodeGen/AArch64/neon-compare-instructions.ll
Commit 939b5ce73461e9a6bbd57ffb27b3ef9f28b0e1ec by Amara Emerson
[AArch64][GlobalISel] Lower G_USUBSAT and G_UADDSAT for scalars.

We have some missing optimization counterparts to LowerXALUO, but it's a start.
The file was addedllvm/test/CodeGen/AArch64/GlobalISel/legalize-uadd-sat.mir
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
The file was addedllvm/test/CodeGen/AArch64/GlobalISel/legalize-usub-sat.mir
Commit ef1f7f1d7db1e9bf7e256e208c295b605b014059 by Jessica Paquette
Recommit "[AArch64][GlobalISel] Match G_SHUFFLE_VECTOR -> insert elt + extract elt"

Attempted fix for the added test failing.

https://lab.llvm.org/buildbot/#/builders/104/builds/2355/steps/5/logs/stdio

I can't reproduce the failure anywhere, so I'm going to guess that passing a
std::function as MatchInfo is sketchy in this context.

Switch it to a std::tuple and hope for the best.
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
The file was addedllvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-shuf-to-ins.mir
The file was modifiedllvm/lib/Target/AArch64/AArch64Combine.td
Commit 5e233ff144e2f05254469ae0e20a4597b03d11b7 by craig.topper
[RISCV] Use a different constant in one of the smulo test cases to avoid converting the mul to an add.
The file was modifiedllvm/test/CodeGen/RISCV/xaluo.ll
Commit 479db97a34e3fa387c7549a4b10bce8e993605eb by Lang Hames
Revert "[docs][ORC] Fix section title and reference."

This reverts commit 6e1affe71c79a1cb5ea9d805ff7baae5cba59c0e, which caused an
error on the Sphinx doc bot.
The file was modifiedllvm/docs/ORCv2.rst
Commit f51b3de4e851812b5f7d7c307ddb7b6ec61c05ab by david.green
[AArch64] Introduce UDOT/SDOT DAG nodes

This is used to lower UDOT/SDOT instructions, as opposed to relying on
the intrinsic. Subsequent optimizations will be able to optimize them
more cleanly based on these nodes.
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.h
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrInfo.td
Commit 6da7d3141651ed3ef2b5f369e8ca0eb2e5c66778 by matthew.voss
[llvm-profdata] Emit Error when Invalid MemOpSize Section is Created by llvm-profdata

Under certain (currently unknown) conditions, llvm-profdata is outputting
profiles that have two consecutive entries in the MemOPSize section for the
value 0. This causes the PGOMemOPSizeOpt pass to output an invalid switch
instruction with two cases for 0. As mentioned, we’re not quite sure what’s
causing this to happen, but this patch prevents llvm-profdata from outputting a
profile that has this problem and gives an error with a request for a
reproducible.

Differential Revision: https://reviews.llvm.org/D92074
The file was modifiedllvm/include/llvm/ProfileData/InstrProf.h
The file was modifiedllvm/tools/llvm-profdata/llvm-profdata.cpp
The file was addedllvm/test/tools/llvm-profdata/invalid-profile-gen-zeros.proftext
The file was addedllvm/test/Transforms/PGOProfile/Inputs/consecutive-zeros.proftext
The file was modifiedllvm/lib/Transforms/Instrumentation/PGOMemOPSizeOpt.cpp
The file was modifiedllvm/lib/ProfileData/InstrProfWriter.cpp
The file was modifiedllvm/include/llvm/ProfileData/InstrProfWriter.h
The file was modifiedllvm/lib/ProfileData/InstrProf.cpp
The file was addedllvm/test/Transforms/PGOProfile/consecutive-zeros.ll
The file was modifiedllvm/test/Transforms/PGOProfile/memop_size_opt.ll
Commit 6740694742165c03e074f19141f58a8df5a887ec by eschweitz
[flang][fir][NFC] remove dead code

Removes unused function from FatalError.h.

Differential revision: https://reviews.llvm.org/D97328
The file was modifiedflang/include/flang/Optimizer/Support/FatalError.h
Commit 17fa9198471eb559aa772df92484516aee1dbf87 by ajcbik
[mlir][sparse] incorporate vector index into address computation

When computing dense address, a vectorized index must be accounted
for properly. This bug was formerly undetected because we get 0 * prev + i
in most cases, which folds away the scalar part. Now it works for all cases.

Reviewed By: bixia

Differential Revision: https://reviews.llvm.org/D97317
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/Sparsification.cpp
The file was modifiedmlir/test/Dialect/Linalg/sparse_vector.mlir
Commit 979ca1c05f83114483caec3e6d1b75daae86da79 by jgorbe
Defer the decision whether to use the CU or TU index until after reading the unit header.

In DWARF v4 compile units go in .debug_info and type units go in
.debug_types. However, in v5 both kinds of units are in .debug_info.
Therefore we can't decide whether to use the CU or TU index just by
looking at which section we're reading from. We have to wait until we
have read the unit type from the header.

Differential Revision: https://reviews.llvm.org/D96194
The file was modifiedlldb/source/Plugins/SymbolFile/DWARF/DWARFDebugInfo.cpp
The file was modifiedlldb/source/Plugins/SymbolFile/DWARF/DWARFUnit.h
The file was addedlldb/test/Shell/SymbolFile/DWARF/dwarf5_tu_index_abbrev_offset.s
The file was modifiedlldb/source/Plugins/SymbolFile/DWARF/DWARFUnit.cpp
Commit 7f9d5d6e444c91ce6f2e377b312ac573dfc6779a by markus.boeck02
[Driver][Windows] Support per-target runtimes dir layout for profile instr generate

When targeting a MSVC triple, --dependant-libs with the name of the clang runtime library for profiling is added to the command line args. In it's current implementations clang_rt.profile-<ARCH> is chosen as the name. When building a distribution using LLVM_ENABLE_PER_TARGET_RUNTIME_DIR this fails, due to the runtime file names not having an architecture suffix in the filename.

This patch refactors getCompilerRT and getCompilerRTBasename to always consider per-target runtime directories. getCompilerRTBasename now simply returns the filename component of the path found by getCompilerRT

Differential Revision: https://reviews.llvm.org/D96638
The file was modifiedclang/lib/Driver/ToolChain.cpp
The file was modifiedclang/include/clang/Driver/ToolChain.h
The file was modifiedclang/test/Driver/instrprof-ld.c
The file was modifiedclang/test/Driver/cl-options.c
The file was modifiedclang/test/Driver/sanitizer-ld.c
The file was modifiedclang/lib/Driver/ToolChains/BareMetal.h
The file was modifiedclang/test/Driver/fsanitize.c
The file was modifiedclang/lib/Driver/ToolChains/BareMetal.cpp
Commit 039f79c78cfa2c0d0d61de117ff46aa43cb5e831 by richard
[SEMA] Added warn_decl_shadow support for structured bindings

https://bugs.llvm.org/show_bug.cgi?id=40858

CheckShadow is now called for each binding in the structured binding to make sure it does not shadow any other variable in scope. This does use a custom implementation of getShadowedDeclaration though because a BindingDecl is not a VarDecl

Added a few unit tests for this. In theory though all the other shadow unit tests should be duplicated for the structured binding variables too but whether it is probably not worth it as they use common code. The MyTuple and std interface code has been copied from live-bindings-test.cpp

Reviewed By: rsmith

Differential Revision: https://reviews.llvm.org/D96147
The file was modifiedclang/test/SemaCXX/warn-shadow.cpp
The file was modifiedclang/include/clang/Basic/DiagnosticSemaKinds.td
The file was modifiedclang/lib/Sema/SemaDecl.cpp
The file was modifiedclang/docs/ReleaseNotes.rst
The file was modifiedclang/include/clang/Sema/Sema.h
The file was modifiedclang/lib/Sema/SemaDeclCXX.cpp
Commit e844f24a278bf4b3622fb969d06e7b771a6a2aca by Matthew.Arsenault
AMDGPU: Use aligned vgprs/agprs in gfx90a mir tests

These would fail a verifier check in a future change.
The file was modifiedllvm/test/CodeGen/AMDGPU/waitcnt-agpr.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/mai-hazards-gfx90a.mir
Commit 8fa2bbaed9252b217105ea332be8a0a85492099b by david.green
[ARM] Mir test for pre/postinc ldstopt combines. NFC
The file was addedllvm/test/CodeGen/Thumb2/store-prepostinc.mir
The file was addedllvm/test/CodeGen/ARM/store-prepostinc.mir
Commit 65a3197a8fa2e5d1deb8707bda13ebd21e1dedb3 by riddleriver
[mlir] Refactor InterfaceMap to use a sorted vector of interfaces, as opposed to a DenseMap

A majority of operations have a very small number of interfaces, which means that the cost of using a hash map is generally larger for interface lookups than just a binary search. In the future when there are a number of operations with large amounts of interfaces, we can switch to a hybrid approach that optimizes lookups based on the number of interfaces. For now, however, a binary search is the best approach.

This dropped compile time on a largish TF MLIR module by 20%(half a second).

Differential Revision: https://reviews.llvm.org/D96085
The file was modifiedmlir/include/mlir/Support/InterfaceSupport.h
The file was modifiedmlir/include/mlir/IR/OperationSupport.h
The file was modifiedmlir/lib/IR/Operation.cpp
Commit abd3c6f24c823be6fb316b501482d8637c4a0724 by riddleriver
[mlir][Inliner] Use llvm::parallelForEach instead of llvm::parallelTransformReduce

llvm::parallelTransformReduce does not schedule work on the caller thread, which becomes very costly for
the inliner where a majority of SCCs are small, often ~1 element. The switch to llvm::parallelForEach solves this,
and also aligns the implementation with the PassManager (which realistically should share the same implementation).

This change dropped compile time on an internal benchmark by ~1(25%) second.

Differential Revision: https://reviews.llvm.org/D96086
The file was modifiedmlir/lib/Transforms/Inliner.cpp
Commit 445f4e74841e87da06743a4c126b09c9b9b05124 by aheejin
[WebAssembly] Disable wasm.lsda() optimization in WasmEHPrepare

In every catchpad except `catch (...)`, we add a call to
`_Unwind_CallPersonality`, which is a wapper to call the personality
function. (In most of other Itanium-based architectures the call is done
from libunwind, but in wasm we don't have the control over the VM.)
Because the personatlity function is called to figure out whether the
current exception is a type we should catch, such as `int` or
`SomeClass&`, `catch (...)` does not need the personality function call.
For the same reason, all cleanuppads don't need it.

When we call `_Unwind_CallPersonality`, we store some necessary info in
a data structure called `__wasm_lpad_context` of type
`_Unwind_LandingPadContext`, which is defined  in the wasm's port of
libunwind in Emscripten. Also the personality wrapper function returns
some info (selector and the caught pointer) in that data structure, so
it is used as a medium for communication.

One of the info we need to store is the address for LSDA info for the
current function. `wasm.lsda()` intrinsic returns that address. (This
intrinsic will be lowered to a symbol that points to the LSDA address.)
The simpliest thing is call `wasm.lsda()` every time we need to call
`_Unwind_CallPersonality` and store that info in `__wasm_lpad_context`
data structure. But we tried to be better than that (D77423 and some
more previous CLs), so if catchpad A dominates catchpad B and catchpad A
is not `catch (...)`, we didn't insert `wasm.lsda()` call in catchpad B,
thinking that the LSDA address is the same for a single function and we
already visited catchpad A and `__wasm_lpad_context.lsda` field would
already have that value.

But this can be incorrect if there is a call to another function, which
also can have the personality function and LSDA, between catchpad A and
catchpad B, because `__wasm_lpad_context` is a globally defined
structure and the callee function will overwrite its `lsda` field.

So in this CL we don't try to do any optimizaions on adding
`wasm.lsda()` call; we store the result of `wasm.lsda()` every time we
call `_Unwind_CallPersonality`. We can do some complicated analysis,
like checking if there is a function call between the dominating
catchpad and the current catchpad, but at this time it seems overkill.

This deletes three tests because they all tested `wasm.ldsa()` call
optimization.

Fixes https://github.com/emscripten-core/emscripten/issues/13548.

Reviewed By: tlively

Differential Revision: https://reviews.llvm.org/D97309
The file was modifiedllvm/lib/CodeGen/WasmEHPrepare.cpp
The file was modifiedllvm/test/CodeGen/WebAssembly/wasmehprepare.ll
Commit 4691405ba983d7b1efc3e72d17d09c1a497afe90 by Amara Emerson
Fix a range-loop-analysis warning.
The file was modifiedllvm/lib/CodeGen/RDFLiveness.cpp
Commit 97a304cc8f949e40693d63b855b4b24bc81fa729 by mvanotti
[scan-build-py] Add sarif-html support in scan-build-py

Update scan-build-py to be able to trigger sarif-html output format in clang static analyzer.

NOTE: testcase `test_sarif_and_html_creates_sarif_and_html_reports` will fail if the default clang does not have change https://reviews.llvm.org/D96389 . This can be remediated by pointing the default clang in arguments.py to a locally built clang. I was unable to figure out where these particular tests for scan-build-py are being invoked (aside from manually), so any help there would be greatly appreciated.

Reviewed By: aabbaabb, xazax.hun

Differential Revision: https://reviews.llvm.org/D96570
The file was modifiedclang/tools/scan-build-py/libscanbuild/report.py
The file was modifiedclang/tools/scan-build-py/tests/functional/cases/test_from_cdb.py
The file was modifiedclang/tools/scan-build-py/libscanbuild/arguments.py
The file was modifiedclang/tools/scan-build-py/libscanbuild/analyze.py
Commit ea8c6375e3330f181105106b3adb84ff9fa76a7c by aheejin
[WebAssembly] Fix incorrect grouping and sorting of exceptions

This CL is not big but contains changes that span multiple analyses and
passes. This description is very long because it tries to explain basics
on what each pass/analysis does and why we need this change on top of
that. Please feel free to skip parts that are not necessary for your
understanding.

---

`WasmEHFuncInfo` contains the mapping of <EH pad, the EH pad's next
unwind destination>. The value (unwind dest) here is where an exception
should end up when it is not caught by the key (EH pad). We record this
info in WasmEHPrepare to fix catch mismatches, because the CFG itself
does not have this info. A CFG only contains BBs and
predecessor-successor relationship between them, but in `WasmEHFuncInfo`
the unwind destination BB is not necessarily a successor or the key EH
pad BB. Their relationship can be intuitively explained by this C++ code
snippet:
```
try {
  try {
    foo();
  } catch (int) { // EH pad
    ...
  }
} catch (...) {   // unwind destination
}
```
So when `foo()` throws, it goes to `catch (int)` first. But if it is not
caught by it, it ends up in the next unwind destination `catch (...)`.
This unwind destination is what you see in `catchswitch`'s
`unwind label %bb` part.

---

`WebAssemblyExceptionInfo` groups exceptions so that they can be sorted
continuously together in CFGSort, as we do for loops. What this analysis
does is very simple: it creates a single `WebAssemblyException` per EH
pad, and all BBs that are dominated by that EH pad are included in this
exception. We also identify subexception relationship in this way: if
EHPad A domiantes EHPad B, EHPad B's exception is a subexception of
EHPad A's exception.

This simple rule turns out to be incorrect in some cases. In
`WasmEHFuncInfo`, if EHPad A's unwind destination is EHPad B, it means
semantically EHPad B should not be included in EHPad A's exception,
because it does not make sense to rethrow/delegate to an inner scope.
This is what happened in CFGStackify as a result of this:
```
try
  try
  catch
    ...   <- %dest_bb is among here!
  end
delegate %dest_bb
```

So this patch adds a phase in `WebAssemblyExceptionInfo::recalculate` to
make sure excptions' unwind destinations are not subexceptions of
their unwind sources in `WasmEHFuncInfo`.

But this alone does not prevent `dest_bb` in the example above from
being sorted within the inner `catch`'s exception, even if its exception
is not a subexception of that `catch`'s exception anymore, because of
how CFGSort works, which will be explained below.

---

CFGSort places BBs within the same `SortRegion` (loop or exception)
continuously together so they can be demarcated with `loop`-`end_loop`
or `catch`-`end_try` in CFGStackify.

`SortRegion` is a wrapper for one of `MachineLoop` or
`WebAssemblyException`. `SortRegionInfo` already does some complicated
things because there discrepancies between those two data structures.
`WebAssemblyException` is what we control, and it is defined as an EH
pad as its header and BBs dominated by the header as its BBs (with a
newly added exception of unwind destinations explained in the previous
paragraph). But `MachineLoop` is an LLVM data structure and uses the
standard loop detection algorithm. So by the algorithm, BBs that are 1.
dominated by the loop header and 2. have a path back to its header.
Because of the second condition, many BBs that are dominated by the loop
header are not included in the loop. So BBs that contain `return` or
branches to outside of the loop are not technically included in
`MachineLoop`, but they can be sorted together with the loop with no
problem.

Maybe to relax the condition, in CFGSort, when we are in a `SortRegion`
we allow sorting of not only BBs that belong to the current innermost
region but also BBs that are by the current region header.
(This was written this way from the first version written by Dan, when
only loops existed.) But now, we have cases in exceptions when EHPad B
is the unwind destination for EHPad A, even if EHPad B is dominated by
EHPad A it should not be included in EHPad A's exception, and should not
be sorted within EHPad A.

One way to make things work, at least correctly, is change `dominates`
condition to `contains` condition for `SortRegion` when sorting BBs, but
this will change compilation results for existing non-EH code and I
can't be sure it will not degrade performance or code size. I think it
will degrade performance because it will force many BBs dominated by a
loop, which don't have the path back to the header, to be placed after
the loop and it will likely to create more branches and blocks.

So this does a little hacky check when adding BBs to `Preferred` list:
(`Preferred` list is a ready list. CFGSort maintains ready list in two
priority queues: `Preferred` and `Ready`. I'm not very sure why, but it
was written that way from the beginning. BBs are first added to
`Preferred` list and then some of them are pushed to `Ready` list, so
here we only need to guard condition for `Preferred` list.)

When adding a BB to `Preferred` list, we check if that BB is an unwind
destination of another BB. To do this, this adds the reverse mapping,
`UnwindDestToSrc`, and getter methods to `WasmEHFuncInfo`. And if the BB
is an unwind destination, it checks if the current stack of regions
(`Entries`) contains its source BB by traversing the stack backwards. If
we find its unwind source in there, we add the BB to its `Deferred`
list, to make sure that unwind destination BB is added to `Preferred`
list only after that region with the unwind source BB is sorted and
popped from the stack.

---

This does not contain a new test that crashes because of this bug, but
this fix changes the result for one of existing test case. This test
case didn't crash because it fortunately didn't contain `delegate` to
the incorrectly placed unwind destination BB.

Fixes https://github.com/emscripten-core/emscripten/issues/13514.

Reviewed By: dschuff, tlively

Differential Revision: https://reviews.llvm.org/D97247
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyExceptionInfo.h
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyCFGSort.cpp
The file was modifiedllvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
The file was modifiedllvm/include/llvm/CodeGen/WasmEHFuncInfo.h
The file was modifiedllvm/test/CodeGen/WebAssembly/cfg-stackify-eh.ll
The file was modifiedllvm/unittests/Target/WebAssembly/WebAssemblyExceptionInfoTest.cpp
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyExceptionInfo.cpp
Commit 1d7f1d15c517db2bde30228dfdcb17f6471f7916 by matthew.voss
[LTO] Fix test failures caused by 6da7d3141651

Adds "REQUIRES: asserts", since the test uses debug messages
The file was modifiedllvm/test/Transforms/PGOProfile/consecutive-zeros.ll
Commit a05aa0dd5ef8f5633d49192f32a3d0b4653b8a0c by jianzhouzh
[dfsan] Update memset and dfsan_(set|add)_label with origin tracking

This is a part of https://reviews.llvm.org/D95835.

Reviewed-by: morehouse

Differential Revision: https://reviews.llvm.org/D97302
The file was modifiedllvm/test/Instrumentation/DataFlowSanitizer/basic.ll
The file was addedllvm/test/Instrumentation/DataFlowSanitizer/origin_mem_intrinsic.ll
The file was modifiedcompiler-rt/lib/dfsan/dfsan.cpp
The file was modifiedllvm/test/Instrumentation/DataFlowSanitizer/memset.ll
The file was modifiedllvm/lib/Transforms/Instrumentation/DataFlowSanitizer.cpp
Commit b79507a4acad4114ab0fde3babd81551b214e65b by lntue
[libc] Add exhaustive test for sqrtf.

Differential Revision: https://reviews.llvm.org/D96985
The file was addedlibc/test/src/math/exhaustive/sqrtf_test.cpp
The file was addedlibc/test/src/math/exhaustive/CMakeLists.txt
The file was modifiedlibc/test/src/math/CMakeLists.txt
The file was modifiedlibc/test/CMakeLists.txt
The file was modifiedlibc/cmake/modules/LLVMLibCTestRules.cmake
Commit dbb131d53aacabdf5d85299e447a970a0280b127 by sivachandra
[libc] Add a standalone flavor of an equivalent of std::string_view.

This class is to serve as a replacement for llvm::StringRef as part of
the plans to limit dependency on other parts of LLVM. One use of
llvm::StringRef in MPFRWrapper has been replaced with the new class.

Reviewed By: lntue

Differential Revision: https://reviews.llvm.org/D97330
The file was addedlibc/test/utils/CPP/stringview_test.cpp
The file was modifiedlibc/utils/CPP/CMakeLists.txt
The file was modifiedlibc/utils/MPFRWrapper/MPFRUtils.cpp
The file was addedlibc/utils/CPP/StringView.h
The file was modifiedlibc/test/utils/CPP/CMakeLists.txt
The file was modifiedlibc/utils/MPFRWrapper/CMakeLists.txt
Commit 1a35a1b0748639a0014eb8aec1a9c36e330c5316 by kai.wang
[RISCV] Add vadd with mask and without mask builtin.

Demonstrate how to add RISC-V V builtins and lower them to IR intrinsics for V extension.

Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com>
Co-Authored-by: Hsiangkai Wang <kai.wang@sifive.com>

Differential Revision: https://reviews.llvm.org/D93446
The file was modifiedclang/lib/CodeGen/CodeGenFunction.h
The file was modifiedclang/lib/Sema/SemaChecking.cpp
The file was modifiedclang/include/clang/Basic/DiagnosticSemaKinds.td
The file was modifiedclang/include/clang/module.modulemap
The file was modifiedclang/lib/CodeGen/CGBuiltin.cpp
The file was addedclang/test/CodeGen/RISCV/vadd.c
The file was modifiedclang/include/clang/Basic/TargetBuiltins.h
The file was modifiedclang/include/clang/Sema/Sema.h
The file was modifiedclang/lib/Basic/Targets/RISCV.h
The file was addedclang/include/clang/Basic/BuiltinsRISCV.def
The file was modifiedclang/lib/Basic/Targets/RISCV.cpp
Commit 0a5949dcfa31d599353fb4ccf4d207bdae7c7281 by tejohnson
[WPD] Fix handling of pure virtual base class

The fix in 3c4c205060c9398da705eb71b63ddd8a04999de9 caused an assert in
the case of a pure virtual base class. In that case, the vTableFuncs
list on the summary will be empty, so we were hitting the new assert
that the linkage type was not available_externally.

In the case of pure virtual, we do not want to assert, and additionally
need to set VS so that we don't treat it conservatively and quit the
analysis of the type id early.

This exposed a pre-existing issue where we were not updating the vcall
visibility on pure virtual functions when whole program visibility was
specified. We were skipping updating the visibility on any global vars
that didn't have any vTableFuncs, which meant all pure virtual were not
updated, and the later analysis would block any devirtualization of
calls that had a type id used on those pure virtual vtables (see the
handling in the other code modified in this patch). Simply remove that
check. It will mean that we may update the vcall visibility on global
vars that aren't vtables, but that setting is ignored for any global
vars that didn't have type metadata anyway.

Added a new test case that asserted without removing the assert, and
that requires the other fixes in this patch (updateVCallVisibilityInIndex
and not skipping all vtables without virtual funcs) to get a successful
devirtualization with index-only WPD. I added cases to test hybrid and
regular LTO for completeness, although those already worked without the
fixes here.

With this final fix, a clang multistage bootstrap with WPD builds and
runs all tests successfully.

Differential Revision: https://reviews.llvm.org/D97126
The file was modifiedllvm/lib/Transforms/IPO/WholeProgramDevirt.cpp
The file was addedllvm/test/ThinLTO/X86/devirt_pure_virtual_base.ll
Commit 3adb89bb9f8e73c82787babb2f877fece7394770 by i
[ThinLTO] Make cloneUsedGlobalVariables deterministic

Iterating on `SmallPtrSet<GlobalValue *, 8>` with more than 8 elements
is not deterministic. Use a SmallVector instead because `Used` is guaranteed to contain unique elements.

While here, decrease inline element counts from 8 to 4. The number of
`llvm.used`/`llvm.compiler.used` elements is usually 0 or 1. For full
LTO/hybrid LTO, the number may be large, so we need to be careful.

According to tejohnson's analysis https://reviews.llvm.org/D97128#2582399 , 4 is
good for a large project with WholeProgramDevirt, when available_externally
vtables are placed in the llvm.compiler.used set.

Differential Revision: https://reviews.llvm.org/D97128
The file was modifiedllvm/lib/Transforms/IPO/ThinLTOBitcodeWriter.cpp
The file was modifiedllvm/include/llvm/IR/Module.h
The file was modifiedllvm/lib/IR/Module.cpp
Commit ed02f52d288fb4d8f9049868afa6af84a980cbc3 by i
Fix unstable SmallPtrSet iteration issues due to collectUsedGlobalVariables

While here, decrease inline element counts from 8 to 4. See D97128 for the choice.

Depends on D97128 (which added a new SmallVecImpl overload for collectUsedGlobalVariables).

Reviewed By: tejohnson

Differential Revision: https://reviews.llvm.org/D97139
The file was modifiedllvm/lib/Transforms/IPO/LowerTypeTests.cpp
The file was modifiedllvm/lib/Bitcode/Writer/BitcodeWriter.cpp
Commit ef312951fd6b4a255baf3cff27439c9ed8751651 by i
collectUsedGlobalVariables: migrate SmallPtrSetImpl overload to SmallVecImpl overload after D97128

And delete the SmallPtrSetImpl overload.

While here, decrease inline element counts from 8 to 4. See D97128 for the choice.

Reviewed By: tejohnson

Differential Revision: https://reviews.llvm.org/D97257
The file was modifiedllvm/lib/Transforms/IPO/Internalize.cpp
The file was modifiedllvm/include/llvm/Transforms/Utils/FunctionImportUtils.h
The file was modifiedllvm/lib/Object/IRSymtab.cpp
The file was modifiedllvm/lib/Analysis/ModuleSummaryAnalysis.cpp
The file was modifiedllvm/include/llvm/IR/Module.h
The file was modifiedllvm/lib/IR/Module.cpp
The file was modifiedllvm/lib/Transforms/IPO/GlobalOpt.cpp
Commit daf7d7f0dc283873f40f3500b20f02bc2cde701d by Jessica Paquette
[AArch64][GlobalISel] Correct function evaluation order in applyINS

The order in which the nested calls to Builder.buildWhatever are
evaluated in differs between GCC and Clang.

This caused a bot failure because the MIR in the testcase was
coming out in a different order than expected.

Rather than using nested calls, pull them out in order to fix the
order of evaluation.
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
Commit af4451eb4f38ce492ca38add91c8378f32b93eca by erich.keane
[NFC] Make TrailingObjects non-copyable/non-movable

This got me pretty recently... TrailingObjects cannot be copied or
moved, since they need to be pre-allocated. This patch deletes the copy
and move operations (plus re-adds the default ctor).

Differential Revision: https://reviews.llvm.org/D97324
The file was modifiedllvm/include/llvm/Support/TrailingObjects.h
Commit 16a50c9e642fd085e5ceb68c403b71b5b2e0607c by riddleriver
[mlir][Inliner] Keep the number of async pass managers constant

This prevents a bug in the pass instrumentation implementation where the main thread would end up with a different pass manager in different runs of the pass.
The file was modifiedmlir/lib/Transforms/Inliner.cpp
Commit 3c4cdd0b6a6fd760707be9b5dec32378ec55c549 by kern.handa
[mlir] ExecutionEngine needs special handling for COFF binaries

Reviewed By: mehdi_amini

Differential Revision: https://reviews.llvm.org/D97141
The file was modifiedmlir/lib/ExecutionEngine/ExecutionEngine.cpp
Commit ab5b00ada9e77437ed2c76f73cfb8481bb9826a5 by thakis
Revert "[Driver][Windows] Support per-target runtimes dir layout for profile instr generate"

This reverts commit 7f9d5d6e444c91ce6f2e377b312ac573dfc6779a.
Breaks check-clang everywhere, see https://reviews.llvm.org/D96638#2583608
The file was modifiedclang/lib/Driver/ToolChain.cpp
The file was modifiedclang/test/Driver/cl-options.c
The file was modifiedclang/test/Driver/sanitizer-ld.c
The file was modifiedclang/include/clang/Driver/ToolChain.h
The file was modifiedclang/lib/Driver/ToolChains/BareMetal.h
The file was modifiedclang/lib/Driver/ToolChains/BareMetal.cpp
The file was modifiedclang/test/Driver/fsanitize.c
The file was modifiedclang/test/Driver/instrprof-ld.c
Commit 56d228a14e3631de157ae98dd61d21193e4502d5 by aqjune
[SimplifyCFG] Update passingValueIsAlwaysUndefined to check more attributes

This is a simple patch to update SimplifyCFG's passingValueIsAlwaysUndefined to inspect more attributes.

A new function `CallBase::isPassingUndefUB` checks attributes that imply noundef.

Reviewed By: spatel

Differential Revision: https://reviews.llvm.org/D97244
The file was modifiedllvm/include/llvm/IR/InstrTypes.h
The file was modifiedllvm/lib/Transforms/Utils/SimplifyCFG.cpp
The file was modifiedllvm/test/Transforms/SimplifyCFG/UnreachableEliminate.ll
Commit 98c6110d9bdda166a6093f8fdf1320b5f477ecbe by tu.da.wei
[LoopNest] Use `getUniqueSuccessor()` instead when checking empty blocks

Blocks that contain only a single branch instruction to the next block can be skipped in analyzing the loop-nest structure.
This is currently done by `getSingleSuccessor()`.
However, the branch instruction might have multiple targets which happen to all be the same.
In this case, the block should still be considered as empty and skipped.

An example is `test/Transforms/LoopInterchange/update-condbranch-duplicate-successors.ll` (the LIT test for this patch is modified from it as well).

Reviewed By: Whitney

Differential Revision: https://reviews.llvm.org/D97286
The file was modifiedllvm/lib/Analysis/LoopNestAnalysis.cpp
The file was addedllvm/test/Analysis/LoopNestAnalysis/duplicate-successors.ll
Commit c4a91444689455a35db1e7f50bcd876a3eb86126 by Adrian Prantl
Add more historic DWARF vendor extensions

The maintainer of libdwarf kindly provided this patch with a bunch of
historic DWARF extensions that are missing from Dwarf.def. This list
is helpful to avoid potential conflicts in the user-defined vendor
extension space in the future.

Patch by David Anderson!

Differential Revision: https://reviews.llvm.org/D97242
The file was modifiedllvm/include/llvm/BinaryFormat/Dwarf.def
The file was modifiedllvm/include/llvm/BinaryFormat/Dwarf.h
Commit be5d92e37e4fe0b7ba2f5658fa828c1c39988374 by czhengsz
[Debug-Info][NFC] move emitDwarfUnitLength to MCStreamer class

We may need to do some customization for DWARF unit length in DWARF
section headers for some targets for some code generation path.

For example, for XCOFF in assembly path, AIX assembler does not require
the debug section containing its debug unit length in the header.

Move emitDwarfUnitLength to MCStreamer class so that we can do
customization in different Streamers

Reviewed By: ikudrin

Differential Revision: https://reviews.llvm.org/D95932
The file was modifiedllvm/lib/MC/MCStreamer.cpp
The file was modifiedllvm/include/llvm/MC/MCStreamer.h
The file was modifiedllvm/unittests/CodeGen/AsmPrinterDwarfTest.cpp
The file was modifiedllvm/lib/CodeGen/AsmPrinter/AsmPrinterDwarf.cpp
The file was modifiedllvm/include/llvm/CodeGen/AsmPrinter.h
Commit 59f0e4627a5e8789c9ab997cd13f96600848fea8 by riddleriver
[mlir][Inliner] Don't optimize callees in async mode if there is only one to optimize

This avoids unnecessary async overhead in situations that won't benefit from it.
The file was modifiedmlir/lib/Transforms/Inliner.cpp
Commit e5d780e049c275b628461c043fa5953ecd4f16e0 by jezng
[lld-macho] Use full input file name in invalid relocation error message

Just something I noticed while debugging arm relocations...

Reviewed By: #lld-macho, thakis

Differential Revision: https://reviews.llvm.org/D97078
The file was modifiedlld/MachO/InputFiles.cpp
The file was modifiedlld/test/MachO/invalid/invalid-relocation-pcrel.yaml
Commit 5e851733c5b603bec962bb4c5cf9d5cc93d88175 by jezng
[lld-macho] Fix semantics & add tests for ARM64 GOT/TLV relocs

I've adjusted the RelocAttrBits to better fit the semantics of
the relocations. In particular:

1. *_UNSIGNED relocations are no longer marked with the `TLV` bit, even
   though they can occur within TLV sections. Instead the `TLV` bit is
   reserved for relocations that can reference thread-local symbols, and
   *_UNSIGNED relocations have their own `UNSIGNED` bit. The previous
   implementation caused TLV and regular UNSIGNED semantics to be
   conflated, resulting in rebase opcodes being incorrectly emitted for TLV
   relocations.

2. I've added a new `POINTER` bit to denote non-relaxable GOT
   relocations. This distinction isn't important on x86 -- the GOT
   relocations there are either relaxable or non-relaxable loads -- but
   arm64 has `GOT_LOAD_PAGE21` which loads the page that the referent
   symbol is in (regardless of whether the symbol ends up in the GOT). This
   relocation must reference a GOT symbol (so must have the `GOT` bit set)
   but isn't itself relaxable (so must not have the `LOAD` bit). The
   `POINTER` bit is used for relocations that *must* reference a GOT
   slot.

3. A similar situation occurs for TLV relocations.

4. ld64 supports both a pcrel and an absolute version of
   ARM64_RELOC_POINTER_TO_GOT. But the semantics of the absolute version
   are pretty weird -- it results in the value of the GOT slot being
   written, rather than the address. (That means a reference to a
   dynamically-bound slot will result in zeroes being written.) The
   programs I've tried linking don't use this form of the relocation, so
   I've dropped our partial support for it by removing the relevant
   RelocAttrBits.

Reviewed By: alexshap

Differential Revision: https://reviews.llvm.org/D97031
The file was modifiedlld/MachO/Target.cpp
The file was modifiedlld/MachO/Arch/X86_64.cpp
The file was addedlld/test/MachO/arm64-reloc-got-load.s
The file was modifiedlld/MachO/Target.h
The file was modifiedlld/MachO/Writer.cpp
The file was addedlld/test/MachO/arm64-reloc-tlv-load.s
The file was modifiedlld/MachO/Arch/ARM64.cpp
The file was modifiedlld/MachO/InputFiles.cpp
The file was modifiedlld/MachO/InputSection.cpp
The file was addedlld/test/MachO/arm64-reloc-pointer-to-got.s
Commit 4752cdc9a20abb5fbb2a255011417b8a77e4c31e by jezng
[lld-macho] Check for arch compatibility when loading ObjFiles and TBDs

The silent failures had confused me a few times.

I haven't added a similar check for platform yet as we don't yet have logic to
infer the platform automatically, and so adding that check would require
updating dozens of test files.

Reviewed By: #lld-macho, thakis, alexshap

Differential Revision: https://reviews.llvm.org/D97209
The file was addedlld/test/MachO/invalid/incompatible-arch-tapi.s
The file was addedlld/test/MachO/invalid/incompatible-arch.s
The file was modifiedlld/test/MachO/header.s
The file was addedlld/test/MachO/invalid/Inputs/libincompatible.tbd
The file was modifiedlld/MachO/InputFiles.cpp
The file was modifiedlld/test/MachO/Inputs/MacOSX.sdk/usr/lib/libc++.tbd
Commit 4a5e111aea7ac78190211a2549f8d0d53ee2f01d by jezng
[lld-macho] Better deduplication of personality pointers

{D95809} introduced a mechanism for synthetic symbol creation of personality
pointers. When multiple section relocations referred to the same personality
pointer, it would deduplicate them. However, it neglected to consider that we
could have symbol relocations that also refer to the same personality pointer.
This diff fixes it.

In practice, this mix of relocations arises when there is a statically-linked
personality routine that is referenced from multiple object files. Within the
same object file, it will be referred to via section relocations, but
(obviously) other object files will refer to it via symbol relocations. Failing
to deduplicate these references resulted in us going over the
3-personality-pointer limit when linking some larger applications.

Fixes llvm.org/PR48389.

Reviewed By: #lld-macho, thakis, alexshap

Differential Revision: https://reviews.llvm.org/D97245
The file was modifiedlld/test/MachO/compact-unwind.s
The file was modifiedlld/MachO/UnwindInfoSection.cpp
Commit f14a14dd2564703db02f80c00db8ae492b594f77 by thakis
Revert "Add more historic DWARF vendor extensions"

This reverts commit c4a91444689455a35db1e7f50bcd876a3eb86126.
Breaks check-llvm everywhere, see https://reviews.llvm.org/D97242#2583716
The file was modifiedllvm/include/llvm/BinaryFormat/Dwarf.h
The file was modifiedllvm/include/llvm/BinaryFormat/Dwarf.def
Commit 71a39862475e1d192d41d335452267590103acfc by czhengsz
[XCOFF] add C_FILE symbol at index 0 of symbol table.

This is for XCOFF DWARF support.

Seems when DWARF debug is enable, symbol 0 has special usage
for AIX binder. At least, symbol 0 can not be the .text
section. Otherwise, we get some binding time error.

Add correct C_FILE symbol at index 0 here to make AIX binder
work.

Reviewed By: hubert.reinterpretcast

Differential Revision: https://reviews.llvm.org/D97117
The file was modifiedllvm/test/CodeGen/PowerPC/aix-xcoff-data.ll
The file was modifiedllvm/test/CodeGen/PowerPC/aix-xcoff-reloc.ll
The file was modifiedllvm/test/CodeGen/PowerPC/aix-xcoff-rodata.ll
The file was modifiedllvm/lib/MC/XCOFFObjectWriter.cpp
The file was modifiedllvm/test/CodeGen/PowerPC/aix-weak.ll
The file was modifiedllvm/test/CodeGen/PowerPC/aix-overflow-toc.py
The file was modifiedllvm/test/CodeGen/PowerPC/aix-xcoff-lcomm.ll
The file was modifiedllvm/test/CodeGen/PowerPC/aix-func-dsc-gen.ll
The file was modifiedllvm/test/CodeGen/PowerPC/aix-user-defined-memcpy.ll
The file was modifiedllvm/test/CodeGen/PowerPC/aix-xcoff-data-sections.ll
The file was modifiedllvm/test/CodeGen/PowerPC/aix-extern.ll
The file was modifiedllvm/test/CodeGen/PowerPC/aix-llvm-intrinsic.ll
The file was modifiedllvm/test/CodeGen/PowerPC/aix-xcoff-symbol-rename.ll
The file was modifiedllvm/test/CodeGen/PowerPC/aix-extern-weak.ll
The file was modifiedllvm/test/CodeGen/PowerPC/aix-xcoff-explicit-section.ll
Commit eb55203e009ec98351f2be6e5655b7178b604920 by Amara Emerson
[AArch64][GlobalISel][PostSelectOpt] Constrain reg operands after mutating instructions.

The non-flag setting variants of instructions may have different regclass
requirements. If so, we need to constrain them.

Differential Revision: https://reviews.llvm.org/D97343
The file was addedllvm/test/CodeGen/AArch64/GlobalISel/postselectopt-constrain-new-regop.mir
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64PostSelectOptimize.cpp
Commit a3ce7f5cd2ae236bec7752e343f4b63ddda7ebe7 by Yaxun.Liu
[HIP] Fix managed variable linkage

Currently managed variables are emitted as undefined symbols, which
causes difficulty for diagnosing undefined symbols for non-managed
variables.

This patch transforms managed variables in device compilation so that
they can be emitted as normal variables.

Reviewed by: Artem Belevich

Differential Revision: https://reviews.llvm.org/D96195
The file was modifiedllvm/lib/IR/ReplaceConstant.cpp
The file was modifiedclang/lib/CodeGen/CGCUDARuntime.h
The file was modifiedclang/test/CodeGenCUDA/device-var-linkage.cu
The file was modifiedclang/lib/CodeGen/CodeGenModule.cpp
The file was modifiedclang/lib/CodeGen/CGCUDANV.cpp
The file was modifiedclang/test/CodeGenCUDA/managed-var.cu