SuccessChanges

Summary

  1. [Zorg][OpenMP] Add CUDA offloading worker. (details)
  2. [PowerPC] Change RHEL buildbot to unifiedtreebuilder (details)
Commit e4aa8a2773fe76c427a91229f021ab067eafc8e7 by llvm-zorg
[Zorg][OpenMP] Add CUDA offloading worker.

This worker tests OpenMP offloading for the x86_64 and NVIDIA GPU. In
addition to check-openmp, it runs the SOLLVE Validation & Verification Suite
via the LLVM test-suite External builder. The builder is configured to
only warn if the SOLLVE suite fails, as it also tests features that
have not been implemented in Clang yet.

CUDA is intentionally not installed in a default location (/opt/cuda) to
resemble setups often found in computing clusters with multiple versions
of CUDA to choose from.

Reviewed By: gkistanova

Differential Revision: https://reviews.llvm.org/D101268
The file was modifiedbuildbot/osuosl/master/config/workers.py (diff)
The file was modifiedzorg/buildbot/builders/OpenMPBuilder.py (diff)
The file was modifiedbuildbot/osuosl/master/config/builders.py (diff)
Commit 69c601cb34aecc7e2dcb112cd112b6fa9a105d7f by albionapc
[PowerPC] Change RHEL buildbot to unifiedtreebuilder

The patch switches the RHEL buildbot to utilise more jobs when building, as
well as UnifiedTreeBuilder (ie, with cmake and Ninja).

Differential: https://reviews.llvm.org/D101199
The file was modifiedbuildbot/osuosl/master/config/workers.py (diff)
The file was modifiedbuildbot/osuosl/master/config/builders.py (diff)

Summary

  1. [OpenCL] Allow use of double type without extension pragma. (details)
  2. [AMDGPU] Move code sinking before structurizer (details)
  3. [SLP] restrict matching of load combine candidates (details)
  4. [X86][CostModel] X86TTIImpl::getMemoryOpCost(): rewrite vector handling again (details)
  5. CodeGen: Fix null dereference before null check (details)
  6. [X86][SSE] Replace foldShuffleOfHorizOp with generalized version in canonicalizeShuffleMaskWithHorizOp (details)
  7. [X86] Replace repeated isa/cast<ConstantSDNode> calls with single single dyn_cast<>. NFCI. (details)
  8. [TableGen] Make the NUL character invalid in .td files (details)
  9. [X86] X86TTIImpl::getInterleavedMemoryOpCostAVX2(): use getMemoryOpCost() (details)
  10. [VPlan] Register recipe for instr if the simplified value is recipe. (details)
  11. [OpenMP] Fix hidden helper + affinity (details)
  12. Revert "[TableGen] Make the NUL character invalid in .td files" (details)
  13. Fix typo "Execpt" in comments (details)
  14. [LoopInterchange] Fix legality for triangular loops (details)
  15. Revert "[AMDGPU][OpenMP] Emit textual IR for -emit-llvm -S" (details)
  16. [NFC][AMDGPU] Correct product name for gfx908 (details)
  17. [IR][AutoUpgrade] Drop align attribute from void return types (details)
  18. Produce warning for performing pointer arithmetic on a null pointer. (details)
  19. [NFC][X86] Precommit another testcase for D101944 (details)
  20. Fix branch coverage merging in FunctionCoverageSummary::get() for instantiation (details)
  21. Change Target::ReadMemory to ensure the amount of memory read from the file-cache is the amount requested. (details)
  22. Add null-pointer checks when accessing a TypeSystem's SymbolFile (details)
  23. [mlir] Use static shape knowledge when lowering memref.reshape (details)
  24. [libomptarget][nfc] Add hook to easily disable building amdgcn bclib (details)
  25. [libc++] s/_VSTD::declval/declval/g. NFCI. (details)
  26. [libc++] s/std::size_t/size_t/g. NFCI. (details)
  27. [libc++] s/_VSTD::chrono/chrono/g. NFCI. (details)
  28. [libc++] s/_VSTD::is_unsigned/is_unsigned/ in <random>. NFCI. (details)
  29. [libc++] Remove more unnecessary _VSTD:: from type names. NFCI. (details)
  30. Revert "Fix branch coverage merging in FunctionCoverageSummary::get() for instantiation" (details)
  31. [RISCV] Match trunc_vector_vl+sra_vl/srl_vl with splat shift amount to vnsra/vnsrl. (details)
  32. [X86][Codegen] Shift amount mod: sh? i64 x, (32-y) --> sh? i64 x, -(y+32) (details)
  33. [RISCV] Use fractional LMULs for fixed length types smaller than riscv-v-vector-bits-min. (details)
  34. [libcxx][tests] Fix incomplte.verify tests by disabling them on clang-10. (details)
  35. [X86][SSE] Add tests for permute(phaddw(phaddw(x,y),phaddw(z,w))) -> phaddw(phaddw(),phaddw()) folds. (details)
  36. Reland "[Coverage] Fix branch coverage merging in FunctionCoverageSummary::get() for instantiation"" (details)
  37. Revert "[ORC-RT] Add unit test infrastructure, extensible_rtti..." (details)
  38. [TextAPI] Reformat llvm_unreachable message (details)
  39. [flang] Allow large and erroneous ac-implied-do's (details)
  40. Re-apply "[ORC-RT] Add unit test infrastructure, extensible_rtti..." (details)
  41. [lld/mac] Implement -sectalign (details)
  42. [git-clang-format] Do not apply clang-format to symlinks (details)
  43. [libcxx] [test] Fix filesystem permission tests for windows (details)
  44. [mlir][ODS]: Add per-op cppNamespace. (details)
  45. [ArgumentPromotion] Fix byval alignment handling. (details)
  46. [RISCV] Prefer to lower MC_GlobalAddress operands to .Lfoo$local (details)
  47. [AArch64][GlobalISel] Support truncstorei8/i16 w/ combine to form truncating G_STOREs. (details)
  48. [GlobalOpt] Remove heap SROA (details)
  49. [X86] X86TTIImpl::getInterleavedMemoryOpCostAVX2(): canonicalize to integer type (details)
  50. [lld][WebAssembly] Convert test to assembly. NFC. (details)
  51. [clang] Support -fpic -fno-semantic-interposition for RISCV (details)
  52. [OpenMP] Use compound operators for reduction combiner if available. (details)
  53. [libc++] Run `substitutes-in-compile-flags.sh.cpp` test on Windows. (details)
  54. Add an "interrupt timeout" to Process, and pipe that through the (details)
  55. [lld][WebAssembly] Remove relocation target verification (details)
  56. [mlir] Move move capture in SparseElementsAttr::getValues (details)
  57. [NFC][LSAN] Limit the number of concurrent threads is the test (details)
  58. [AArch64][GlobaISel] Mark target generic instructions as HasNoSideEffects. (details)
  59. [PowerPC] Improve codegen for int-to-fp conversion of subword vector extract (details)
  60. [OpenMP] Changes to enable MSVC ARM64 build of libomp (details)
  61. [RISCV] Regenerate stepvector.ll. NFC (details)
  62. [hwasan] Stress test for thread creation. (details)
  63. [AMDGPU] Fix extra waitcnt being added with BUFFER_INVL2 (details)
  64. Removed unnecessary introduction of semi-colons. (details)
  65. [mlir] Elide large elements attrs when printing Operations in diagnostics (details)
  66. [mlir][tosa] Tosa elementwise broadcasting had some minor bugs (details)
  67. [InstCombine] Clean up one-hot merge optimization (NFC) (details)
  68. [RISCV] Move instruction information into the RISCVII namespace (NFC) (details)
  69. [llvm-cov] Support for v4 format in convert-for-testing (details)
  70. Revert "[LoopInterchange] Fix legality for triangular loops" (details)
  71. [AIX][TLS] Diagnose use of unimplemented TLS models (details)
  72. [JITLink] Make LinkGraph debug dumps more readable. (details)
  73. [JITLink][x86-64] Add an x86_64 PointerSize constexpr. (details)
  74. [JITLink][MachO/x86_64] Expose API for creating eh-frame fixing passes. (details)
  75. [Coverage] Support overriding compilation directory (details)
  76. [LoopInterchange] Fix legality for triangular loops (details)
  77. [clang][Fuchsia] Introduce compat multilibs (details)
  78. [JITLink] Fix bogus format string. (details)
  79. Revert "[GVN] Clobber partially aliased loads." (details)
  80. GlobalISel: Move AArch64 AssignFnVarArg to base class (details)
  81. GlobalISel: Split ValueHandler into assignment and emission classes (details)
  82. GlobalISel: Make constant fields const (details)
  83. AMDGPU: Fix assert on constant load from addrspacecasted pointer (details)
  84. GlobalISel: Don't hardcode varargs=false in resultsCompatible (details)
  85. Fix bad mangling of <data-member-prefix> for a closure in the initializer of a variable at global namespace scope. (details)
  86. Add test for PR50039. (details)
  87. Revert "Fix bad mangling of <data-member-prefix> for a closure in the initializer of a variable at global namespace scope." (details)
  88. [lld][WebAssembly] Fix for string merging + negative addends (details)
  89. This test is failing on Linux, skip while I investigate. (details)
  90. AMDGPU: Fix SILoadStoreOptimizer for gfx90a (details)
  91. Removing test... (details)
  92. [LoopInterchange] Handle lcssa PHIs with multiple predecessors (details)
  93. [NFC][msan] Move setlocale test into sanitizer_common (details)
  94. [mlir][AsmPrinter] Remove recursion while SSA naming (details)
  95. tsan: add a simple syscall test (details)
  96. tsan: mark sigwait as blocking (details)
  97. [VectorComine] Restrict single-element-store index to inbounds constant (details)
  98. tsan: declare annotations in test.h (details)
  99. sanitizer_common: fix SIG_DFL warning (details)
  100. [symbolizer] Fix leak after D96883 (details)
  101. sanitizer_common: don't write into .rodata (details)
  102. [libcxx][test] Split more debug mode tests (details)
  103. [PowerPC] [Clang] Enable float128 feature on VSX targets (details)
  104. sanitizer_common: deduplicate CheckFailed (details)
  105. [COFF] Fix ARM and ARM64 REL32 relocations to be relative to the end of the relocation (details)
  106. tsan: fix syscall test on aarch64 (details)
  107. [mlir] Support alignment in LLVM dialect GlobalOp (details)
  108. [MLIR] Enable conversion from llvm::SMLoc to mlir::Location with OpAsmParser. (details)
  109. scudo: fix CheckFailed-related build breakage (details)
  110. [libc] Simplifies multi implementations (details)
  111. [NFC][llvm-dwarfdump] Avoid passing std::string by value in collectStatsForDie() (details)
  112. Fixed llvm-objcopy to add correct symbol table for ELF with program headers. (details)
  113. [ARM] Precommit test for D101898 (details)
  114. [ARM] Prevent spilling between ldrex/strex pairs (details)
  115. Revert "[PowerPC] [Clang] Enable float128 feature on VSX targets" (details)
  116. [AMDGPU] Skip invariant loads when avoiding WAR conflicts (details)
  117. Remove Windows editline from LLDB (details)
  118. Reapply "[DebugInfo] Fix updateDbgUsersToReg to support DBG_VALUE_LIST" (details)
  119. [lldb] [Process/elf-core] Fix reading FPRs from FreeBSD/i386 cores (details)
  120. [Process/elf-core] Read PID from FreeBSD prpsinfo (details)
  121. [AArch64][SVE] Improve sve.convert.to.svbool lowering (details)
  122. [LoopVectorize] Fix scalarisation crash in widenPHIInstruction for scalable vectors (details)
  123. [llvm-symbolizer] Place Mach-O options into the Mach-O option group. (details)
  124. [llvm-readelf] Unhide short options to match the command guide (details)
  125. [X86][AVX] canonicalizeShuffleMaskWithHorizOp - improve support for 256/512-bit vectors (details)
  126. [libcxx] NFC. Correct wordings of _LIBCPP_ASSERT debug messages (details)
  127. [mlir][linalg] Remove IndexedGenericOp support from LinalgToStandard... (details)
  128. [clang-tidy] Enable the use of IgnoreArray flag in pro-type-member-init rule (details)
  129. Revert "[scudo] Enable arm32 arch" (details)
  130. [mlir][linalg] Remove IndexedGenericOp support from LinalgBufferize... (details)
  131. [clang-tidy][NFC] Simplify a lot of bugprone-sizeof-expression matchers (details)
  132. [x86] add test for pcmpeq with 0; NFC (details)
  133. [x86] try harder to lower to PCMPGT instead of not-of-PCMPEQ (details)
  134. [AMDGPU] Remove assert (details)
  135. [mlir][linalg] Remove IndexedGenericOp support from LinalgInterchangePattern... (details)
  136. [TargetRegisterInfo] Speed up getAllocatableSet. NFCI. (details)
  137. [InstCombine] ~(C + X) --> ~C - X (PR50308) (details)
  138. [AMDGPU] Improve Codegen for build_vector (details)
  139. [llvm-objdump] Exclude __mh_*_header symbols during MachO disassembly (details)
  140. [Passes] Reenable the relative lookup table converter pass for ELF and COFF on aarch64 (details)
  141. [NFC] Use variable GEP index in vec_demanded_elts tests (details)
  142. [clang][AVR] Redefine some types to be compatible with avr-gcc (details)
  143. [CodeGen][AArch64][SVE] Fold [rdffr, ptest] => rdffrs; bugfix for optimizePTestInstr (details)
  144. [DAGCombiner] Add test exposing bug in DAG combine. (details)
  145. [DAGCombiner] Fix DAG combine store elimination, different address space. (details)
  146. Revert "[SelectionDAG][Mips][PowerPC][RISCV][WebAssembly] Teach computeKnownBits/ComputeNumSignBits about atomics" (details)
  147. [ValueTypes] Rename MVT::getVectorNumElements() to MVT::getVectorMinNumElements(). Fix some misuses of getVectorNumElements() (details)
  148. [CUDA][HIP] Fix device template variables (details)
  149. [llvm-cov][test] Add test coverage for "gcov" implying "llvm-cov gcov" compatibility. (details)
  150. [OpenCL] Remove pragma requirement from Arm dot extension. (details)
  151. [mlir][openacc] Conversion of data operand to LLVM IR dialect (details)
  152. [TargetLowering] Improve legalization of scalable vector types (details)
  153. [X86][AVX] Add v4i64 shift-by-32 tests (details)
  154. [X86][AVX] combineConcatVectorOps - add ConcatSubOperand helper. NFCI. (details)
  155. Fix grammar in README.md (details)
  156. [AMDGPU] Disable the SIFormMemoryClauses pass at -O1 (details)
  157. [PowerPC] Fix definitions of CMPRB8, CMPEQB, CMPRB, SETB in PPCInstr64Bit.td and PPCInstrInfo.td (details)
  158. [MLIR] Factor pass timing out into a dedicated timing manager (details)
  159. [docs] Fix documentation for bugprone-dangling-handle (details)
  160. [SystemZ][z/OS] Fix warning caused by umask returning a signed integer type (details)
  161. [libomptarget][amdgpu][nfc] Expand errorcheck macros (details)
  162. [lld-macho] Implement branch-range-extension thunks (details)
  163. [AArch64][GlobalISel] Add MMOs to constant pool loads to allow LICM hoisting. (details)
  164. [mlir][sparse] keep runtime support library signature consistent (details)
  165. [X86][AVX] Fold concat(ps*lq(x,32),ps*lq(y,32)) -> shuffle(concat(x,y),zero) (PR46621) (details)
  166. Update static bound checker for Linalg to cover decreasing cases (details)
  167. [CMake][ELF] Add -fno-semantic-interposition and -Bsymbolic-functions (details)
  168. [X86] Fix -Wunused-lambda-capture (details)
  169. [NFCI][clang][Codegen] CodeGenVTables::addVTableComponent(): use getGlobalDecl (details)
  170. [NFC][clang][Codegen] Split ThunkInfo into it's own header (details)
  171. [mlir][openacc] Add OpenACC translation to LLVM IR (enter_data op create/copyin) (details)
  172. Remove AST inclusion from Basic include (details)
  173. [mlir][linalg] Fixed issue generating reassociation map with Rank-0 types (details)
  174. [cmake] Add support for multiple distributions (details)
  175. [LoopFlatten] Simplify loops so that the pass can operate on unsimplified loops. (details)
  176. [SCEV] Add loop-guard pessimizing test with step = 2. (details)
  177. [PhaseOrdering] Add test for missing vectorization with NewPM. (details)
  178. [clang-tidy] Allow opt-in or out of some commonly occuring patterns in NarrowingConversionsCheck. (details)
  179. Revert "Produce warning for performing pointer arithmetic on a null pointer." (details)
  180. Add type information to integral template argument if required. (details)
  181. [InstCombine] Support one-hot merge for logical and/or (details)
  182. [libc++][nfc] remove duplicated __to_unsigned. (details)
  183. [cmake] Fix typo in function name (details)
  184. [libcxx] [test] Fix fs.op.last_write_time for Windows (details)
  185. [LLD] [COFF] Fix including the personality function for DWARF EH when linking with --gc-sections (details)
  186. [ELF][AVR] Add explicit relocation types to getRelExpr (details)
  187. [mlir][tosa] Remove tosa.identityn operator (details)
  188. Suppress Deferred Diagnostics in discarded statements. (details)
  189. [flang] Fix standalone builds (details)
  190. [mlir-lsp-server] Add support for sending diagnostics to the client (details)
  191. [mlir-lsp-server][NFC] Add newline between Protocol JSON serialization methods and class definitions. (details)
  192. Fix bad mangling of <data-member-prefix> for a closure in the initializer of a variable at global namespace scope. (details)
  193. [RISCV] Remove RISCVII:VSEW enum. Make encodeVYPE operate directly on SEW. (details)
  194. [WebAssembly] Allow Wasm EH with Emscripten SjLj (details)
  195. [WebAssembly] Add TLS data segment flag: WASM_SEG_FLAG_TLS (details)
  196. [lld][WebAssembly] Allow data symbols to extend past end of segment (details)
  197. [mlir] Fix ssa values naming bug (details)
  198. Optimize GSymCreator::finalize. (details)
  199. Change the context instruction for computeKnownBits in LoadStoreVectorizer pass (details)
  200. [mlir][Linalg] Add interface methods to get lhs and rhs of contraction (details)
  201. [AMDGPU] Refactor shouldExpandAtomicRMWInIR(). NFC. (details)
  202. [mlir][sparse][capi][python] add sparse tensor passes (details)
  203. [libcxx] modifies `_CmpUnspecifiedParam` ignore types outside its domain (details)
  204. scudo: Require fault address to be in bounds for UAF. (details)
  205. [AMDGPU][OpenMP] Emit textual IR for -emit-llvm -S (details)
  206. Add test for substitutability of variable templates in closure type (details)
  207. Clean up handling of constrained parameters in lambdas. (details)
  208. PR50306: When instantiating a generic lambda with a constrained 'auto', (details)
  209. Handle unexpanded packs appearing in type-constraints. (details)
  210. Rename human-readable name for DW_LANG_Mips_Assembler (details)
  211. [clang] Minor fix for MarkVarDeclODRUsed (details)
  212. [mlir] Fix masked vector transfer ops with broadcasts (details)
  213. Revert "[mlir] Fix masked vector transfer ops with broadcasts" (details)
  214. [Debug-Info] add -gstrict-dwarf support in backend (details)
  215. [mlir] Fix masked vector transfer ops with broadcasts (details)
  216. [mlir] Allow empty position in vector.insert and vector.extract (details)
  217. [mlir] Unrolled progressive-vector-to-scf. (details)
  218. [mlir] Support memref layout maps in vector transfer ops (details)
  219. [clang-repl] Land initial infrastructure for incremental parsing (details)
  220. [SLP][Test] Fix and precommit tests for D98714 (details)
  221. [SLP][Test] Fix and precommit tests for D98714 (details)
  222. [SLP] Add insertelement instructions to vectorizable tree (details)
  223. [Coroutines] Enable printing coroutine frame when dbg info is available (details)
  224. Revert "[clang-repl] Land initial infrastructure for incremental parsing" (details)
  225. [mlir][tosa] Fix tosa.cast semantics to perform rounding/clipping (details)
  226. [Coroutines] Salvege Debug.values (details)
  227. Add some warnings when debugserver is running in translation (details)
  228. [JITLink] Add a transferDefinedSymbol operation. (details)
  229. [JITLink] Expose x86-64 pointer jump stub block construction. (details)
  230. [GC][NFC] Move GCStrategy from CodeGen to IR (details)
  231. [gn build] Port d8b37de8a478 (details)
  232. [mlir] Support masks in TransferOpReduceRank and TransferReadPermutationLowering (details)
  233. [clang-repl] Recommit "Land initial infrastructure for incremental parsing" (details)
  234. [clang-repl] Add exhaustive list of libInterpreter dependencies. (details)
  235. Use an allow list on reserved macro identifiers (details)
  236. [FPEnv][X86] Implement lowering of llvm.set.rounding (details)
  237. Revert "[SimpleLoopUnswitch] Port partially invariant unswitch from LoopUnswitch to SimpleLoopUnswitch" (details)
  238. [NFC] Add GetInferiorAddrSize method, unify code to compute (details)
  239. [libcxx] NFC. Fix misprint unodered -> unordered (details)
  240. [clang-repl] Add final set of missing library dependencies. (details)
  241. [TSAN] Honor failure memory orders in AtomicCAS (details)
  242. [SCEV] Apply guards to max with non-unitary steps. (details)
  243. [PowerPC] Provide doubleword vector predicate form comparisons on Power7 (details)
  244. [Utils] Use whoami to get username for arcanist warning message (details)
  245. [clang-repl] Fix ClangReplInterpreterTests unittest dependency. (details)
  246. [Passes] Use MemorySSA for LICM during LTO. (details)
  247. [RISCV][NFC] Simplify test run lines (details)
  248. [Passes] Run GlobalsAA before LICM during LTO in new PM. (details)
  249. [Passes] Use regex to match GlobalsAA line in test. (details)
  250. [X86] VZeroUpperInserter::insertVZeroUpper - avoid DebugLoc creation by embedding in the BuildMI calls. NFCI. (details)
  251. [X86] X86InstrInfo.cpp - try to pass DebugLoc by const-ref to avoid costly TrackingMDNodeRef copies. NFCI. (details)
  252. [X86] X86ExpandPseudo.cpp - try to pass DebugLoc by const-ref to avoid costly TrackingMDNodeRef copies. NFCI. (details)
  253. [VPlan] Adjust assert in splitBlock to allow splitting at end. (details)
  254. [PowerPC] Handle inline assembly clobber of link regsiter (details)
  255. [clang-tidy] Fix test that requires Windows platofrm (details)
  256. [gn build] (manually) port 92f9852fc99b, clang-repl (details)
  257. [mlir] Do not use pass labels in unrolled ProgressiveVectorToSCF (details)
  258. [AIX] XFAIL CodeGen/Generic/externally_available.ll (details)
  259. Add entry about Hexagon V68 support to the release notes (details)
  260. Revert "[CMake][ELF] Add -fno-semantic-interposition and -Bsymbolic-functions" (details)
  261. Fix section title underlining in the release notes (details)
  262. [mlir] Migrate vector-to-loops.mlir to ProgressiveVectorToSCF (details)
  263. Reapply [ConstantFold] Fold more operations to poison (details)
  264. [TableGen] Make the NUL character invalid in .td files (details)
  265. [mlir][linalg] Remove IndexedGenericOp support from DropUnitDims... (details)
  266. [mlir] Replace vector-to-scf with progressive-vector-to-scf (details)
  267. [mlir][linalg] Remove IndexedGenericOp support from FusionOnTensors... (details)
  268. [AArch64][SVE] Fix missed immediate selection due to mishandling of signedness (details)
  269. Parse vector bool when stdbool.h and altivec.h are included (details)
  270. [HIP] Add __builtin_amdgcn_groupstaticsize (details)
  271. [AMDGPU] Only allow global fp atomics with unsafe option (details)
  272. [OpenMP] Test unified shared memory tests only on systems that support it. (details)
  273. [InstSimplify] Remove redundant {insert,extract}_vector intrinsic chains (details)
  274. [mlir] Add python test for shape dialect (details)
  275. [libomptarget][amdgpu] Convert an assert to print and offload_fail (details)
  276. [libomptarget][amdgpu] Fix truncation error for partial wavefront (details)
  277. [PowerPC] Add clang option -m[no-]prefixed (details)
  278. [libcxx][ranges] Fix `ranges::empty` when begin, end, and empty members are provided. (details)
  279. Modules: Remove ModuleLoader::OtherUncachedFailure, NFC (details)
  280. [pstl] Use logical operator for loop condition in tests (details)
  281. [analyzer][solver] Prevent use of a null state (details)
  282. [mlir][spirv] Define spv.ImageQuerySize operation (details)
  283. Modules: Rename ModuleBuildFailed => DisableGeneratingGlobalModuleIndex, NFC (details)
  284. [lldb] Fixup more code addresses (details)
  285. [lldb] Fixup indirect symbols as they are signed. (details)
  286. [ARM] Constrain CMPZ shift combine to a single use (details)
  287. [NFC][Clang][Codegen] Add tests with wrong attributes on this/return of thunks (details)
  288. [Clang][Codegen] Do not annotate thunk's this/return types with align/deref/nonnull attrs (details)
  289. Return "[CGCall] Annotate `this` argument with alignment" (details)
  290. Modules: Simplify how DisableGeneratingGlobalModuleIndex is set, likely NFC (details)
  291. [flang] Implement DOT_PRODUCT in the runtime (details)
  292. [PowerPC] Add ROP Protection to prologue and epilogue (details)
  293. [NFC] Try to fix CodeGenCXX/thunk-wrong-this.cpp test (details)
  294. Support unwinding from inline assembly (details)
  295. [NFC] Try to fix CodeGenCXX/thunk-wrong-return-type.cpp test (details)
  296. [flang] (NFC) Expose internal idiom as utility API (details)
  297. [NFC] Delete two newly-added test cases (details)
  298. [ASTMatchers] NFC: Fix formatting around forFunction(). (details)
  299. [ASTMatchers] Add forCallable(), a generalization of forFunction(). (details)
  300. [clang-tidy] bugprone-infinite-loop: forFunction() -> forCallable(). (details)
  301. [clang-tidy] bugprone-infinite-loop: React to ObjC ivars and messages. (details)
  302. [AMDGPU] Add gfx1034 target (details)
  303. [libcxx][docs] Update the One Ranges PRoposal Status with open revisions. (details)
  304. [libcxx][docs] Add two locks: transform_view and take_view. (details)
  305. [flang] Support legacy extension OPEN(ACCESS='APPEND') (details)
  306. [HIP] Clean up llvm intrinsics using __asm (details)
  307. [flang][OpenMP] Add semantic check for close nesting of `master` regions (details)
  308. [libc] Add x86_64 implementations of double precision cos, sin and tan. (details)
  309. [libc][NFC] Instead of erroring, skip math targets with missing implementations. (details)
  310. [llvm-nm] Support the -V option, print that the tool is compatible with GNU nm (details)
  311. [mlir][NFC] Add helper for common pattern of replaceAllUsesExcept (details)
  312. [mlir][tosa] Add tosa.div integer lowering to linalg.generic. (details)
  313. [OpenMP] Prevent Attributor from deleting functions in OpenMPOptCGSCC pass (details)
  314. [CMake][ELF] Link libLLVM.so and libclang-cpp.so with -Bsymbolic-functions (details)
  315. [libc] Enable fmaf and fma on x86_64. (details)
  316. [mlir][tosa] Add lowering to tosa.abs for integer cases (details)
  317. [NFC][X86][MCA] AMD Zen 3: add same-reg SSE XMM XORPS test (details)
  318. [X86] AMD Zen 3: same-reg SSE XMM XORPS is a 1-cycle(!) dep-breaking one-idiom (details)
  319. Revert "[X86] X86TTIImpl::getInterleavedMemoryOpCostAVX2(): use getMemoryOpCost()" (details)
  320. Revert "[X86][CostModel] X86TTIImpl::getMemoryOpCost(): rewrite vector handling again" (details)
  321. [AA] Use isIdentifiedFunctionLocal() (NFC) (details)
  322. [CaptureTracking] Use isIdentifiedFunctionLocal() (NFC) (details)
  323. [clang-repl] Temporarily disable the execute.cpp test on ppc64. (details)
  324. [docs] Add page on opaque pointer types (details)
  325. Don't run MachineVerifier on sjlj-unwind-inline-asm test because of known issue (PR39439) (details)
  326. [Clang][OpenMP] Allow unified_shared_memory for Pascal-generation GPUs. (details)
  327. [IR] Introduce the opaque pointer type (details)
  328. Widen `name` stencil to support `TypeLoc` nodes. (details)
  329. [mlir][Linalg] Add ComprehensiveBufferize for functions(step 1/n) (details)
  330. [mlir][Linalg] Add support for vector.transfer ops to comprehensive bufferization (2/n). (details)
  331. AMDGPU/GlobalISel: Implement tail calls (details)
  332. AMDGPU/GlobalISel: Don't hardcode stack alignment in assert message (details)
  333. [gn] Don't pass -fprofile-instr-generate to linker on Windows (details)
  334. [mlir][openacc][NFC] add anonymous namespace around LegalizeDataOpForLLVMTranslation class (details)
  335. [AArch64][GlobalISel] Fix a crash during unsuccessful G_CTPOP <2 x s64> legalization. (details)
  336. [Debug-Info] make DIE attributes generation under strict DWARF control (details)
  337. [sanitizer] Use size_t on g_tls_size to fix build on x32 (details)
  338. [test] Fix new-pm-lto-defaults.ll to work on all platforms (details)
  339. scudo: Check for UAF in ring buffer before OOB in more distant blocks. (details)
  340. scudo: Fix MTE error reporting for zero-sized allocations. (details)
  341. [Debug-Info] change Tag type to dwarf::Tag for createAndAddDIE; NFC (details)
  342. [mlir] VectorToSCF target rank is a pass option (details)
  343. [ORC] Remove some stale unit test utils. (details)
  344. [ORC] Remove unused RTDyldObjectLinkingLayerExecutionTest class from unit test. (details)
  345. [ORC] Remove the OrcExecutionTest class. It is no longer used. (details)
  346. [MLIR] Fix build failures due to unused variables in non-debug builds. (details)
  347. [mlir] VectorToSCF cleanup (details)
  348. [COFF] Remove a truncation assertion from setRVA (details)
  349. Use enum comparison instead of generated switch/case, NFC (details)
  350. [AMDGPU] Do not clause NSA instructions (details)
  351. [sanitizer] Simplify __sanitizer::BufferedStackTrace::UnwindImpl implementations (details)
  352. [JITLink] Fix missing 'static' keyword in unit test. (details)
  353. [ORC] Add support for adding LinkGraphs directly to ObjectLinkingLayer. (details)
  354. [gn build] Port 0fda4c4745b8 (details)
  355. [ORC] Add JITLink dependence for ObjectLinkingLayerTest. (details)
  356. [DSE] Move isOverwrite into DSEState. NFC (details)
  357. [GVN] Clobber partially aliased loads. (details)
  358. New tag for ittapi - fix an error related to cross-compiling ITTAPI in LLVM with mingw (details)
  359. [llvm][AsmPrinter] Restore source location to register clobber warning (details)
  360. [AMDGPU][AsmParser/Disassembler] Correct A16 and G16 handling (details)
  361. [AMDGPU] Fix codegen of image intrinsics for g16 and a16 (details)
  362. [docs] Added llvm/cmake section (details)
  363. [NFC][X86][MCA] AMD Zen 3: add same-reg AVX XMM VXORPS tests (details)
  364. [X86] AMD Zen 3: same-reg AVX XMM VXORPS is a zero-cycle(!) dep-breaking zero-idiom (details)
  365. [NFC][X86][MCA] AMD Zen 3: add same-reg AVX YMM VXORPS tests (details)
  366. [X86] AMD Zen 3: same-reg AVX YMM VXORPS is a zero-cycle(!) dep-breaking zero-idiom (details)
  367. [NFC][X86][MCA] AMD Zen 3: add same-reg SSE XMM XORPD tests (details)
  368. [NFC][X86][MCA] AMD Zen 3: add same-reg AVX XMM VXORPD tests (details)
  369. [NFC][X86][MCA] AMD Zen 3: add same-reg AVX YMM VXORPD tests (details)
  370. [X86] AMD Zen 3: same-reg SSE XMM XORPD is a 1-cycle(!) dep-breaking zero-idiom (details)
  371. [X86] AMD Zen 3: same-reg AVX XMM VXORPD is a zero-cycle(!) dep-breaking zero-idiom (details)
  372. [X86] AMD Zen 3: same-reg AVX YMM VXORPD is a zero-cycle(!) dep-breaking zero-idiom (details)
  373. [libcxx] [test] Change the generic_string_alloc test to test conversions to all char types (details)
  374. [llvm-mc][AArch64] HINT instruction disassembled as BTI (details)
  375. [AMDGPU] getMemOperandsWithOffset: add vaddr operand for stack access BUF instructions (details)
  376. NFCI: Remove VF argument from isScalarWithPredication (details)
  377. AArch64: support i128 cmpxchg in GlobalISel. (details)
  378. [Test] Add test on missing opportunity in Loop Deletion (details)
  379. [X86] Try to pass DebugLoc by const-ref to avoid costly TrackingMDNodeRef copies. NFCI. (details)
  380. [SLP] Fix spill cost computation for insertelement tree node (details)
  381. [VectorCombine] Add tests with assumes involvind variable index. (details)
  382. [Local] collectBitParts - reduce maximum recursion depth. (details)
  383. [Local] collectBitParts - for bswap-only matches, limit shift amounts to whole bytes to reduce compile time. (details)
  384. IR+AArch64: add a "swiftasync" argument attribute. (details)
  385. [WebAssembly] Support Emscripten EH/SjLj in Wasm64 (details)
  386. [WebAssembly] Omit DBG_VALUE after terminator (details)
  387. [LoopVectorizationLegality] NFC: Mark some interfaces as 'const' (details)
  388. [NFC][X86][MCA] AMD Zen 3: add same-reg SSE XMM ANDNPS tests (details)
  389. [NFC][X86][MCA] AMD Zen 3: add same-reg AVX XMM VANDNPS tests (details)
  390. [NFC][X86][MCA] AMD Zen 3: add same-reg AVX YMM VANDNPS tests (details)
  391. [X86] AMD Zen 3: same-reg SSE XMM ANDNPS is a 1-cycle(!) dep-breaking zero-idiom (details)
  392. [X86] AMD Zen 3: same-reg AVX XMM VANDNPS is a zero-cycle(!) dep-breaking zero-idiom (details)
  393. [X86] AMD Zen 3: same-reg AVX YMM VANDNPS is a zero-cycle(!) dep-breaking zero-idiom (details)
  394. [NFC][X86][MCA] AMD Zen 3: add same-reg SSE XMM ANDNPD tests (details)
  395. [NFC][X86][MCA] AMD Zen 3: add same-reg AVX XMM VANDNPD tests (details)
  396. [NFC][X86][MCA] AMD Zen 3: add same-reg AVX YMM VANDNPD tests (details)
  397. [X86] AMD Zen 3: same-reg SSE XMM ANDNPD is a 1-cycle(!) dep-breaking zero-idiom (details)
  398. [X86] AMD Zen 3: same-reg AVX XMM VANDNPD is a zero-cycle(!) dep-breaking zero-idiom (details)
  399. [X86] AMD Zen 3: same-reg AVX YMM VANDNPD is a zero-cycle(!) dep-breaking zero-idiom (details)
  400. [TableGen] Remove unneeded forward defs. NFC. (details)
  401. [Transforms][Debugify] Fix "Missing line" false alarm on PHI nodes (details)
  402. [clang][NFC] remove unused return value (details)
  403. [SDAG] reduce code duplication for extend_vec_inreg combines; NFC (details)
  404. [PowerPC] Add vec_vupkhpx and vec_vupklpx for XL compatibility (details)
  405. [AMDGPU][MC][NFC][DOC] Updated AMD GPU assembler syntax description. (details)
  406. [ARM][AArch64] Correct __ARM_FEATURE_CRYPTO macro and crypto feature (details)
  407. [RISCV] Add the DebugLoc parameter to getVLENFactoredAmount(). (details)
  408. [ARM] Define CPSR on MEMCPY pseudos (details)
  409. [ARM] Expand predecessor search to multiple blocks when reverting WhileLoopStarts (details)
  410. [utils] Don't print username in arcanist clang format message (details)
  411. [clangd] Always default to raw pch format (details)
  412. [rs4gc] Strip memory related attributes consistently (details)
  413. [AArch64][SVE] Add unpredicated vector BIC ISD node (details)
  414. Bump googletest to 1.8.1 (details)
  415. [libc++] Improve make_string test support. (details)
  416. [X86][SSE] Pull out combineToHorizontalAddSub helper from inside (F)ADD/SUB combines. NFCI. (details)
  417. Fix some typos. (details)
  418. [AArch64][SVE] Combine cntp intrinsics with add/sub to produce incp/decp (details)
  419. [LV] Add a few more complex first-order recurrence tests. (details)
  420. Autogen a test for ease of update (details)
  421. [ELF][test] Improve -Bsymbolic & -Bsymbolic-functions test (details)
  422. [ELF] Add -Bno-symbolic (details)
  423. [OpenCL] Simplify use of C11 atomic types. (details)
  424. [HWASan] Add aliasing flag and enable HWASan to use it. (details)
  425. Do actual DCE in LoopUnroll (details)
  426. Revert "Do actual DCE in LoopUnroll" (details)
  427. Bump googletest to 1.10.0 (details)
  428. [NFC][X86][MCA] AMD Zen 3: add same-reg SSE XMM PXOR tests (details)
  429. [NFC][X86][MCA] AMD Zen 3: add same-reg AVX XMM VPXOR tests (details)
  430. [NFC][X86][MCA] AMD Zen 3: add same-reg AVX YMM VPXOR tests (details)
  431. [X86] AMD Zen 3: same-reg SSE XMM PXOR is a 1-cycle(!) dep-breaking zero-idiom (details)
  432. [X86] AMD Zen 3: same-reg AVX XMM VPXOR is a zero-cycle(!) dep-breaking zero-idiom (details)
  433. [X86] AMD Zen 3: same-reg AVX YMM VPXOR is a zero-cycle(!) dep-breaking zero-idiom (details)
  434. [NFC][X86][MCA] AMD Zen 3: add same-reg SSE XMM PANDN tests (details)
  435. [NFC][X86][MCA] AMD Zen 3: add same-reg AVX XMM VPANDN tests (details)
  436. [NFC][X86][MCA] AMD Zen 3: add same-reg AVX YMM VPANDN tests (details)
  437. [X86] AMD Zen 3: same-reg SSE XMM PANDN is a 1-cycle(!) dep-breaking zero-idiom (details)
  438. [X86] AMD Zen 3: same-reg AVX XMM VPANDN is a zero-cycle(!) dep-breaking zero-idiom (details)
  439. [X86] AMD Zen 3: same-reg AVX YMM VPANDN is a zero-cycle(!) dep-breaking zero-idiom (details)
  440. [NFC][X86][MCA] AMD Zen 3: add same-reg SSE XMM PSUB{B,W,D,Q} tests (details)
  441. [NFC][X86][MCA] AMD Zen 3: add same-reg AVX XMM VPSUB{B,W,D,Q} tests (details)
  442. [NFC][X86][MCA] AMD Zen 3: add same-reg AVX YMM VPSUB{B,W,D,Q} tests (details)
  443. [X86] AMD Zen 3: same-reg SSE XMM PSUB{B,W,D,Q} is a 1-cycle(!) dep-breaking zero-idiom (details)
  444. [X86] AMD Zen 3: same-reg AVX XMM VPSUB{B,W,D,Q} is a zero-cycle(!) dep-breaking zero-idiom (details)
  445. [X86] AMD Zen 3: same-reg AVX YMM VPSUB{B,W,D,Q} is a zero-cycle(!) dep-breaking zero-idiom (details)
  446. [NFC][X86][MCA] AMD Zen 3: add same-reg SSE XMM PSUBS{B,W} tests (details)
  447. [NFC][X86][MCA] AMD Zen 3: add same-reg AVX XMM VPSUBS{B,W} tests (details)
  448. [NFC][X86][MCA] AMD Zen 3: add same-reg AVX YMM VPSUBS{B,W} tests (details)
  449. [X86] AMD Zen 3: same-reg SSE XMM PSUBS{B,W} is a 1-cycle(!) dep-breaking zero-idiom (details)
  450. [X86] AMD Zen 3: same-reg AVX XMM VPSUBS{B,W} is a 1-cycle(!) dep-breaking zero-idiom (details)
  451. [X86] AMD Zen 3: same-reg AVX YMM VPSUBS{B,W} is a 1-cycle(!) dep-breaking zero-idiom (details)
  452. [NFC][X86][MCA] AMD Zen 3: add same-reg SSE XMM PSUBUS{B,W} tests (details)
  453. [NFC][X86][MCA] AMD Zen 3: add same-reg AVX XMM VPSUBUS{B,W} tests (details)
  454. [NFC][X86][MCA] AMD Zen 3: add same-reg AVX YMM VPSUBUS{B,W} tests (details)
  455. [X86] AMD Zen 3: same-reg SSE XMM PSUBUS{B,W} is a 1-cycle(!) dep-breaking zero-idiom (details)
  456. [X86] AMD Zen 3: same-reg AVX XMM VPSUBUS{B,W} is a 1-cycle(!) dep-breaking zero-idiom (details)
  457. [X86] AMD Zen 3: same-reg AVX YMM VPSUBUS{B,W} is a 1-cycle(!) dep-breaking zero-idiom (details)
  458. [NFC][X86][MCA] AMD Zen 3: add same-reg SSE XMM PCMPGT{B,W,D,Q} tests (details)
  459. [NFC][X86][MCA] AMD Zen 3: add same-reg AVX XMM VPCMPGT{B,W,D,Q} tests (details)
  460. [NFC][X86][MCA] AMD Zen 3: add same-reg AVX YMM VPCMPGT{B,W,D,Q} tests (details)
  461. [X86] AMD Zen 3: same-reg SSE XMM PCMPGT{B,W,D,Q} is a 1-cycle(!) dep-breaking zero-idiom (details)
  462. [X86] AMD Zen 3: same-reg AVX XMM VPCMPGT{B,W,D,Q} is a zero-cycle(!) dep-breaking zero-idiom (details)
  463. [X86] AMD Zen 3: same-reg AVX YMM VPCMPGT{B,W,D,Q} is a zero-cycle(!) dep-breaking zero-idiom (details)
  464. [NFC][X86][MCA] Add sudo-zero-idiom vperm2f128/vperm2i128 tests - don't break deps (details)
  465. AMDGPU: Fix assert when rewriting saddr d16 loads (details)
  466. Document updated googletest + modifications (details)
  467. [mlir][NFC] Move passes in test/lib/Transforms/ to a directory that mirrors what they test (details)
  468. [clangd] Make unit test compatible with gtest 1.10.0 (details)
  469. [test] Improve x86-64-plt.s (details)
  470. Allow same memory space for SRC and DST of dma_start operations (details)
  471. [GWP-ASan] Migrate lit tests from old Scudo -> Standalone. (details)
  472. Do actual DCE in LoopUnroll (try 2) (details)
  473. [Demangle][Rust] Parse integer constants (details)
  474. [gn build] (manually) merge b7d1ab75cf47 (details)
  475. [AMDGPU] Add support for architected flat scratch (details)
  476. [InstCombine] add test for shl demanded bits miscompile; NFC (details)
  477. [InstCombine] drop poison flags when simplifying 'shl' based on demanded bits (details)
  478. [Polly] Add support for -polly-position=early with the NPM. (details)
  479. [mlir] Add missing dependence to TestDialect from TestTransforms (details)
  480. Discount invariant instructions in full unrolling (details)
  481. SwiftAsync: remove duplicate instance in array. NFC. (details)
  482. Add another -Wdeprecated-copy hack for gtest (details)
  483. [flang] s/TYPED_TEST_CASE/TYPED_TEST_SUITE/ as the former is deprecated (details)
  484. Remove (unneeded) '-asan-use-after-return' from hoist-argument-init-insts.ll. (details)
  485. [ProfData] Address a unit test FIXME (details)
  486. GTEST_HAS_TR1_TUPLE is gone, stop defining it. (details)
  487. [sanitizer] Fall back to fast unwinder (details)
  488. [sanitizer] Commit a missing change in BufferedStackTrace::Unwind (details)
  489. [SLP][NFC]Add a test for non-consecutive inserts, NFC. (details)
  490. [AA] Support callCapturesBefore() on BatchAA (NFCI) (details)
  491. [Clang,Driver] Add -fveclib=Darwin_libsystem_m support. (details)
  492. [LV] Add another more complex first-order recurrence sinking test. (details)
  493. [Scudo] Delete unused flag 'rss_limit_mb'. (details)
  494. [MinGW] Always enable -mbig-obj for LLVM build unless using Clang (details)
  495. [LLD][MinGW] Ignore --no-undefined flag (details)
  496. [SystemZ] [z/OS] Add SystemZCallingConventionRegisters class (details)
  497. [MemDep] Use BatchAA in more places (NFCI) (details)
  498. [CSSPGO] Fix return value of getProbeWeight (details)
  499. [Polly] Run polly-update-format. NFC. (details)
  500. [NFC] Directly get GV type (details)
  501. Revert "[X86] Try to pass DebugLoc by const-ref to avoid costly TrackingMDNodeRef copies. NFCI." (details)
  502. [mlir][Linalg] Add support for subtensor_insert comprehensive bufferization (3/n) (details)
  503. [msan] [NFC] Add newline to EOF in test. (details)
  504. [AMDGPU] Update SCC defs to VCC when uses are changed to VCC (details)
  505. [mlir][Linalg] NFC - More gracefully degrade lookup into failure during comprehensive bufferization (4/n) (details)
  506. [compiler-rt] Fix deprection warnings on INSTANTIATE_TEST_CASE_P (details)
  507. [libcxx][ranges] Add `contiguous_iterator`. (details)
  508. [LowerConstantIntrinsics] reuse isManifestLogic from ConstantFolding (details)
  509. Reinstate gtest fix from 4f0b0bf5c6731e3d370558be08c9261801263b09 (details)
  510. [lld][WebAssembly] Remove unused method declaration. NFC (details)
  511. [GlobalISel][CallLowering] Fix crash when handling a v3s32 type that's being passed as v2s64. (details)
  512. [Compiler-rt] Distinguish between testing just built runtime libraries and the libraries shipped with the compiler. (details)
  513. [MC] Add the ability to pass MCRegisterInfo to dump_pretty. (details)
  514. Extract a helper routine to simplify D91481 [NFC] (details)
  515. [mlir][sparse] prepare runtime support lib for multiple dim level types (details)
  516. [gn build] (manually) port ad7e12226f6b (details)
  517. [mlir][sparse] remove accidental debug code (details)
  518. [llvm-jitlink] Link libnetwork on Haiku in llvm-jitlink (details)
  519. Fix "is not used" warning (details)
  520. [sanitizer] Disable test on Android (details)
  521. Revert "[Clang,Driver] Add -fveclib=Darwin_libsystem_m support." (details)
  522. Verifier: second attempt to fix what I broke with swiftasync. (details)
  523. [Demangle][Rust] Parse bool constants (details)
Commit 13ea238b1e1db96ef5fd409e869d9a8ebeef1332 by anastasia.stulova
[OpenCL] Allow use of double type without extension pragma.

Simply use of extensions by allowing the use of supported
double types without the pragma. Since earlier standards
instructed that the pragma is used explicitly a new warning
is introduced in pedantic mode to indicate that use of
type without extension pragma enable can be non-portable.

This patch does not break backward compatibility since the
extension pragma is still supported and it makes the behavior
of the compiler less strict by accepting code without extra
pragma statements.

Differential Revision: https://reviews.llvm.org/D100980
The file was modifiedclang/lib/Sema/Sema.cpp
The file was modifiedclang/include/clang/Basic/DiagnosticSemaKinds.td
The file was modifiedclang/test/Misc/warning-flags.c
The file was modifiedclang/test/SemaOpenCL/extensions.cl
The file was modifiedclang/lib/Sema/SemaType.cpp
Commit 09fe84abb4ee71f707c3ec8e960a42d8292f6211 by Piotr Sobczak
[AMDGPU] Move code sinking before structurizer

Moving code sinking pass before structurizer creates more sinking
opportunities.

The extra flow edges introduced by the structurizer can have adverse
effects on sinking, because the sinking pass prefers moving instructions
to blocks with unique predecessors and the structurizer destroys that
property in some cases.

A notable example is moving high-latency image instructions across kills.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D101115
The file was modifiedllvm/test/CodeGen/AMDGPU/loop_exit_with_xor.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/llc-pipeline.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/multilevel-break.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
The file was addedllvm/test/CodeGen/AMDGPU/sink-image-sample.ll
Commit 49950cb1f6f699cbb9d8f141c0c043d4795c3417 by spatel
[SLP] restrict matching of load combine candidates

The test example from https://llvm.org/PR50256 (and reduced here)
shows that we can match a load combine candidate even when there
are no "or" instructions. We can avoid that by confirming that we
do see an "or". This doesn't apply when matching an or-reduction
because that match begins from the operands of the reduction.

Differential Revision: https://reviews.llvm.org/D102074
The file was modifiedllvm/test/Transforms/SLPVectorizer/AArch64/widen.ll
The file was modifiedllvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Commit c02476f3158f2908ef0a6f628210b5380bd33695 by lebedev.ri
[X86][CostModel] X86TTIImpl::getMemoryOpCost(): rewrite vector handling again

Instead of handling power-of-two sized vector chunks,
try handling the large vector in a stream mode,
decreasing the operational vector size
once it no longer works for the elements left to process.

Notably, this improves costs for overaligned loads - loading padding is fine.
This more directly tracks when we need to insert/extract the YMM/XMM subvector,
some costs fluctuate because of that.

Reviewed By: RKSimon, ABataev

Differential Revision: https://reviews.llvm.org/D100684
The file was modifiedllvm/test/Analysis/CostModel/X86/interleaved-store-i16-stride-3.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-3.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/load_store.ll
The file was modifiedllvm/lib/Target/X86/X86TargetTransformInfo.cpp
Commit bce3cca4889a9e4ab7b9652b0c44bb49ca8f3bad by Matthew.Arsenault
CodeGen: Fix null dereference before null check
The file was modifiedllvm/lib/CodeGen/MachineBlockFrequencyInfo.cpp
Commit 9acc03ad92c66b856f67bf11ff4460c7da45f413 by llvm-dev
[X86][SSE] Replace foldShuffleOfHorizOp with generalized version in canonicalizeShuffleMaskWithHorizOp

foldShuffleOfHorizOp only handled basic shufps(hop(x,y),hop(z,w)) folds - by moving this to canonicalizeShuffleMaskWithHorizOp we can work with more general/combined v4x32 shuffles masks, float/integer domains and support shuffle-of-packs as well.

The next step will be to support 256/512-bit vector cases.
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was modifiedllvm/test/CodeGen/X86/horizontal-shuffle.ll
The file was modifiedllvm/test/CodeGen/X86/horizontal-sum.ll
Commit 759b97e55a4bd7b0d89493686f4a769718e385ee by llvm-dev
[X86] Replace repeated isa/cast<ConstantSDNode> calls with single single dyn_cast<>. NFCI.

Noticed while looking at D101944
The file was modifiedllvm/lib/Target/X86/X86ISelDAGToDAG.cpp
Commit 6ca2bdb03c0fdb6736ed5c6a30d7bec6b557d1a0 by Paul C. Anagnostopoulos
[TableGen] Make the NUL character invalid in .td files

Differential Revision: https://reviews.llvm.org/D101923
The file was addedllvm/test/TableGen/nul-char.td
The file was modifiedllvm/lib/TableGen/TGLexer.cpp
Commit 69ed93a4355123a45c1d7216aea7cd53d07a361b by lebedev.ri
[X86] X86TTIImpl::getInterleavedMemoryOpCostAVX2(): use getMemoryOpCost()

Now that getMemoryOpCost() correctly handles all the vector variants,
we should no longer hand-roll our own version of it, but use it directly.

The AVX512 variant probably needs a similar change,
but there it is less obvious.
The file was modifiedllvm/test/Analysis/CostModel/X86/interleaved-store-i8.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/interleaved-load-i8.ll
The file was modifiedllvm/lib/Target/X86/X86TargetTransformInfo.cpp
Commit faebc6bf108eccdfd75917636c64137f73a7bda7 by flo
[VPlan] Register recipe for instr if the simplified value is recipe.

If the simplified VPValue is a recipe, we need to register it for Instr,
in case it needs to be recorded. The way this is handled in general may
change soon, following some post-commit comments.

This fixes PR50298.
The file was modifiedllvm/test/Transforms/LoopVectorize/reduction.ll
The file was modifiedllvm/lib/Transforms/Vectorize/LoopVectorize.cpp
Commit c765d140fe45906fb503d843acccf5838e775245 by jonathan.l.peyton
[OpenMP] Fix hidden helper + affinity

When KMP_AFFINITY is set, each worker thread's gtid value is used as an
index into the place list to determine the thread's placement. With hidden
helpers enabled, this gtid value is shifted down leading to unexpected
shifted thread placement. This patch restores the previous behavior by
adjusting the mask index to take the number of hidden helper threads
into account.

Hidden helper threads are given the full initial mask and do not
participate in any of the other affinity mechanisms (place partitioning,
balanced affinity). Their affinity is only printed for debug builds.

Differential Revision: https://reviews.llvm.org/D101882
The file was modifiedopenmp/runtime/src/kmp_runtime.cpp
The file was modifiedopenmp/runtime/src/kmp.h
The file was modifiedopenmp/runtime/src/kmp_affinity.cpp
Commit 46402eb103d06b1e695ecfd6f6c9571615042a9c by Paul C. Anagnostopoulos
Revert "[TableGen] Make the NUL character invalid in .td files"

At least one build uses a 'sed' that does not understand \x00.

This reverts commit cf9647011c4f05e1eb4423c6637d84e2f26b2042.
The file was removedllvm/test/TableGen/nul-char.td
The file was modifiedllvm/lib/TableGen/TGLexer.cpp
Commit c58912eca743c612fd2a22c03b64a1bda3d2180f by aakanksha555
Fix typo "Execpt" in comments

Differential Revision: https://reviews.llvm.org/D101858
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.td
Commit 29342291d25b83da97e74d75004b177ba41114fc by congzhecao
[LoopInterchange] Fix legality for triangular loops

This is a bug fix in legality check.

When we encounter triangular loops such as the following form:
    for (int i = 0; i < m; i++)
      for (int j = 0; j < i; j++), or

    for (int i = 0; i < m; i++)
      for (int j = 0; j*i < n; j++),

we should not perform interchange since the number of executions of the loop body
will be different before and after interchange, resulting in incorrect results.

Reviewed By: bmahjour

Differential Revision: https://reviews.llvm.org/D101305
The file was addedllvm/test/Transforms/LoopInterchange/inner-indvar-depend-on-outer-indvar.ll
The file was modifiedllvm/lib/Transforms/Scalar/LoopInterchange.cpp
Commit eca3d68399246765bc6e8c94ffb4d5927b1add12 by Pushpinder.Singh
Revert "[AMDGPU][OpenMP] Emit textual IR for -emit-llvm -S"

This reverts commit 7f78e409d0280c62209e1a7dc8c6d1409acc9184.
The file was modifiedclang/test/Driver/amdgpu-openmp-toolchain.c
The file was modifiedclang/lib/Driver/ToolChains/Clang.cpp
Commit d6a228cba47ffb33d4f6814af1feaf49b34568d0 by Tony.Tye
[NFC][AMDGPU] Correct product name for gfx908

The product name for gfx908 is "AMD Instinct MI100 Accelerator".

Reviewed By: rampitec

Differential Revision: https://reviews.llvm.org/D102209
The file was modifiedllvm/docs/AMDGPUUsage.rst
Commit 4eff9469475384a59a9da407e78aa00262edcdd0 by Steven Wu
[IR][AutoUpgrade] Drop align attribute from void return types

Since D87304, `align` become an invalid attribute on none pointer types and
verifier will reject bitcode that has invalid `align` attribute.

The problem is before the change, DeadArgumentElimination can easily
turn a pointer return type into a void return type without removing
`align` attribute. Teach Autograde to remove invalid `align` attribute
from return types to maintain bitcode compatibility.

rdar://77022993

Reviewed By: dexonsmith

Differential Revision: https://reviews.llvm.org/D102201
The file was addedllvm/test/Bitcode/upgrade-void-ret-attr-11.0.ll
The file was addedllvm/test/Bitcode/upgrade-void-ret-attr-11.0.ll.bc
The file was modifiedllvm/lib/Bitcode/Reader/BitcodeReader.cpp
The file was modifiedllvm/lib/IR/AutoUpgrade.cpp
Commit dfc1e31d49fe1380c9bab43373995df5fed15e6d by schmeise
Produce warning for performing pointer arithmetic on a null pointer.

Summary:
Test and produce warning for subtracting a pointer from null or subtracting
null from a pointer.  Reuse existing warning that this is undefined
behaviour.  Also add unit test for both warnings.

Reformat to satisfy clang-format.

Respond to review comments:  add additional test.

Respond to review comments:  Do not issue warning for nullptr - nullptr
in C++.

Fix indenting to satisfy clang-format.

Respond to review comments:  Add C++ tests.

Author: Jamie Schmeiser <schmeise@ca.ibm.com>
Reviewed By: efriedma (Eli Friedman), nickdesaulniers (Nick Desaulniers)
Differential Revision: https://reviews.llvm.org/D98798
The file was modifiedclang/test/Sema/pointer-addition.c
The file was modifiedclang/lib/Sema/SemaExpr.cpp
The file was addedclang/test/Sema/pointer-addition.cpp
Commit 2c1f9f390b0a5dd308e2e925fe250d19a29c103f by lebedev.ri
[NFC][X86] Precommit another testcase for D101944
The file was modifiedllvm/test/CodeGen/X86/64-bit-shift-by-32-minus-y.ll
Commit 6400905a615282c83a2fc6e49e57ff716aa8b4de by a-phipps
Fix branch coverage merging in FunctionCoverageSummary::get() for instantiation
groups.

This change corrects the implementation for the branch coverage
summary to do the same thing for branches that is done for lines and regions.
That is, across function instantiations in an instantiation group, the maximum
branch coverage found in any of those instantiations is returned, with the
total number of branches being the same across instantiations.

Differential Revision: https://reviews.llvm.org/D102193
The file was modifiedllvm/tools/llvm-cov/CoverageSummaryInfo.h
The file was modifiedllvm/tools/llvm-cov/CoverageSummaryInfo.cpp
The file was modifiedllvm/test/tools/llvm-cov/branch-templates.cpp
Commit 6c82b8a378a6f59e94a81d91225db4fabf6e2bff by augusto2112
Change Target::ReadMemory to ensure the amount of memory read from the file-cache is the amount requested.

This change ensures that if for whatever reason we read less bytes than expected (for example, when trying to read memory that spans multiple sections), we try reading from the live process as well.

Reviewed By: jasonmolenda

Differential Revision: https://reviews.llvm.org/D101390
The file was modifiedlldb/source/Target/Target.cpp
Commit ec28e43e01540a57f8822b2efb8638996873f945 by augusto2112
Add null-pointer checks when accessing a TypeSystem's SymbolFile

A type system is not guaranteed to have a symbol file. This patch adds null-pointer checks so we don't crash when trying to access a type system's symbol file.

Reviewed By: aprantl, teemperor

Differential Revision: https://reviews.llvm.org/D101539
The file was modifiedlldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp
The file was modifiedlldb/source/Symbol/Type.cpp
The file was modifiedlldb/source/Plugins/SymbolFile/PDB/PDBASTParser.cpp
The file was modifiedlldb/unittests/Symbol/TestTypeSystemClang.cpp
Commit b20e150c9be16f69c73f4cd2986053d13d0f376a by benny.kra
[mlir] Use static shape knowledge when lowering memref.reshape

This is actually necessary for correctness, as memref.reinterpret_cast
doesn't verify if the output shape doesn't match the static sizes.

Differential Revision: https://reviews.llvm.org/D102232
The file was modifiedmlir/test/Dialect/Standard/expand-ops.mlir
The file was modifiedmlir/lib/Dialect/StandardOps/Transforms/ExpandOps.cpp
Commit 72995a4bdf7d95887883ccfa04567b723f2b342a by jonathanchesterfield
[libomptarget][nfc] Add hook to easily disable building amdgcn bclib

[libomptarget][nfc] Add hook to easily disable building amdgcn bclib

This is useful when building LLVM with a toolchain that can't emit code
for amdgcn, e.g. because it overrides the include search path with headers
from another architecture, or the clang compiler is missing builtins.

Reviewed By: tianshilei1992

Differential Revision: https://reviews.llvm.org/D102229
The file was modifiedopenmp/libomptarget/deviceRTLs/amdgcn/CMakeLists.txt
Commit ab3fcc5065a895f88ec8a020bc3c2f7e54cc4561 by arthur.j.odwyer
[libc++] s/_VSTD::declval/declval/g. NFCI.
The file was modifiedlibcxx/include/concepts
The file was modifiedlibcxx/include/__memory/construct_at.h
The file was modifiedlibcxx/include/memory
The file was modifiedlibcxx/include/experimental/propagate_const
The file was modifiedlibcxx/include/__functional_base
The file was modifiedlibcxx/include/variant
The file was modifiedlibcxx/include/ostream
The file was modifiedlibcxx/include/istream
The file was modifiedlibcxx/include/optional
The file was modifiedlibcxx/include/algorithm
The file was modifiedlibcxx/include/scoped_allocator
The file was modifiedlibcxx/include/__memory/shared_ptr.h
The file was modifiedlibcxx/include/type_traits
Commit 0b8da5fa5915f1cea790c7e246195e30afd9e391 by arthur.j.odwyer
[libc++] s/std::size_t/size_t/g. NFCI.
The file was modifiedlibcxx/include/type_traits
The file was modifiedlibcxx/include/experimental/functional
Commit aa5e3beea3d4d4e00cb2b0f2d103b4bd52239384 by arthur.j.odwyer
[libc++] s/_VSTD::chrono/chrono/g. NFCI.
The file was modifiedlibcxx/include/chrono
Commit 866b27950aaf2c38f4ecfc8a0f18945fff3b8542 by arthur.j.odwyer
[libc++] s/_VSTD::is_unsigned/is_unsigned/ in <random>. NFCI.
The file was modifiedlibcxx/test/std/numerics/rand/rand.eng/rand.eng.lcong/params.fail.cpp
The file was modifiedlibcxx/include/random
Commit 6491d99e330c38b33b9cb6acb19afa3a464febeb by arthur.j.odwyer
[libc++] Remove more unnecessary _VSTD:: from type names. NFCI.

Differential Revision: https://reviews.llvm.org/D102181
The file was modifiedlibcxx/include/experimental/type_traits
The file was modifiedlibcxx/include/__memory/allocator_traits.h
The file was modifiedlibcxx/include/algorithm
The file was modifiedlibcxx/include/type_traits
The file was modifiedlibcxx/include/memory
The file was modifiedlibcxx/include/experimental/functional
The file was modifiedlibcxx/include/random
The file was modifiedlibcxx/include/functional
Commit 668dccc396da4f593ac87c92dc0eb7bc983b5762 by a-phipps
Revert "Fix branch coverage merging in FunctionCoverageSummary::get() for instantiation"

This reverts commit 6400905a615282c83a2fc6e49e57ff716aa8b4de.
The file was modifiedllvm/test/tools/llvm-cov/branch-templates.cpp
The file was modifiedllvm/tools/llvm-cov/CoverageSummaryInfo.cpp
The file was modifiedllvm/tools/llvm-cov/CoverageSummaryInfo.h
Commit dc00cbb5053895356955a6dc03632d4fa05048e3 by craig.topper
[RISCV] Match trunc_vector_vl+sra_vl/srl_vl with splat shift amount to vnsra/vnsrl.

Limited to splats because we would need to truncate the shift
amount vector otherwise.

I tried to do this with new ISD nodes and a DAG combine to
avoid such a large pattern, but we don't form the splat until
LegalizeDAG and need DAG combine to remove a scalable->fixed->scalable
cast before it becomes visible to the shift node. By the time that
happens we've already visited the truncate node and won't revisit it.

I think I have an idea how to improve i64 on RV32 I'll save for a
follow up.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D102019
The file was addedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-vnsra-vnsrl.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
Commit 5f78ba001ca23ab826b9be823fc8ac0a0e5d2237 by lebedev.ri
[X86][Codegen] Shift amount mod: sh? i64 x, (32-y) --> sh? i64 x, -(y+32)

I've seen this in the RawSpeed's BitPumpMSB*::push() hotpath,
after fixing the buffer abstraction to a more sane one,
when looking into a +5% runtime regression.
I was hoping that this would fix it, but it does not look it does.

This seems to be at least not worse than the original pattern.
But i'm actually mainly interested in the case where we already
compute `(y+32)` (see last test),

https://alive2.llvm.org/ce/z/ZCzJio

Reviewed By: spatel

Differential Revision: https://reviews.llvm.org/D101944
The file was modifiedllvm/test/CodeGen/X86/64-bit-shift-by-32-minus-y.ll
The file was modifiedllvm/lib/Target/X86/X86ISelDAGToDAG.cpp
Commit ce6e4f27dd72f834502f47176d84869a1f509d7b by craig.topper
[RISCV] Use fractional LMULs for fixed length types smaller than riscv-v-vector-bits-min.

My thought process is that if v2i64 is an LMUL=1 type then v2i32
should be an LMUL=1/2 type. We limit the fractional LMUL so that
SEW=64 clips to LMUL=1, SEW=32 clips to LMUL=1/2, etc. This
ensures there's always a fractional LMUL available to truncate a type.
This does reduce the number of vsetvlis in some cases.

Some tests increase vsetvlis because the best container type for a
mask type is dependent on the LMUL+SEW that the mask was produced
from, but you can't tell that from the type. I think this is
something we need to solve this in the machine IR when optimizing
vsetvlis.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D101215
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-fp.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-vremu-vp.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-select-int.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrsub-vp.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-splat.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-exttrunc.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-vand-vp.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.cpp
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsrl-vp.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-vor-vp.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-int.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-vxor-vp.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmul-vp.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-load-fp.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-logic.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmin.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-select-fp.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsra-vp.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-stepvector-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-setcc.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-splat.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-vshl-vp.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-conv.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdiv-vp.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-extload-truncstore.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-load-store.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-stepvector-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmax.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsub-vp.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-load-int.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-vreductions-mask.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrem-vp.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-bitcast.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdivu-vp.ll
The file was modifiedllvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll
Commit db13f832a1eec7427762c1ef1f56f169518f1abe by zoecarver
[libcxx][tests] Fix incomplte.verify tests by disabling them on clang-10.

For some reason clang-10 can't match the expected errors produced by
passing icomplete arrays to range access functions. Disabling the tests
is a stop-gap solution to fix the bots.
The file was modifiedlibcxx/test/std/ranges/range.access/range.access.cend/incomplete.compile.verify.cpp
The file was modifiedlibcxx/test/std/ranges/range.access/range.prim/empty.incomplete.verify.cpp
The file was modifiedlibcxx/test/std/ranges/range.access/range.access.cbegin/incomplete.compile.verify.cpp
The file was modifiedlibcxx/test/std/ranges/range.access/range.access.end/incomplete.compile.verify.cpp
The file was modifiedlibcxx/test/std/ranges/range.access/range.access.begin/incomplete.compile.verify.cpp
Commit 4f80340fb6712f5f1e97e7667bfd5cffa7d684b7 by llvm-dev
[X86][SSE] Add tests for permute(phaddw(phaddw(x,y),phaddw(z,w))) -> phaddw(phaddw(),phaddw()) folds.

We currently only fold if NumEltsPerLane == 4
The file was modifiedllvm/test/CodeGen/X86/horizontal-shuffle-4.ll
Commit eccb925147d5f262a3e74cc050d0665dd4e6d8db by a-phipps
Reland "[Coverage] Fix branch coverage merging in FunctionCoverageSummary::get() for instantiation""

Originally landed in: 6400905a615282c83a2fc6e49e57ff716aa8b4de
Reverted in: 668dccc396da4f593ac87c92dc0eb7bc983b5762

Fix branch coverage merging in FunctionCoverageSummary::get() for instantiation
groups.

This change corrects the implementation for the branch coverage summary to do
the same thing for branches that is done for lines and regions.  That is,
across function instantiations in an instantiation group, the maximum branch
coverage found in any of those instantiations is returned, with the total
number of branches being the same across instantiations.

Differential Revision: https://reviews.llvm.org/D102193
The file was modifiedllvm/test/tools/llvm-cov/branch-templates.cpp
The file was modifiedllvm/tools/llvm-cov/CoverageSummaryInfo.cpp
The file was modifiedllvm/tools/llvm-cov/CoverageSummaryInfo.h
Commit 1c7c6f2b106250d63905d7cde99a4559f0bb4978 by Lang Hames
Revert "[ORC-RT] Add unit test infrastructure, extensible_rtti..."

This reverts commit 6d263b6f1c9 while I investigate the CMake failures that it
causes in some configurations.
The file was modifiedcompiler-rt/lib/orc/CMakeLists.txt
The file was removedcompiler-rt/lib/orc/unittests/orc_unit_test_main.cpp
The file was modifiedcompiler-rt/cmake/config-ix.cmake
The file was removedcompiler-rt/lib/orc/unittests/CMakeLists.txt
The file was addedcompiler-rt/lib/orc/placeholder.cpp
The file was removedcompiler-rt/lib/orc/extensible_rtti.cpp
The file was removedcompiler-rt/lib/orc/unittests/extensible_rtti_test.cpp
The file was removedcompiler-rt/lib/orc/extensible_rtti.h
Commit cba508fb678798094a4fd668ce6bf4225fc73509 by Jonas Devlieghere
[TextAPI] Reformat llvm_unreachable message

Change llvm_unreachable message from "Unknown llvm.MachO.PlatformKind
enum" to "Unknown llvm::MachO::PlatformKind enum".

Differential revision: https://reviews.llvm.org/D102250
The file was modifiedllvm/lib/TextAPI/Platform.cpp
Commit 5a9497d6890145da74325dfcb032ad2963b5da3f by psteinfeld
[flang] Allow large and erroneous ac-implied-do's

We sometimes unroll an ac-implied-do of an array constructor into a flat list
of values.  We then re-analyze the array constructor that contains the
resulting list of expressions.  Such a list may or may not contain errors.

But when processing an array constructor with an unrolled ac-implied-do, the
compiler was building an expression to represent the extent of the resulting
array constructor containing the list of values.  The number of operands
in this extent expression was based on the number of elements in the
unrolled list of values.  For very large lists, this created an
expression so large that it could not be evaluated by the compiler
without overflowing the stack.

I fixed this by continuously folding the extent expression as each operand is
added to it.  I added the test .../flang/test/Semantics/array-constr-big.f90
that will cause the compiler to seg fault without this change.

Also, when the unrolled ac-implied-do expression contains errors, we were
repeating the same error message referencing the same source line for every
instance of the erroneous expression in the unrolled list.  This potentially
resulted in a very long list of messages for a single error in the source code.

I fixed this by comparing the message being emitted to the previously emitted
message.  If they are the same, I do not emit the message.  This change is also
tested by the new test array-constr-big.f90.

Several of the existing tests had duplicate error messages for the same source
line, and this change caused differences in their output.  So I adjusted the
tests to match the new message emitting behavior.

Differential Revision: https://reviews.llvm.org/D102210
The file was modifiedflang/test/Semantics/io06.f90
The file was modifiedflang/lib/Parser/message.cpp
The file was modifiedflang/test/Semantics/omp-atomic.f90
The file was modifiedflang/test/Semantics/omp-clause-validity01.f90
The file was addedflang/test/Semantics/array-constr-big.f90
The file was modifiedflang/test/Semantics/allocate02.f90
The file was modifiedflang/include/flang/Evaluate/shape.h
The file was modifiedflang/test/Semantics/omp-flush01.f90
The file was modifiedflang/include/flang/Parser/message.h
The file was modifiedflang/test/Semantics/resolve70.f90
Commit e0b6c99288bf1798ccc80aa0c5c7940c17665e69 by Lang Hames
Re-apply "[ORC-RT] Add unit test infrastructure, extensible_rtti..."

This reapplies 6d263b6f1c9 (which was reverted in 1c7c6f2b106) with a fix for a
CMake issue.
The file was modifiedcompiler-rt/lib/orc/CMakeLists.txt
The file was addedcompiler-rt/lib/orc/unittests/CMakeLists.txt
The file was addedcompiler-rt/lib/orc/extensible_rtti.cpp
The file was addedcompiler-rt/lib/orc/unittests/orc_unit_test_main.cpp
The file was addedcompiler-rt/lib/orc/extensible_rtti.h
The file was removedcompiler-rt/lib/orc/placeholder.cpp
The file was addedcompiler-rt/lib/orc/unittests/extensible_rtti_test.cpp
The file was modifiedcompiler-rt/cmake/config-ix.cmake
Commit 9ab49ae55dd7b928c2b806adccf6d07a89e59102 by thakis
[lld/mac] Implement -sectalign

clang sometimes passes this flag along (see D68351), so we should implement it.

Differential Revision: https://reviews.llvm.org/D102247
The file was modifiedlld/MachO/Config.h
The file was modifiedlld/MachO/OutputSegment.cpp
The file was modifiedlld/MachO/Options.td
The file was addedlld/test/MachO/sectalign.s
The file was modifiedlld/MachO/Driver.cpp
Commit 0fd0a010a1ed2ce761d20bfc6378e5bbaa75c8de by pirama
[git-clang-format] Do not apply clang-format to symlinks

This fixes PR46992.

Git stores symlinks as text files and we should not format them even if
they have one of the requested extensions.

(Move the call to `cd_to_toplevel()` up a few lines so we can also print
the skipped symlinks during verbose output.)

Differential Revision: https://reviews.llvm.org/D101878
The file was modifiedclang/tools/clang-format/git-clang-format
The file was modifiedclang/docs/ReleaseNotes.rst
Commit 68de58cd649cb3a3e94a1c9552ebf2a18bb9d040 by martin
[libcxx] [test] Fix filesystem permission tests for windows

On Windows, the permission bits are mapped down to essentially only
two possible states; readonly or readwrite. Normalize the checked
permission bitmask to match what the implementation will return.

Differential Revision: https://reviews.llvm.org/D101728
The file was modifiedlibcxx/test/support/filesystem_test_helper.h
The file was modifiedlibcxx/test/std/input.output/filesystems/fs.op.funcs/fs.op.permissions/permissions.pass.cpp
The file was modifiedlibcxx/test/std/input.output/filesystems/fs.op.funcs/fs.op.copy_file/copy_file.pass.cpp
Commit 49755871ad0c24ed970c0a4f2c51f90488b0ddd2 by silvasean
[mlir][ODS]: Add per-op cppNamespace.

This is useful for dialects that have logical subparts.

Differential Revision: https://reviews.llvm.org/D102200
The file was modifiedmlir/include/mlir/TableGen/Operator.h
The file was modifiedmlir/lib/TableGen/Operator.cpp
The file was modifiedmlir/include/mlir/IR/OpBase.td
The file was modifiedmlir/test/mlir-tblgen/dialect.td
The file was modifiedmlir/tools/mlir-tblgen/OpDefinitionsGen.cpp
The file was modifiedmlir/include/mlir/TableGen/CodeGenHelpers.h
Commit 61cbbba7a645a1d87db9a80867c84a788ab2ea9c by efriedma
[ArgumentPromotion] Fix byval alignment handling.

Make sure the alignment of the generated operations matches the
alignment of the byval argument.  Previously, we were just ignoring
alignment and getting lucky.

While I'm here, also delete the unnecessary "tail" handling.
Passing a pointer to a byval argument to a "tail" call is UB, so
rewriting to an alloca doesn't require any special handling.

Differential Revision: https://reviews.llvm.org/D89819
The file was modifiedllvm/test/Transforms/ArgumentPromotion/byval.ll
The file was modifiedllvm/test/Transforms/ArgumentPromotion/dbg.ll
The file was modifiedllvm/lib/Transforms/IPO/ArgumentPromotion.cpp
The file was modifiedllvm/test/Transforms/ArgumentPromotion/byval-2.ll
The file was removedllvm/test/Transforms/ArgumentPromotion/tail.ll
The file was modifiedllvm/test/Transforms/ArgumentPromotion/attrs.ll
Commit ec27c5f170441ab54295830aa9f7d376406c6a0f by i
[RISCV] Prefer to lower MC_GlobalAddress operands to .Lfoo$local

Similar to X86 D73230 and AArch64 D101872

With this change, we can set dso_local in clang's -fpic -fno-semantic-interposition mode,
for default visibility external linkage non-ifunc-non-COMDAT definitions.

For such dso_local definitions, variable access/taking the address of a
function/calling a function will go through a local alias to avoid GOT/PLT.

Reviewed By: jrtc27, luismarques

Differential Revision: https://reviews.llvm.org/D101875
The file was modifiedllvm/lib/Target/RISCV/RISCVMCInstLower.cpp
The file was addedllvm/test/CodeGen/RISCV/elf-preemption.ll
Commit ae2b36e8bdfa612649c6f2d8b6b9079679cb2572 by Amara Emerson
[AArch64][GlobalISel] Support truncstorei8/i16 w/ combine to form truncating G_STOREs.

This needs some tablegen changes so that we can actually import the patterns properly.

Differential Revision: https://reviews.llvm.org/D102204
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll
The file was modifiedllvm/include/llvm/Target/TargetSelectionDAG.td
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
The file was addedllvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-truncstore.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/select-store.mir
The file was modifiedllvm/utils/TableGen/GlobalISelEmitter.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64Combine.td
Commit 129f466e222e13fdf680356831bb935e1229bdf4 by i
[GlobalOpt] Remove heap SROA

GlobalOpt implements a heap SROA (SROA for an malloc allocatated struct or array
of structs) which is largely undertested (heap-sra-[1234].ll are basically the
same test with very little difference) and does not trigger at all when
bootstrapping clang (it only supports the case of one single store).

The heap SROA implementation causes PR50027 (GEP is not properly handled; crash or miscompile).
Just drop the implementation. I have deleted some obviously duplicated tests
but kept `heap-sra-[12]{,-no-nullopt}.ll`.

Reviewed By: aeubanks

Differential Revision: https://reviews.llvm.org/D102257
The file was modifiedllvm/test/Transforms/GlobalOpt/MallocSROA-section.ll
The file was modifiedllvm/test/Transforms/GlobalOpt/heap-sra-1.ll
The file was removedllvm/test/Transforms/GlobalOpt/heap-sra-3.ll
The file was removedllvm/test/Transforms/GlobalOpt/heap-sra-4-no-null-opt.ll
The file was modifiedllvm/test/Transforms/GlobalOpt/heap-sra-phi.ll
The file was modifiedllvm/test/Transforms/GlobalOpt/heap-sra-2.ll
The file was removedllvm/test/Transforms/GlobalOpt/heap-sra-3-no-null-opt.ll
The file was removedllvm/test/Transforms/GlobalOpt/heap-sra-4.ll
The file was modifiedllvm/lib/Transforms/IPO/GlobalOpt.cpp
Commit 97e04d41e646aa13b0cc5ff3812bfb7305fa4756 by lebedev.ri
[X86] X86TTIImpl::getInterleavedMemoryOpCostAVX2(): canonicalize to integer type

This way we don't have to duplicate i32/f32 and i64/f64 entries,
which was already forgotten to be done for a few tuples.
The file was modifiedllvm/lib/Target/X86/X86TargetTransformInfo.cpp
Commit b2f227c6c87c16fa593e643a487efd9326249066 by sbc
[lld][WebAssembly] Convert test to assembly. NFC.

Differential Revision: https://reviews.llvm.org/D102264
The file was addedlld/test/wasm/reloc-addend.s
The file was removedlld/test/wasm/reloc-addend.ll
Commit 2075f2b296b0fa90cb7597f0f318232940d29e95 by i
[clang] Support -fpic -fno-semantic-interposition for RISCV

-fno-semantic-interposition (only effective with -fpic) can optimize default
visibility external linkage (non-ifunc-non-COMDAT) variable access and function
calls to avoid GOT/PLT, by using local aliases, e.g.
```
int var;
__attribute__((optnone)) int fun(int x) { return x * x; }
int test() { return fun(var); }
```

-fpic (var and fun are dso_preemptable)
```
test:
.LBB1_1:
        auipc   a0, %got_pcrel_hi(var)
        ld      a0, %pcrel_lo(.LBB1_1)(a0)
        lw      a0, 0(a0)
// fun is preemptible by default in ld -shared mode. ld will create a PLT.
        tail    fun@plt
```

vs -fpic -fno-semantic-interposition (var and fun are dso_local)
```
test:
.Ltest$local:
.LBB1_1:
        auipc   a0, %pcrel_hi(.Lvar$local)
        addi    a0, a0, %pcrel_lo(.LBB1_1)
        lw      a0, 0(a0)
// The assembler either resolves .Lfun$local at assembly time (-mno-relax
// -fno-function-sections), or produces a relocation referencing a non-preemptible
// local symbol (which can avoid PLT).
        tail    .Lfun$local
```

Note: Clang's default -fpic is more aggressive than GCC -fpic: interprocedural
optimizations (including inlining) are available but local aliases are not used.
-fpic -fsemantic-interposition can disable interprocedural optimizations.

Depends on D101875

Reviewed By: luismarques

Differential Revision: https://reviews.llvm.org/D101876
The file was modifiedclang/test/Driver/fsemantic-interposition.c
The file was modifiedclang/lib/Driver/ToolChains/Clang.cpp
Commit f90abac6caab3b44e6a000de8cb72d204e74eb76 by michael.p.rice
[OpenMP] Use compound operators for reduction combiner if available.

The OpenMP spec seems to require the compound operators be used for
+, *, &, |, and ^ reduction.  So use these if a class has those operators.
If not try the simple operators as we did previously to limit the impact
to existing code.

Fixes: https://bugs.llvm.org/show_bug.cgi?id=48584

Differential Revision: https://reviews.llvm.org/D101941
The file was modifiedclang/test/OpenMP/sections_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/parallel_for_simd_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/taskgroup_task_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/teams_distribute_simd_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/master_taskloop_simd_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/for_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/target_teams_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/target_teams_distribute_parallel_for_simd_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/target_parallel_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/parallel_sections_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/target_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/parallel_master_taskloop_simd_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/task_in_reduction_message.cpp
The file was modifiedclang/test/OpenMP/taskloop_simd_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/teams_distribute_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/nvptx_target_parallel_reduction_codegen_tbaa_PR46146.cpp
The file was modifiedclang/test/OpenMP/target_teams_distribute_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/teams_distribute_parallel_for_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/target_teams_distribute_parallel_for_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/teams_distribute_parallel_for_simd_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/target_parallel_for_reduction_messages.cpp
The file was modifiedclang/lib/Sema/SemaOpenMP.cpp
The file was modifiedclang/test/OpenMP/taskloop_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/distribute_parallel_for_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/master_taskloop_in_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/parallel_master_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/taskloop_in_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/parallel_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/distribute_parallel_for_simd_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/parallel_master_taskloop_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/simd_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/target_teams_distribute_simd_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/distribute_simd_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/target_parallel_for_simd_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/taskloop_simd_in_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/master_taskloop_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/teams_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/master_taskloop_simd_in_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/for_simd_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/parallel_for_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/target_simd_reduction_messages.cpp
The file was addedclang/test/OpenMP/reduction_compound_op.cpp
Commit 384dd9ddaf616a1563ee1c1a8a1347b7658e7a70 by vvereschaka
[libc++] Run `substitutes-in-compile-flags.sh.cpp` test on Windows.

Fix for substitutes-in-compile-flags.sh.cpp to run it properly on Windows platform.

Differential Revision: https://reviews.llvm.org/D102048
The file was modifiedlibcxx/test/libcxx/selftest/additional_compile_flags/substitutes-in-compile-flags.sh.cpp
Commit 9558b602b22cb7d681757c5f56d941e39a9d9d19 by jingham
Add an "interrupt timeout" to Process, and pipe that through the
ProcessGDBRemote plugin layers.

Also fix a bug where if we tried to interrupt, but the ReadPacket
wakeup timer woke us up just after the timeout, we would break out
the switch, but then since we immediately check if the response is
empty & fail if it is, we could end up actually only giving a
small interval to the interrupt.

Differential Revision: https://reviews.llvm.org/D102085
The file was modifiedlldb/source/Plugins/Process/gdb-remote/GDBRemoteClientBase.h
The file was modifiedlldb/source/Target/TargetProperties.td
The file was modifiedlldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.h
The file was modifiedlldb/unittests/Process/gdb-remote/GDBRemoteCommunicationClientTest.cpp
The file was modifiedlldb/source/Target/Process.cpp
The file was modifiedlldb/include/lldb/Target/Process.h
The file was modifiedlldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp
The file was modifiedlldb/unittests/tools/lldb-server/tests/TestClient.cpp
The file was modifiedlldb/source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext.cpp
The file was modifiedlldb/source/Plugins/Process/gdb-remote/GDBRemoteClientBase.cpp
The file was modifiedlldb/test/API/functionalities/gdb_remote_client/TestHaltFails.py
The file was modifiedlldb/source/Plugins/Platform/gdb-server/PlatformRemoteGDBServer.cpp
The file was modifiedlldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
The file was modifiedlldb/unittests/Process/gdb-remote/GDBRemoteClientBaseTest.cpp
Commit b49a798e71f922a68628ad9e31ca12fdb864c2f5 by sbc
[lld][WebAssembly] Remove relocation target verification

We have this extra step in wasm-ld that doesn't exist in other lld
backend which verifies the existing contents of the relocation targets.
This was originally intended as an extra form of double checking and an
aid to compiler developers.   However it has always been somewhat
controversial and there have been suggestions in the past the we simply
remove it.

My motivation for removing it now is that its causing me a headache
when trying to fix an issue with negative addends.  In the case of
negative addends that final result can be wrapped/negative but this
checking code would require significant modification to be able to deal
with that case.  For example with some test cases I'm looking at I'm
seeing error like this:

```
wasm-ld: warning: /usr/local/google/home/sbc/dev/wasm/llvm-build/tools/lld/test/wasm/Output/merge-string.s.tmp.o:(.rodata_relocs): unexpected existing value for R_WASM_MEMORY_ADDR_I32: existing=FFFFFFFA expected=FFFFFFFFFFFFFFFA
```

Rather than try to refactor `calcExpectedValue` to somehow return two
different types of results (32 and 64-bit) depending on the relocation
type, I think we can just remove this code.

Differential Revision: https://reviews.llvm.org/D102265
The file was modifiedlld/wasm/InputFiles.cpp
The file was modifiedlld/test/wasm/reloc-addend.s
The file was modifiedlld/wasm/InputChunks.cpp
The file was modifiedlld/wasm/InputFiles.h
Commit 731206f3684af5979e3a794970db83f9a34b4541 by riddleriver
[mlir] Move move capture in SparseElementsAttr::getValues

This was a TODO for the move to C++14. Now that the move has been completed, we can resolve it.
The file was modifiedmlir/include/mlir/IR/BuiltinAttributes.h
Commit 2a73b7bd8cf7620fc0e478ac838b07ee6649dd8a by Vitaly Buka
[NFC][LSAN] Limit the number of concurrent threads is the test

Test still fails with D88184 reverted.

The test was flaky on https://bugs.chromium.org/p/chromium/issues/detail?id=1206745 and
https://lab.llvm.org/buildbot/#/builders/sanitizer-x86_64-linux

Reviewed By: morehouse

Differential Revision: https://reviews.llvm.org/D102218
The file was modifiedcompiler-rt/test/lsan/TestCases/many_threads_detach.cpp
Commit 69069509b2d3cb0e0bcf6e38e0ab05c432adc763 by Amara Emerson
[AArch64][GlobaISel] Mark target generic instructions as HasNoSideEffects.

One test needed updating because the newly side-effect-free instructions were
now being DCE'd.
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrGISel.td
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/select-ext.mir
Commit ffbffaf6b6b0fc06abb7b43ec8de8bc61d941bc7 by albionapc
[PowerPC] Improve codegen for int-to-fp conversion of subword vector extract

When an integer is converted into floating point in subword vector extract,
it can be done in 2 instructions instead of the 3+ instructions it generates
right now. This patch removes the uncessary generation.

Differential: https://reviews.llvm.org/D100604
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrVSX.td
The file was modifiedllvm/test/CodeGen/PowerPC/uint-to-fp-v4i32.ll
The file was modifiedllvm/test/CodeGen/PowerPC/vec_conv_i8_to_fp32_elts.ll
The file was addedllvm/test/CodeGen/PowerPC/vec-extract-itofp.ll
The file was modifiedllvm/test/CodeGen/PowerPC/vec_conv_i16_to_fp32_elts.ll
Commit 4fb0aaf03381473ec8af727edb4b5d59b64b0d60 by Andrey.Churbanov
[OpenMP] Changes to enable MSVC ARM64 build of libomp

This is the first in a series of changes to the OpenMP runtime
that have been done internally by Microsoft. This patch makes
the necessary changes to enable libomp.dll to build with
the MSVC compiler targeting ARM64.

Differential Revision: https://reviews.llvm.org/D101173
The file was modifiedopenmp/runtime/src/z_Windows_NT-586_util.cpp
The file was modifiedopenmp/runtime/src/kmp_atomic.cpp
The file was modifiedopenmp/runtime/src/kmp.h
The file was modifiedopenmp/runtime/src/kmp_platform.h
The file was modifiedopenmp/runtime/src/CMakeLists.txt
The file was modifiedopenmp/runtime/src/dllexports
The file was modifiedopenmp/runtime/src/kmp_os.h
Commit d092dd56aed8af64425446544ca7c9a0616d86ce by craig.topper
[RISCV] Regenerate stepvector.ll. NFC

It looks like the RV32 and RV64 prefixes were removed from the
RUN lines while another patch was in review that added check
lines that used them.
The file was modifiedllvm/test/CodeGen/RISCV/rvv/stepvector.ll
Commit a7757f6c22e45e84e56da79af67fe29dd1c224f5 by eugenis
[hwasan] Stress test for thread creation.

This test has two modes - testing reused threads with multiple loops of
batch create/join, and testing new threads with a single loop of
create/join per fork.

The non-reuse variant catches the problem that was fixed in D101881 with
a high probability.

Differential Revision: https://reviews.llvm.org/D101936
The file was addedcompiler-rt/test/hwasan/TestCases/Linux/create-thread-stress.cpp
Commit 4433f4601e8a8e36ddd9bb6f6ed394bda353b828 by Austin.Kerbow
[AMDGPU] Fix extra waitcnt being added with BUFFER_INVL2

The waitcnt pass would increment the number of vmem events for some buffer
invalidates that were not handled by the pass.

Reviewed By: rampitec

Differential Revision: https://reviews.llvm.org/D102252
The file was modifiedllvm/lib/Target/AMDGPU/BUFInstructions.td
The file was modifiedllvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
The file was modifiedllvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
The file was modifiedllvm/test/CodeGen/AMDGPU/waitcnt-preexisting.mir
The file was modifiedllvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
Commit ebdcebfcb4b522a81290f67dcbb7222ff7f9d052 by aorlov
Removed unnecessary introduction of semi-colons.
The file was modifiedllvm/include/llvm/DebugInfo/Symbolize/DIPrinter.h
Commit a9bbbaaa8810b22c9672694d576e3a0a210af54a by riddleriver
[mlir] Elide large elements attrs when printing Operations in diagnostics

Diagnostics are intended to be read by users, and in most cases displayed in a terminal. When not eliding huge element attributes, in some cases we end up dumping hundreds of megabytes(gigabytes) to the terminal (or logs), completely obfuscating the main diagnostic being shown.

Differential Revision: https://reviews.llvm.org/D102272
The file was modifiedmlir/lib/IR/Diagnostics.cpp
Commit 764ad3b3fafbf57ca916715625fffb7df5dbeb92 by rob.suderman
[mlir][tosa] Tosa elementwise broadcasting had some minor bugs

Updated tests to include broadcast of left and right. Includes
bypass if in-type and out-type match shape (no broadcasting).

Differential Revision: https://reviews.llvm.org/D102276
The file was modifiedmlir/test/Conversion/TosaToLinalg/tosa-to-linalg.mlir
The file was modifiedmlir/lib/Conversion/TosaToLinalg/TosaToLinalg.cpp
Commit 15565403722ec37d8b1a3ee8625ee2e8efcd96ee by nikita.ppv
[InstCombine] Clean up one-hot merge optimization (NFC)

Remove the requirement that the instruction is a BinaryOperator,
make the predicate check more compact and use slightly more
meaningful naming for the and operands.
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineInternal.h
Commit 3a64b7080d5033b3bd6f28fbac4a24d9490dc3c3 by evandro.menezes
[RISCV] Move instruction information into the RISCVII namespace (NFC)

Move instruction attributes into the `RISCVII` namespace and add associated helper functions.

Differential Revision: https://reviews.llvm.org/D102268
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.h
The file was modifiedllvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
The file was modifiedllvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
The file was modifiedllvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
The file was modifiedllvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
The file was modifiedllvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.cpp
The file was modifiedllvm/lib/Target/RISCV/RISCVMCInstLower.cpp
Commit 489a3531a42fe97c7fa00255fc5e8d31a610492d by phosek
[llvm-cov] Support for v4 format in convert-for-testing

v4 moves function records to a dedicated section so we need to write
and read it separately.

https://reviews.llvm.org/D100535
The file was modifiedllvm/lib/ProfileData/Coverage/CoverageMappingReader.cpp
The file was modifiedllvm/tools/llvm-cov/TestingSupport.cpp
Commit d3f89d4d16883b2bcf5f032152f10e384b53d92a by congzhecao
Revert "[LoopInterchange] Fix legality for triangular loops"

This reverts commit 29342291d25b83da97e74d75004b177ba41114fc.

The test case requires an assert build. Will add REQUIRES and re-commit.
The file was modifiedllvm/lib/Transforms/Scalar/LoopInterchange.cpp
The file was removedllvm/test/Transforms/LoopInterchange/inner-indvar-depend-on-outer-indvar.ll
Commit 46475a79f85b230fde3e7de8966c96bef14f0d24 by wei.huang
[AIX][TLS] Diagnose use of unimplemented TLS models

Add front end diagnostics to report error for unimplemented TLS models set by
- compiler option `-ftls-model`
- attributes like `__thread int __attribute__((tls_model("local-exec"))) var_name;`

Reviewed by: aaron.ballman, nemanjai, PowerPC

Differential Revision: https://reviews.llvm.org/D102070
The file was modifiedclang/include/clang/Basic/DiagnosticSemaKinds.td
The file was modifiedclang/include/clang/Basic/DiagnosticDriverKinds.td
The file was modifiedclang/lib/Sema/SemaDeclAttr.cpp
The file was addedclang/test/Sema/aix-attr-tls_model.c
The file was modifiedclang/lib/Frontend/CompilerInvocation.cpp
The file was addedclang/test/CodeGen/aix-tls-model.cpp
Commit cbcfca343f02876cef2b5ca3f27a037bab8fa90f by Lang Hames
[JITLink] Make LinkGraph debug dumps more readable.

This commit reorders some fields and fixes the width of others to try to
maintain more consistent columns. It also switches to long-hand scope
and linkage names, since LinkGraph dumps aren't read often enough for
single-character codes to be memorable.
The file was modifiedllvm/lib/ExecutionEngine/JITLink/JITLink.cpp
Commit 74a96b4c98434e328eeca0afc85dc7053133a7d2 by Lang Hames
[JITLink][x86-64] Add an x86_64 PointerSize constexpr.

This can be used in place of magic '8' values in generic x86-64 utilities.
The file was modifiedllvm/include/llvm/ExecutionEngine/JITLink/x86_64.h
The file was modifiedllvm/lib/ExecutionEngine/JITLink/x86_64.cpp
Commit a0162a81b1377331c3e0ebb58ac349b2ffd7b598 by Lang Hames
[JITLink][MachO/x86_64] Expose API for creating eh-frame fixing passes.

These can be used to create eh-frame section fixing passes outside the usual
linker pipeline, which can be useful for tests and tools that just want to
verify or dump graphs.
The file was modifiedllvm/include/llvm/ExecutionEngine/JITLink/MachO_x86_64.h
The file was modifiedllvm/lib/ExecutionEngine/JITLink/MachO_x86_64.cpp
Commit 8280ece0c972db24e51aae5074ca5433002f1071 by phosek
[Coverage] Support overriding compilation directory

When making compilation relocatable, for example in distributed
compilation scenarios, we want to set compilation dir to a relative
value like `.` but this presents a problem when generating reports
because if the file path is relative as well, for example `..`, you
may end up writing files outside of the output directory.

This change introduces a flag that allows overriding the compilation
directory that's stored inside the profile with a different value that
is absolute.

Differential Revision: https://reviews.llvm.org/D100232
The file was modifiedllvm/tools/llvm-cov/CoverageViewOptions.h
The file was modifiedllvm/unittests/ProfileData/CoverageMappingTest.cpp
The file was modifiedllvm/include/llvm/ProfileData/Coverage/CoverageMapping.h
The file was modifiedllvm/include/llvm/ProfileData/Coverage/CoverageMappingReader.h
The file was addedllvm/test/tools/llvm-cov/Inputs/compilation_dir.proftext
The file was modifiedllvm/lib/ProfileData/Coverage/CoverageMapping.cpp
The file was modifiedllvm/lib/ProfileData/Coverage/CoverageMappingReader.cpp
The file was addedllvm/test/tools/llvm-cov/Inputs/compilation_dir.covmapping
The file was addedllvm/test/tools/llvm-cov/compilation_dir.c
The file was modifiedllvm/tools/llvm-cov/CodeCoverage.cpp
Commit 40e3aa39bd68b554808ddcb096a63919f53f2e43 by congzhecao
[LoopInterchange] Fix legality for triangular loops

This is a bug fix in legality check.

When we encounter triangular loops such as the following form:
    for (int i = 0; i < m; i++)
      for (int j = 0; j < i; j++), or

    for (int i = 0; i < m; i++)
      for (int j = 0; j*i < n; j++),

we should not perform interchange since the number of executions
of the loop body will be different before and after interchange,
resulting in incorrect results.

Reviewed By: bmahjour

Differential Revision: https://reviews.llvm.org/D101305
The file was addedllvm/test/Transforms/LoopInterchange/inner-indvar-depend-on-outer-indvar.ll
The file was modifiedllvm/lib/Transforms/Scalar/LoopInterchange.cpp
Commit 5cb17728d19408725d4ced928ff3276dd4ffd1c9 by leonardchan
[clang][Fuchsia] Introduce compat multilibs

These are GCC-compatible multilibs that use the generic Itanium C++ ABI
instead of the Fuchsia C++ ABI.

Differential Revision: https://reviews.llvm.org/D102030
The file was modifiedclang/test/Driver/fuchsia.cpp
The file was addedclang/test/Driver/Inputs/basic_fuchsia_tree/lib/x86_64-unknown-fuchsia/compat/libc++.so
The file was modifiedclang/lib/Driver/ToolChains/Fuchsia.cpp
Commit d63860a05226d89f840a665134e2cb52c30ce4c4 by Lang Hames
[JITLink] Fix bogus format string.
The file was modifiedllvm/lib/ExecutionEngine/JITLink/JITLink.cpp
Commit fec2945998947f04d672e9c5f33b57f7177474c0 by rupprecht
Revert "[GVN] Clobber partially aliased loads."

This reverts commit 6c570442318e2d3b8b13e95c2f2f588d71491acb.

It causes assertion errors due to widening atomic loads, and potentially causes miscompile elsewhere too. Repro, also posted to D95543:

```
$ cat repro.ll
; ModuleID = 'repro.ll'
source_filename = "repro.ll"
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

%struct.widget = type { i32 }
%struct.baz = type { i32, %struct.snork }
%struct.snork = type { %struct.spam }
%struct.spam = type { i32, i32 }

@global = external local_unnamed_addr global %struct.widget, align 4
@global.1 = external local_unnamed_addr global i8, align 1
@global.2 = external local_unnamed_addr global i32, align 4

define void @zot(%struct.baz* %arg) local_unnamed_addr align 2 {
bb:
  %tmp = getelementptr inbounds %struct.baz, %struct.baz* %arg, i64 0, i32 1
  %tmp1 = bitcast %struct.snork* %tmp to i64*
  %tmp2 = load i64, i64* %tmp1, align 4
  %tmp3 = getelementptr inbounds %struct.baz, %struct.baz* %arg, i64 0, i32 1, i32 0, i32 1
  %tmp4 = icmp ugt i64 %tmp2, 4294967295
  br label %bb5

bb5:                                              ; preds = %bb14, %bb
  %tmp6 = load i32, i32* %tmp3, align 4
  %tmp7 = icmp ne i32 %tmp6, 0
  %tmp8 = select i1 %tmp7, i1 %tmp4, i1 false
  %tmp9 = zext i1 %tmp8 to i8
  store i8 %tmp9, i8* @global.1, align 1
  %tmp10 = load i32, i32* @global.2, align 4
  switch i32 %tmp10, label %bb11 [
    i32 1, label %bb12
    i32 2, label %bb12
  ]

bb11:                                             ; preds = %bb5
  br label %bb14

bb12:                                             ; preds = %bb5, %bb5
  %tmp13 = load atomic i32, i32* getelementptr inbounds (%struct.widget, %struct.widget* @global, i64 0, i32 0) acquire, align 4
  br label %bb14

bb14:                                             ; preds = %bb12, %bb11
  br label %bb5
}
$ opt -O2 repro.ll -disable-output
opt: /home/rupprecht/src/llvm-project/llvm/lib/Transforms/Utils/VNCoercion.cpp:496: llvm::Value *llvm::VNCoercion::getLoadValueForLoad(llvm::LoadInst *, unsigned int, llvm::Type *, llvm::Instruction *, const llvm::DataLayout &): Assertion `SrcVal->isSimple() && "Cannot widen volatile/atomic load!"' failed.
PLEASE submit a bug report to https://bugs.llvm.org/ and include the crash backtrace.
Stack dump:
0.      Program arguments: /home/rupprecht/dev/opt -O2 repro.ll -disable-output
...
```
The file was modifiedllvm/lib/Analysis/MemoryDependenceAnalysis.cpp
The file was modifiedllvm/lib/Transforms/Scalar/GVN.cpp
The file was modifiedllvm/include/llvm/Analysis/MemoryDependenceAnalysis.h
The file was modifiedllvm/test/Transforms/GVN/PRE/rle.ll
Commit 2bdfcf0cac148ada8d3ec36f551c45efb604ac49 by Matthew.Arsenault
GlobalISel: Move AArch64 AssignFnVarArg to base class

We can handle the distinction easily enough in the generic code, and
this makes it easier to abstract the selection of type/location from
the code to insert code.
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/CallLowering.h
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
Commit 24e2e5df0e7eb017c64142c1f5899146fa52abba by Matthew.Arsenault
GlobalISel: Split ValueHandler into assignment and emission classes

Currently the ValueHandler handles both selecting the type and
location for arguments, as well as inserting instructions needed to
handle them. Split this so that the determination of the argument
handling is independent of the function state. Currently the checks
for tail call compatibility do not follow the full assignment logic,
so it misses cases where arguments require nontrivial legalization.

This should help avoid targets ending up in a buggy state where the
argument evaluation may change in different contexts.
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
The file was modifiedllvm/lib/Target/X86/X86CallLowering.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/CallLowering.h
The file was modifiedllvm/lib/CodeGen/GlobalISel/CallLowering.cpp
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/call-translator-tail-call.ll
The file was modifiedllvm/lib/Target/ARM/ARMCallLowering.cpp
Commit 6ecbdb761ffd684dc5fe624c0058fe7527a01881 by Matthew.Arsenault
GlobalISel: Make constant fields const
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/CallLowering.h
Commit a15ed701ab30d0073f46139df850fe23b03fd3ac by Matthew.Arsenault
AMDGPU: Fix assert on constant load from addrspacecasted pointer

This was trying to create a bitcast between different address spaces.
The file was addedllvm/test/CodeGen/AMDGPU/amdgpu-late-codegenprepare.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULateCodeGenPrepare.cpp
Commit 6f5ddf67319b50664f3f5a4001723454696594b4 by Matthew.Arsenault
GlobalISel: Don't hardcode varargs=false in resultsCompatible
The file was modifiedllvm/lib/CodeGen/GlobalISel/CallLowering.cpp
Commit 697ac15a0fc71888c372667bdbc5583ab42d4695 by richard
Fix bad mangling of <data-member-prefix> for a closure in the initializer of a variable at global namespace scope.

This implements the direction proposed in
https://github.com/itanium-cxx-abi/cxx-abi/pull/126.

Differential Revision: https://reviews.llvm.org/D101968
The file was modifiedclang/include/clang/Basic/LangOptions.h
The file was modifiedclang/test/CodeGenCXX/mangle-lambda-explicit-template-params.cpp
The file was modifiedclang/lib/Frontend/CompilerInvocation.cpp
The file was modifiedclang/include/clang/Basic/CodeGenOptions.h
The file was modifiedclang/test/CodeGenCXX/clang-abi-compat.cpp
The file was modifiedclang/test/CodeGenCXX/lambda-expressions-nested-linkage.cpp
The file was modifiedclang/lib/AST/ItaniumMangle.cpp
Commit 3978333b71bff3516ad69aac484b808617976c7a by richard
Add test for PR50039.

I believe Clang's behavior is correct according to the standard here,
but this is an unusual situation for which we had no test coverage, so
I'm adding some.
The file was modifiedclang/test/SemaTemplate/temp_arg_nontype_cxx20.cpp
Commit bb726383ac7554857c62edd2d19e83dc713165ee by richard
Revert "Fix bad mangling of <data-member-prefix> for a closure in the initializer of a variable at global namespace scope."

This reverts commit 697ac15a0fc71888c372667bdbc5583ab42d4695, for which
review was not complete. That change was accidentally pushed when
an unrelated change was pushed.
The file was modifiedclang/test/CodeGenCXX/clang-abi-compat.cpp
The file was modifiedclang/lib/AST/ItaniumMangle.cpp
The file was modifiedclang/test/CodeGenCXX/lambda-expressions-nested-linkage.cpp
The file was modifiedclang/include/clang/Basic/LangOptions.h
The file was modifiedclang/include/clang/Basic/CodeGenOptions.h
The file was modifiedclang/lib/Frontend/CompilerInvocation.cpp
The file was modifiedclang/test/CodeGenCXX/mangle-lambda-explicit-template-params.cpp
Commit 19cedd3cd3ab2144f7e477bb90d5f7ba8e500abb by sbc
[lld][WebAssembly] Fix for string merging + negative addends

Don't include the relocation addend when calculating the
virtual address of a symbol.  Instead just pass the symbol's
offset and add the addend afterwards.

Without this fix we hit the `offset is outside the section`
error in MergeInputSegment::getSegmentPiece.

This fixes a real world error we were are seeing in emscripten.

Differential Revision: https://reviews.llvm.org/D102271
The file was modifiedlld/wasm/InputFiles.cpp
The file was modifiedlld/wasm/Symbols.cpp
The file was modifiedlld/wasm/Symbols.h
The file was modifiedlld/test/wasm/merge-string.s
Commit 0f2eb7e6e5dc2c1b5d1080160733b3a49e00c99c by jingham
This test is failing on Linux, skip while I investigate.

The gdb-remote tests are a bit artificial, depending on
Python threading, and sleeps.  So I'm not 100% surprised it doesn't
work straight up on another XSsystem.
The file was modifiedlldb/test/API/functionalities/gdb_remote_client/TestHaltFails.py
Commit cc79aaced0a405c7448c832a0974a694494496ca by Matthew.Arsenault
AMDGPU: Fix SILoadStoreOptimizer for gfx90a

This was hardcoding the register class to use for the newly created
pointer registers, violating the aligned VGPR requirement.
The file was addedllvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm-gfx90a.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
The file was modifiedllvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
Commit 10c309ad81e2be156ab44a83ee56cddea20637cc by jingham
Removing test...

Actually, I don't think this test is going to be stable enough
to be worthwhile.  Let me see if I can think of a better way to
test this.
The file was removedlldb/test/API/functionalities/gdb_remote_client/TestHaltFails.py
Commit 3f8be15f2911a3d3645030911be83a115bfe9e5c by congzhecao
[LoopInterchange] Handle lcssa PHIs with multiple predecessors

This is a bugfix in the transformation phase.

If the original outer loop header branches to both the inner loop
(header) and the outer loop latch, and if there is an lcssa PHI
node outside the loop nest, then after interchange the new outer latch
will have an lcssa PHI node inserted which has two predecessors, i.e.,
the original outer header and the original outer latch. Currently
the transformation assumes it has only one predecessor (the original
outer latch) and crashes, since the inserted lcssa PHI node does
not take both predecessors as incoming BBs.

Reviewed By: Whitney

Differential Revision: https://reviews.llvm.org/D100792
The file was modifiedllvm/lib/Transforms/Scalar/LoopInterchange.cpp
The file was modifiedllvm/test/Transforms/LoopInterchange/lcssa.ll
Commit 7d101e0f6a38b95f512dc5d78bc9b508f4ee6da0 by Vitaly Buka
[NFC][msan] Move setlocale test into sanitizer_common
The file was addedcompiler-rt/test/sanitizer_common/TestCases/setlocale.cpp
The file was removedcompiler-rt/test/msan/setlocale.cpp
Commit f653313d4aec6f92b224ef996a8ac236dbb48baf by chiahungduan
[mlir][AsmPrinter] Remove recursion while SSA naming

Address the TODO of removing recursion while SSA naming.

Reviewed By: mehdi_amini

Differential Revision: https://reviews.llvm.org/D102226
The file was modifiedmlir/lib/IR/AsmPrinter.cpp
Commit 04b2ada51c90a76b153eedafd8d52a2649695a7f by dvyukov
tsan: add a simple syscall test

Add a simple test that uses syscall annotations.
Just to ensure at least basic functionality works.
Also factor out annotated syscall wrappers into a separate
header file as they may be useful for future tests.

Reviewed By: vitalybuka

Differential Revision: https://reviews.llvm.org/D102223
The file was addedcompiler-rt/test/tsan/Linux/syscall.cpp
The file was addedcompiler-rt/test/tsan/Linux/syscall.h
The file was modifiedcompiler-rt/test/tsan/Linux/fork_syscall.cpp
Commit 5dad3d1ba9ad01152be21e94cfbbfb31659ea3e1 by dvyukov
tsan: mark sigwait as blocking

Add a test case reported in:
https://github.com/google/sanitizers/issues/1401
and fix it.
The code assumes sigwait will process other signals.

Reviewed By: vitalybuka

Differential Revision: https://reviews.llvm.org/D102057
The file was addedcompiler-rt/test/tsan/signal_block2.cpp
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_common_interceptors.inc
Commit 6d2df181638a34f5d4ebc0c92cfb6a30abf8588d by qiucofan
[VectorComine] Restrict single-element-store index to inbounds constant

Vector single element update optimization is landed in 2db4979. But the
scope needs restriction. This patch restricts the index to inbounds and
vector must be fixed sized. In future, we may use value tracking to
relax constant restrictions.

Reviewed By: fhahn

Differential Revision: https://reviews.llvm.org/D102146
The file was modifiedllvm/lib/Transforms/Vectorize/VectorCombine.cpp
The file was modifiedllvm/test/Transforms/VectorCombine/load-insert-store.ll
Commit 8214764f35e1b764fb939e18f16e11aa43073469 by dvyukov
tsan: declare annotations in test.h

We already declare subset of annotations in test.h.
But some are duplicated and declared in tests.
Move all annotation declarations to test.h.

Reviewed By: vitalybuka

Differential Revision: https://reviews.llvm.org/D102152
The file was modifiedcompiler-rt/test/tsan/thread_end_with_ignore3.cpp
The file was modifiedcompiler-rt/test/tsan/annotate_happens_before.cpp
The file was modifiedcompiler-rt/test/tsan/signal_sync2.cpp
The file was modifiedcompiler-rt/test/tsan/thread_name.cpp
The file was modifiedcompiler-rt/test/tsan/mutex_bad_unlock.cpp
The file was modifiedcompiler-rt/test/tsan/thread_end_with_ignore.cpp
The file was modifiedcompiler-rt/test/tsan/test.h
The file was modifiedcompiler-rt/test/tsan/mutex_bad_read_unlock.cpp
The file was modifiedcompiler-rt/test/tsan/benign_race.cpp
The file was modifiedcompiler-rt/test/tsan/ignore_sync.cpp
The file was modifiedcompiler-rt/test/tsan/thread_end_with_ignore2.cpp
The file was modifiedcompiler-rt/test/tsan/mutexset5.cpp
The file was modifiedcompiler-rt/test/tsan/mutex_double_lock.cpp
The file was modifiedcompiler-rt/test/tsan/mutex_bad_read_lock.cpp
Commit 53558ed8a0abaf2f457cfa3d98c85d0fa1e84b22 by dvyukov
sanitizer_common: fix SIG_DFL warning

Currently we have:

sanitizer_posix_libcdep.cpp:146:27: warning: cast between incompatible
  function types from ‘__sighandler_t’ {aka ‘void (*)(int)’} to ‘sa_sigaction_t’
  146 |     sigact.sa_sigaction = (sa_sigaction_t)SIG_DFL;

We don't set SA_SIGINFO, so we need to assign to sa_handler.
And SIG_DFL is meant for sa_handler, so this gets rid of both
compiler warning, type cast and potential runtime misbehavior.

Reviewed By: vitalybuka

Differential Revision: https://reviews.llvm.org/D102162
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_posix_libcdep.cpp
Commit 85a96d82ca76819df56c97b6b3b5d5d98a030d5d by Vitaly Buka
[symbolizer] Fix leak after D96883
The file was modifiedllvm/lib/DebugInfo/Symbolize/DIPrinter.cpp
Commit 23596fece043fa04206dcd5b26b4ca832e6741db by dvyukov
sanitizer_common: don't write into .rodata

setlocale interceptor imitates a write into result,
which may be located in .rodata section.
This is the only interceptor that tries to do this and
I think the intention was to initialize the range for msan.
So do that instead. Writing into .rodata shouldn't happen
(without crashing later on the actual write) and this
traps on my local tsan experiments.

Reviewed By: vitalybuka

Differential Revision: https://reviews.llvm.org/D102161
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_common_interceptors.inc
Commit f8306647fa05b7bf84dff12d731d03abf53b45fe by kbessonova
[libcxx][test] Split more debug mode tests

Split a few more debug mode tests missed in D100592.

Differential Revision: https://reviews.llvm.org/D102194
The file was modifiedlibcxx/test/libcxx/strings/basic.string/string.modifiers/erase_iter_iter_db3.pass.cpp
The file was addedlibcxx/test/libcxx/strings/basic.string/string.modifiers/erase_iter_iter_db5.pass.cpp
The file was addedlibcxx/test/libcxx/strings/basic.string/string.modifiers/erase_iter_iter_db8.pass.cpp
The file was addedlibcxx/test/libcxx/strings/basic.string/string.modifiers/erase_iter_db3.pass.cpp
The file was modifiedlibcxx/test/libcxx/strings/basic.string/string.modifiers/erase_iter_iter_db1.pass.cpp
The file was modifiedlibcxx/test/libcxx/strings/basic.string/string.modifiers/erase_iter_iter_db2.pass.cpp
The file was modifiedlibcxx/test/libcxx/strings/basic.string/string.modifiers/erase_iter_db1.pass.cpp
The file was addedlibcxx/test/libcxx/strings/basic.string/string.modifiers/erase_iter_iter_db6.pass.cpp
The file was modifiedlibcxx/test/libcxx/strings/basic.string/string.modifiers/erase_iter_iter_db4.pass.cpp
The file was addedlibcxx/test/libcxx/strings/basic.string/string.modifiers/erase_iter_iter_db7.pass.cpp
The file was modifiedlibcxx/test/libcxx/containers/sequences/vector/db_cindex.pass.cpp
The file was addedlibcxx/test/libcxx/containers/sequences/vector/db_cindex_2.pass.cpp
The file was modifiedlibcxx/test/libcxx/strings/basic.string/string.modifiers/erase_iter_db2.pass.cpp
The file was addedlibcxx/test/libcxx/strings/basic.string/string.modifiers/erase_iter_db4.pass.cpp
Commit febbe4b5a0ab0cb6f8ada6cd1ead4bb1f565bda8 by qiucofan
[PowerPC] [Clang] Enable float128 feature on VSX targets

Reviewed By: nemanjai, steven.zhang

Differential Revision: https://reviews.llvm.org/D92815
The file was modifiedclang/lib/Basic/Targets/PPC.cpp
The file was modifiedclang/test/Driver/ppc-f128-support-check.c
Commit 2721e27c3aa34841db3fc0b4da25890288652d50 by dvyukov
sanitizer_common: deduplicate CheckFailed

We have some significant amount of duplication around
CheckFailed functionality. Each sanitizer copy-pasted
a chunk of code. Some got random improvements like
dealing with recursive failures better. These improvements
could benefit all sanitizers, but they don't.

Deduplicate CheckFailed logic across sanitizers and let each
sanitizer only print the current stack trace.
I've tried to dedup stack printing as well,
but this got me into cmake hell. So let's keep this part
duplicated in each sanitizer for now.

Reviewed By: vitalybuka

Differential Revision: https://reviews.llvm.org/D102221
The file was modifiedcompiler-rt/test/msan/check-handler.cpp
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_common.h
The file was modifiedcompiler-rt/lib/msan/msan.h
The file was modifiedcompiler-rt/lib/hwasan/hwasan.h
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_rtl.h
The file was modifiedcompiler-rt/lib/hwasan/hwasan.cpp
The file was modifiedcompiler-rt/lib/memprof/memprof_stack.h
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_rtl_report.cpp
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_rtl.cpp
The file was modifiedcompiler-rt/lib/memprof/memprof_rtl.cpp
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_termination.cpp
The file was modifiedcompiler-rt/lib/asan/asan_rtl.cpp
The file was modifiedcompiler-rt/lib/asan/asan_stack.h
The file was modifiedcompiler-rt/lib/msan/msan.cpp
Commit 382c505d9cfca8adaec47aea2da7bbcbc00fc05c by martin
[COFF] Fix ARM and ARM64 REL32 relocations to be relative to the end of the relocation

This matches how they are defined on X86.

This should fix the relative lookup tables pass for COFF, allowing
it to be reenabled.

Differential Revision: https://reviews.llvm.org/D102217
The file was modifiedllvm/test/MC/AArch64/coff-relocations.s
The file was modifiedllvm/lib/MC/WinCOFFObjectWriter.cpp
The file was modifiedllvm/test/MC/ARM/coff-relocations.s
Commit 1dc838717a294ed7bfd7d597d427886ce61df122 by dvyukov
tsan: fix syscall test on aarch64

Add missing includes and use SYS_pipe2 instead of SYS_pipe
as it's not present on some arches.

Differential Revision: https://reviews.llvm.org/D102311
The file was modifiedcompiler-rt/test/tsan/Linux/syscall.h
Commit 9a0ea5994bdc477d77fd4d9f4eb5d34b1ac4184a by zinenko
[mlir] Support alignment in LLVM dialect GlobalOp

First step in adding alignment as an attribute to MLIR global definitions. Alignment can be specified for global objects in LLVM IR. It can also be specified as a named attribute in the LLVMIR dialect of MLIR. However, this attribute has no standing and is discarded during translation from MLIR to LLVM IR. This patch does two things: First, it adds the attribute to the syntax of the llvm.mlir.global operation, and by doing this it also adds accessors and verifications. The syntax is "align=XX" (with XX being an integer), placed right after the value of the operation. Second, it allows transforming this operation to and from LLVM IR. It is checked whether the value is an integer power of 2.

Reviewed By: ftynse, mehdi_amini

Differential Revision: https://reviews.llvm.org/D101492
The file was modifiedmlir/examples/toy/Ch7/mlir/LowerToLLVM.cpp
The file was modifiedmlir/lib/Conversion/StandardToLLVM/StandardToLLVM.cpp
The file was modifiedmlir/lib/Target/LLVMIR/ConvertFromLLVMIR.cpp
The file was modifiedmlir/test/Dialect/LLVMIR/invalid.mlir
The file was modifiedmlir/include/mlir/Dialect/LLVMIR/LLVMOps.td
The file was modifiedmlir/test/Target/LLVMIR/import.ll
The file was modifiedmlir/lib/Target/LLVMIR/ModuleTranslation.cpp
The file was modifiedmlir/lib/Conversion/GPUCommon/GPUOpsLowering.cpp
The file was modifiedmlir/examples/toy/Ch6/mlir/LowerToLLVM.cpp
The file was modifiedmlir/test/Target/LLVMIR/llvmir.mlir
The file was modifiedmlir/lib/Conversion/SPIRVToLLVM/SPIRVToLLVM.cpp
The file was modifiedmlir/lib/Conversion/SPIRVToLLVM/ConvertLaunchFuncToLLVMCalls.cpp
The file was modifiedmlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
The file was modifiedmlir/test/Dialect/LLVMIR/global.mlir
Commit 27b2bd76017f5b486b96ad782bfb28e1b28b5088 by zinenko
[MLIR] Enable conversion from llvm::SMLoc to mlir::Location with OpAsmParser.

DialectAsmParser already allows converting an llvm::SMLoc location to a
mlir::Location location. This commit adds the same functionality to OpAsmParser.
Implementation is copied from DialectAsmParser.

Reviewed By: rriddle

Differential Revision: https://reviews.llvm.org/D102165
The file was modifiedmlir/include/mlir/IR/OpImplementation.h
The file was modifiedmlir/lib/Parser/Parser.cpp
Commit 8aa7f28497b6794ca659f1b729a6e8ce312c54e2 by dvyukov
scudo: fix CheckFailed-related build breakage

I was running:

$ ninja check-sanitizer check-msan check-asan \
  check-tsan check-lsan check-ubsan check-cfi \
  check-profile check-memprof check-xray check-hwasan

but missed check-scudo...

Differential Revision: https://reviews.llvm.org/D102314
The file was modifiedcompiler-rt/lib/scudo/scudo_termination.cpp
Commit 6351993da72e298b3f79218e4f129a9bbde3e679 by gchatelet
[libc] Simplifies multi implementations

This is a roll forward of D101895 with two additional fixes:

Original Patch description:
> This is a follow up on D101524 which:
>
> - simplifies cpu features detection and usage,
> - flattens target dependent optimizations so it's obvious which implementations are generated,
> - provides an implementation targeting the host (march/mtune=native) for the mem* functions,
> - makes sure all implementations are unittested (provided the host can run them).

Additional fixes:
- Fix uninitialized ALL_CPU_FEATURES
- Use non pseudo microarch as it is only supported from Clang 12 on

Differential Revision: https://reviews.llvm.org/D102233
The file was modifiedlibc/src/string/CMakeLists.txt
The file was removedlibc/src/string/aarch64/CMakeLists.txt
The file was removedlibc/src/string/x86_64/CMakeLists.txt
The file was modifiedlibc/test/src/string/CMakeLists.txt
The file was modifiedlibc/cmake/modules/LLVMLibCCheckCpuFeatures.cmake
Commit 44642505ce6be476124575f1589552bd53a6fdeb by djtodoro
[NFC][llvm-dwarfdump] Avoid passing std::string by value in collectStatsForDie()
The file was modifiedllvm/tools/llvm-dwarfdump/Statistics.cpp
Commit d8e65585f7c7cddd63920d122a9e6368d91c9389 by aorlov
Fixed llvm-objcopy to add correct symbol table for ELF with program headers.

This fixes the following bugs:
https://bugs.llvm.org/show_bug.cgi?id=43935

Reviewed By: jhenderson

Differential Revision: https://reviews.llvm.org/D102258
The file was modifiedllvm/test/tools/llvm-objcopy/ELF/add-symbol-no-symtab.test
The file was modifiedllvm/tools/llvm-objcopy/ELF/Object.cpp
Commit edf9d88266376a693b07668f733034d2f6b22072 by tomas.matheson
[ARM] Precommit test for D101898

Differential Revision: https://reviews.llvm.org/D101912
The file was addedllvm/test/CodeGen/ARM/atomicrmw_exclusive_monitor_ints.ll
Commit 34c098b780a27a90b5614ea3b949b9269835f2a5 by tomas.matheson
[ARM] Prevent spilling between ldrex/strex pairs

Based on the same for AArch64: 4751cadcca45984d7671e594ce95aed8fe030bf1

At -O0, the fast register allocator may insert spills between the ldrex and
strex instructions inserted by AtomicExpandPass when expanding atomicrmw
instructions in LL/SC loops. To avoid this, expand to cmpxchg loops and
therefore expand the cmpxchg pseudos after register allocation.

Required a tweak to ARMExpandPseudo::ExpandCMP_SWAP to use the 4-byte encoding
of UXT, since the pseudo instruction can be allocated a high register (R8-R15)
which the 2-byte encoding doesn't support. However, the 4-byte encodings
are not present for ARM v8-M Baseline. To enable this, two new pseudos are
added for Thumb which are only valid for v8mbase, tCMP_SWAP_8 and
tCMP_SWAP_16.

The previously committed attempt in D101164 had to be reverted due to runtime
failures in the test suites. Rather than spending time fixing that
implementation (adding another implementation of atomic operations and more
divergence between backends) I have chosen to follow the approach taken in
D101163.

Differential Revision: https://reviews.llvm.org/D101898

Depends on D101912
The file was modifiedllvm/test/CodeGen/ARM/atomicrmw_exclusive_monitor_ints.ll
The file was modifiedllvm/lib/Target/ARM/ARMInstrThumb.td
The file was modifiedllvm/lib/Target/ARM/ARMISelLowering.cpp
The file was modifiedllvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
The file was modifiedllvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
Commit cbd93cee9bf014402a7405479ba21f6f3340a126 by qiucofan
Revert "[PowerPC] [Clang] Enable float128 feature on VSX targets"

This commit brought build break in some f128 related tests. But that's
not the root cause. There exists some differences between Clang and
GCC's definition for 128-bit float types on PPC, so macros/functions in
glibc may not work with clang -mfloat128 well. We need to handle this
carefully and reland it.
The file was modifiedclang/lib/Basic/Targets/PPC.cpp
The file was modifiedclang/test/Driver/ppc-f128-support-check.c
Commit 68137ef5682f936a5db14202a69548eee6294256 by Piotr Sobczak
[AMDGPU] Skip invariant loads when avoiding WAR conflicts

No need to handle invariant loads when avoiding WAR conflicts, as
there cannot be a vector store to the same memory location.

Reviewed By: foad

Differential Revision: https://reviews.llvm.org/D101177
The file was modifiedllvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/waitcnt-no-redundant.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/mul24-pass-ordering.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/stack-realign.ll
Commit 5af3a6645f38e5638b4ba03613ee18140f36962d by david.spickett
Remove Windows editline from LLDB

I don't mean to undo others' work but it looks like the hand-rolled EditLine for LLDB on Windows isn't used.  It'd be easier to make changes to bring the other platforms' Editline wrapper up to date (e.g. simplifying char vs wchar_t) without modifying/testing this one too.

Reviewed By: amccarth

Differential Revision: https://reviews.llvm.org/D102208
The file was modifiedlldb/include/lldb/Host/Editline.h
The file was removedlldb/source/Host/windows/EditLineWin.cpp
The file was modifiedlldb/source/Host/CMakeLists.txt
The file was removedlldb/include/lldb/Host/windows/editlinewin.h
Commit fdb055f4f139e225884109fbffa275bd3eb3d3b9 by stephen.tozer
Reapply "[DebugInfo] Fix updateDbgUsersToReg to support DBG_VALUE_LIST"

Previous crashes caused by this patch were the result of machine
subregisters being incorrectly handled in updateDbgUsersToReg; this has
been fixed by using RegUnits to determine overlapping registers, instead
of using the register values directly.

Differential Revision: https://reviews.llvm.org/D101523

This reverts commit 7ca26c5fa2df253878cab22e1e2f0d6f1b481218.
The file was modifiedllvm/lib/CodeGen/MachineCopyPropagation.cpp
The file was modifiedllvm/include/llvm/CodeGen/MachineRegisterInfo.h
The file was addedllvm/test/DebugInfo/ARM/machine-cp-updates-dbg-reg.mir
Commit b6c0edb9792c1a216961aefb63783ab4b986e823 by mgorny
[lldb] [Process/elf-core] Fix reading FPRs from FreeBSD/i386 cores

The FreeBSD coredumps from i386 systems contain only FSAVE-style
NT_FPREGSET.  Since we do not really support reading that kind of data
anymore, just use NT_X86_XSTATE to get FXSAVE-style data when available.

Differential Revision: https://reviews.llvm.org/D101086
The file was addedlldb/test/Shell/Register/Core/x86-32-freebsd-fp.test
The file was modifiedlldb/source/Plugins/Process/elf-core/RegisterUtilities.h
The file was modifiedlldb/test/Shell/Register/Core/x86-32-freebsd-addr.test
Commit 71e66da04cf15cf47045b5d1482803197a24a75d by mgorny
[Process/elf-core] Read PID from FreeBSD prpsinfo

Add a function to read NT_PRPSINFO note from FreeBSD core dumps.  This
is necessary to get the process ID (NT_PRSTATUS has only thread ID).
Move the lp64 check from NT_PRSTATUS parsing to the parseFreeBSDNotes()
to avoid repeating it.

Differential Revision: https://reviews.llvm.org/D101893
The file was modifiedlldb/source/Plugins/Process/elf-core/ProcessElfCore.cpp
Commit 6e6f9a636b1917f366821fb0a5c37cde19634c7a by peter.waller
[AArch64][SVE] Improve sve.convert.to.svbool lowering

The sve.convert.to.svbool lowering has the effect of widening a logical
<M x i1> vector representing lanes into a physical <16 x i1> vector
representing bits in a predicate register.

In general, if converting to svbool, the contents of lanes in the
physical register might not be known. For sve.convert.to.svbool the new
lanes are specified to be zeroed, requiring 'and' instructions to mask
off the new lanes. For lanes coming from a ptrue or a comparison,
however, they are known to be zero.

CodeGen Before:
  ptrue p0.s, vl16
  ptrue p1.s
  ptrue p2.b
  and   p0.b, p2/z, p0.b, p1.b
  ret

After:
  ptrue p0.s, vl16
  ret

Differential Revision: https://reviews.llvm.org/D101544
The file was modifiedllvm/test/CodeGen/AArch64/sve-intrinsics-reinterpret.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp
Commit b7a11274f90f07537e2151fa4424db257ff9a950 by david.sherwood
[LoopVectorize] Fix scalarisation crash in widenPHIInstruction for scalable vectors

In InnerLoopVectorizer::widenPHIInstruction there are cases where we have
to scalarise a pointer induction variable after vectorisation. For scalable
vectors we already deal with the case where the pointer induction variable
is uniform, but we currently crash if not uniform. For fixed width vectors
we calculate every lane of the scalarised pointer induction variable for a
given VF, however this cannot work for scalable vectors. In this case I
have added support for caching the whole vector value for each unrolled
part so that we can always extract an arbitrary element. Additionally, we
still continue to cache the known minimum number of lanes too in order
to improve code quality by avoiding an extractelement operation.

I have adapted an existing test `pointer_iv_mixed` from the file:

  Transforms/LoopVectorize/consecutive-ptr-uniforms.ll

and added it here for scalable vectors instead:

  Transforms/LoopVectorize/AArch64/sve-widen-phi.ll

Differential Revision: https://reviews.llvm.org/D101294
The file was modifiedllvm/test/Transforms/LoopVectorize/AArch64/sve-widen-phi.ll
The file was modifiedllvm/lib/Transforms/Vectorize/LoopVectorize.cpp
Commit 725bc3eb0d5cdce1952e2848c1f170c808d0acde by gbreynoo
[llvm-symbolizer] Place Mach-O options into the Mach-O option group.

In the help output of other tools and in the symbolizer command guide,
Mach-O specific options are in their own section. This change fixes the
symbolizer help output to be consistent.

Differential Revision: https://reviews.llvm.org/D102178
The file was modifiedllvm/tools/llvm-symbolizer/Opts.td
Commit 81900dc4982dc03da859a75c927e1bba95837c30 by gbreynoo
[llvm-readelf] Unhide short options to match the command guide

The readelf command guide shows the short options used as aliases but
these are not found in the help text unless --show-hidden is used, other
tools show aliases with --help. This change fixes the help output to be
consistent with the command guide.

Differential Revision: https://reviews.llvm.org/D102173
The file was modifiedllvm/tools/llvm-readobj/llvm-readobj.cpp
Commit 72e242a286be1c821c521fdc8a778517b193a59e by llvm-dev
[X86][AVX] canonicalizeShuffleMaskWithHorizOp - improve support for 256/512-bit vectors

Extend the HOP(HOP(X,Y),HOP(Z,W)) and SHUFFLE(HOP(X,Y),HOP(Z,W)) folds to handle repeating 256/512-bit vector cases.

This allows us to drop the UNPACK(HOP(),HOP()) custom fold in combineTargetShuffle.

This required isRepeatedTargetShuffleMask to be tweaked to support target shuffle masks taking more than 2 inputs.
The file was modifiedllvm/test/CodeGen/X86/horizontal-shuffle.ll
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
Commit 96100f15082679b2c75c7744b8eb4fc87fcf71f5 by kbessonova
[libcxx] NFC. Correct wordings of _LIBCPP_ASSERT debug messages

Differential Revision: https://reviews.llvm.org/D102195
The file was modifiedlibcxx/include/__hash_table
The file was modifiedlibcxx/include/iterator
The file was modifiedlibcxx/include/optional
The file was modifiedlibcxx/include/vector
The file was modifiedlibcxx/include/list
The file was modifiedlibcxx/include/deque
Commit 0fb364a97e74abd3d3700b8f18bbfed787fbfdbb by gysit
[mlir][linalg] Remove IndexedGenericOp support from LinalgToStandard...

after introducing the IndexedGenericOp to GenericOp canonicalization (https://reviews.llvm.org/D101612).

Differential Revision: https://reviews.llvm.org/D102236
The file was modifiedmlir/include/mlir/Conversion/LinalgToStandard/LinalgToStandard.h
The file was modifiedmlir/lib/Conversion/LinalgToStandard/LinalgToStandard.cpp
The file was modifiedmlir/test/Dialect/Linalg/standard.mlir
Commit 163325086c35b3984c5e6f7a2adb6022003fcd84 by n.james93
[clang-tidy] Enable the use of IgnoreArray flag in pro-type-member-init rule

The `IgnoreArray` flag was not used before while running the rule. Fixes [[ https://bugs.llvm.org/show_bug.cgi?id=47288 | b/47288 ]]

Reviewed By: njames93

Differential Revision: https://reviews.llvm.org/D101239
The file was addedclang-tools-extra/test/clang-tidy/checkers/cppcoreguidelines-pro-type-member-init.ignorearrays.cpp
The file was modifiedclang-tools-extra/clang-tidy/cppcoreguidelines/ProTypeMemberInitCheck.cpp
Commit 7d0a81ca38e427de9b7fb0961ec643b757028131 by david.spickett
Revert "[scudo] Enable arm32 arch"

This reverts commit b1a77e465e37fc400c16f9fda2a637f11c698bb9.

Which has a failing test on our armv7 bots:
https://lab.llvm.org/buildbot/#/builders/59/builds/1812
The file was modifiedcompiler-rt/cmake/config-ix.cmake
Commit c6b96ae06f70bd0ecd28995ffc45d87edd89a84d by gysit
[mlir][linalg] Remove IndexedGenericOp support from LinalgBufferize...

after introducing the IndexedGenericOp to GenericOp canonicalization (https://reviews.llvm.org/D101612).

Differential Revision: https://reviews.llvm.org/D102308
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/Bufferize.cpp
The file was modifiedmlir/test/Dialect/Linalg/bufferize.mlir
Commit 4c59ab34f7bda74296e42ef7ea8d83828cb45558 by n.james93
[clang-tidy][NFC] Simplify a lot of bugprone-sizeof-expression matchers

There should be a follow up to this for changing the traversal mode, but some of the tests don't like that.

Reviewed By: steveire

Differential Revision: https://reviews.llvm.org/D101614
The file was modifiedclang-tools-extra/clang-tidy/bugprone/SizeofExpressionCheck.cpp
Commit 24d06fff55510780eba1a267d844ee26a17d6888 by spatel
[x86] add test for pcmpeq with 0; NFC
The file was modifiedllvm/test/CodeGen/X86/setcc-lowering.ll
Commit f58e0513dd95944b81ce7a6e7b49ba656de7d75f by spatel
[x86] try harder to lower to PCMPGT instead of not-of-PCMPEQ

This is motivated by the example in https://llvm.org/PR50055 ,
but it doesn't do anything for that bug currently because we
don't actually have a zero-extended setcc there.

Proof for the generic transform (inverse of what we would
try to do in combining):
https://alive2.llvm.org/ce/z/aBL-Mg

Differential Revision: https://reviews.llvm.org/D102275
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was modifiedllvm/test/CodeGen/X86/setcc-lowering.ll
The file was modifiedllvm/test/CodeGen/X86/vsel-cmp-load.ll
The file was modifiedllvm/test/CodeGen/X86/vec_umulo.ll
Commit a4db7025a9762c568c7bc9fdd3c64f4a60e31cfc by Piotr Sobczak
[AMDGPU] Remove assert

Remove assert introduced in D101177, following post-commit feedback.
The file was modifiedllvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
Commit 06bb9cf30d11247540d5b3f2a714f3aa640353e6 by gysit
[mlir][linalg] Remove IndexedGenericOp support from LinalgInterchangePattern...

after introducing the IndexedGenericOp to GenericOp canonicalization (https://reviews.llvm.org/D101612).

Differential Revision: https://reviews.llvm.org/D102245
The file was modifiedmlir/test/lib/Transforms/TestLinalgTransforms.cpp
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/Transforms.cpp
The file was modifiedmlir/include/mlir/Dialect/Linalg/Transforms/Transforms.h
The file was modifiedmlir/test/Dialect/Linalg/transform-patterns.mlir
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/Interchange.cpp
Commit a383d325f6c6c8d9bb52d1da221d9a144dfc475c by jay.foad
[TargetRegisterInfo] Speed up getAllocatableSet. NFCI.

MachineRegisterInfo caches the reserved register set that is computed by
by TargetRegisterInfo::getReservedRegs, so call into MRI to get the
reserved regs to avoid recomputing them.

In particular this speeds up AMDGPU's SIFormMemoryClauses pass because
AMDGPU has a particularly complicated reserved set that is expensive to
compute.

Differential Revision: https://reviews.llvm.org/D102318
The file was modifiedllvm/lib/CodeGen/TargetRegisterInfo.cpp
Commit 554b1bced325a8d860ad00bd59020d66d01c95f8 by lebedev.ri
[InstCombine] ~(C + X) --> ~C - X (PR50308)

We can not rely on (C+X)-->(X+C) already happening,
because we might not have visited that `add` yet.
The added testcase would get stuck in an endless combine loop.
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
The file was modifiedllvm/test/Transforms/InstCombine/not-add.ll
Commit 46adccc5cc1095f57b65fb2a17a4a023ccc77eb9 by jay.foad
[AMDGPU] Improve Codegen for build_vector

Improve the code generation of build_vector.
Use the v_pack_b32_f16 instruction instead of
v_and_b32 + v_lshl_or_b32

Differential Revision: https://reviews.llvm.org/D98081

Patch by Julien Pagès!
The file was modifiedllvm/test/CodeGen/AMDGPU/fpow.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.log10.f16.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructions.td
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.rint.f16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/fcanonicalize.f16.ll
The file was addedllvm/test/CodeGen/AMDGPU/v_pack.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/frem.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/fcanonicalize-elimination.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.sin.f16.ll
The file was modifiedllvm/lib/Target/AMDGPU/SIInstructions.td
The file was modifiedllvm/test/CodeGen/AMDGPU/fptrunc.f16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.round.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.log.f16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/fexp.ll
The file was modifiedllvm/lib/Target/AMDGPU/SIISelLowering.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/mad-mix-lo.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.cos.f16.ll
Commit 5a439015393e616b2faed9a9fbb1d7036b28e786 by gkm
[llvm-objdump] Exclude __mh_*_header symbols during MachO disassembly

`__mh_(execute|dylib|dylinker|bundle|preload|object)_header` are special symbols whose values hold the VMA of the Mach header to support introspection. They are attached to the first section in `__TEXT`, even though their addresses are outside `__TEXT`, and they do not refer to code.

It is normally harmless, but when the first section of `__TEXT` has no other symbols, `__mh_*_header` is considered by the disassembler when determing function boundaries. Since `__mh_*_header` refers to an address outside `__TEXT`, the boundary determination fails and disassembly quits.

Since `__TEXT,__text` normally has symbols, this bug is obscured. Experiments placing `__stubs` and `__stub_helper` first exposed the bug, since neither has symbols.

Differential Revision: https://reviews.llvm.org/D101786
The file was addedllvm/test/tools/llvm-objdump/MachO/no-text-symbols-disassembly.test
The file was modifiedllvm/tools/llvm-objdump/llvm-objdump.cpp
Commit 4b98199ce8fb94d0de46e04b4d7b3a699691d2e1 by martin
[Passes] Reenable the relative lookup table converter pass for ELF and COFF on aarch64

The bug (PR50227, affecting COFF) that caused the revert in
6f5670a4c3d8c079d4b676140ee69e5cc235d5a8 has been fixed in
382c505d9cfca8adaec47aea2da7bbcbc00fc05c now, so it should be safe
to reenable the pass for that target (and ELF).

In PR50227 it's also mentioned that the same pass seems to cause
problems on aarch64 on darwin, so leaving it disabled there for now.
The file was modifiedllvm/include/llvm/CodeGen/BasicTTIImpl.h
Commit 61630814b1d0415953fd4d1a58427836487f356c by david.sherwood
[NFC] Use variable GEP index in vec_demanded_elts tests

I've changed a test in each of these files:

  Transforms/InstCombine/vec_demanded_elts.ll
  Transforms/InstCombine/vec_demanded_elts-inseltpoison.ll

to use a variable GEP index instead of a constant value so that
we're testing the more general case.
The file was modifiedllvm/test/Transforms/InstCombine/vec_demanded_elts-inseltpoison.ll
The file was modifiedllvm/test/Transforms/InstCombine/vec_demanded_elts.ll
Commit 892c56eabe250acaeb761eaddf783f47d95f7f4d by powerman1st
[clang][AVR] Redefine some types to be compatible with avr-gcc

Reviewed By: dylanmckay

Differential Revision: https://reviews.llvm.org/D100701
The file was modifiedclang/test/Preprocessor/init.c
The file was modifiedclang/lib/Basic/Targets/AVR.cpp
The file was modifiedclang/test/CodeGen/builtins.cpp
Commit 3fa6510f6ea0101c70592487074957bb1cde576c by peter.waller
[CodeGen][AArch64][SVE] Fold [rdffr, ptest] => rdffrs; bugfix for optimizePTestInstr

When a ptest is used to set flags from the output of rdffr, the ptest
can be eliminated, using a flags-setting rdffrs instead.

Additionally, check that nothing consumes flags between rdffr and ptest;
this case appears to have been missed previously.

* There is no unpredicated RDFFRS instruction.
* If substituting RDFFR_PP, require that the mask argument of the
  PTEST matches that of the RDFFR_PP.
* Move some precondition code up inside optimizePTestInstr, so that it
  covers the new code paths for RDFFR which return earlier.
  * Only consider RDFFR, PTEST in same basic block.
  * Check for other flag setting instructions between the two, abort if
    found.
  * Drop an old TODO comment about removing dead PTEST instructions.

RDFFR_P to follow in later patch.

Differential Revision: https://reviews.llvm.org/D101357
The file was addedllvm/test/CodeGen/AArch64/sve-ptest-removal-rdffr.mir
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrInfo.cpp
Commit 4b00ffa767fc8a71c2eaf544cb6397f6db34eb6a by hgreving
[DAGCombiner] Add test exposing bug in DAG combine.

Adds a test in X86, exposing a bug in DAG combine eliminating stores that
are the same value but no the same address space.

Differential Revision: https://reviews.llvm.org/D102243
The file was addedllvm/test/CodeGen/X86/dagcombine-dead-store.ll
Commit 762ac725bf9775536dda5b3dda13574f14a8c2b9 by hgreving
[DAGCombiner] Fix DAG combine store elimination, different address space.

Fixes a bug in the DAG combiner that eliminates the stores because it missed
to inspect the address space of the pointers.

%v = load %ptr_as1
// no chain side effect
store %v, %ptr_as2

As well as

store %v, %ptr_as1
store %v, %ptr_as2

Fixes a test for above in X86.

Differential Revision: https://reviews.llvm.org/D102096
The file was modifiedllvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
The file was modifiedllvm/test/CodeGen/X86/dagcombine-dead-store.ll
Commit 8d37411e48202b490c62ee3548df4b90f5974e12 by stefanp
Revert "[SelectionDAG][Mips][PowerPC][RISCV][WebAssembly] Teach computeKnownBits/ComputeNumSignBits about atomics"

This reverts commit 6c80361b8474535852afb2f7201370fb5f410091.
Breaks PowerPC Big Endian buildbots.
The file was modifiedllvm/test/CodeGen/PowerPC/atomics-i32-ldst.ll
The file was modifiedllvm/test/CodeGen/PowerPC/atomics-i64-ldst.ll
The file was modifiedllvm/test/CodeGen/RISCV/atomic-signext.ll
The file was modifiedllvm/test/CodeGen/PowerPC/atomics-i16-ldst.ll
The file was modifiedllvm/test/CodeGen/Mips/atomic.ll
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
The file was modifiedllvm/test/CodeGen/PowerPC/atomics-i8-ldst.ll
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyInstrAtomics.td
Commit 44e0e91db01abb9de1868f5acf3ff4f2648b8fc0 by craig.topper
[ValueTypes] Rename MVT::getVectorNumElements() to MVT::getVectorMinNumElements(). Fix some misuses of getVectorNumElements()

getVectorNumElements() returns a value for scalable vectors
without any warning so it is effectively getVectorMinNumElements().
By renaming it and making getVectorNumElements() forward to
it, we can insert a check for scalable vectors into getVectorNumElements()
similar to EVT. I didn't do that in this patch because there are still more
fixes needed, but I was able to temporarily do it and passed the RISCV
lit tests with these changes.

The changes to isPow2VectorType and getPow2VectorType are copied from EVT.

The change to TypeInfer::EnforceSameNumElts reduces the size of AArch64's isel table.
We're now considering SameNumElts to require the scalable property to match which
removes some unneeded type checks.

This was motivated by the bug I fixed yesterday in 80b9510806cf11c57f2dd87191d3989fc45defa8

Reviewed By: frasercrmck, sdesmalen

Differential Revision: https://reviews.llvm.org/D102262
The file was modifiedllvm/lib/Target/PowerPC/PPCISelLowering.h
The file was modifiedllvm/lib/Target/Hexagon/HexagonISelLowering.cpp
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was modifiedllvm/utils/TableGen/IntrinsicEmitter.cpp
The file was modifiedllvm/lib/Target/AMDGPU/SIISelLowering.cpp
The file was modifiedllvm/utils/TableGen/CodeGenDAGPatterns.cpp
The file was modifiedllvm/include/llvm/Support/MachineValueType.h
The file was modifiedllvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
Commit 98575708da9544ccab8939fece9c3d638a32f09f by Yaxun.Liu
[CUDA][HIP] Fix device template variables

Currently clang does not emit device template variables
instantiated only in host functions, however, nvcc is
able to do that:

https://godbolt.org/z/fneEfferY

This patch fixes this issue by refactoring and extending
the existing mechanism for emitting static device
var ODR-used by host only. Basically clang records
device variables ODR-used by host code and force
them to be emitted in device compilation. The existing
mechanism makes sure these device variables ODR-used
by host code are added to llvm.compiler-used, therefore
they are guaranteed not to be deleted.

It also fixes non-ODR-use of static device variable by host code
causing static device variable to be emitted and registered,
which should not.

Reviewed by: Artem Belevich

Differential Revision: https://reviews.llvm.org/D102237
The file was modifiedclang/test/CodeGenCUDA/static-device-var-rdc.cu
The file was modifiedclang/lib/CodeGen/CGCUDANV.cpp
The file was modifiedclang/lib/Sema/SemaExpr.cpp
The file was modifiedclang/test/CodeGenCUDA/device-stub.cu
The file was modifiedclang/test/CodeGenCUDA/host-used-device-var.cu
The file was modifiedclang/include/clang/AST/ASTContext.h
The file was modifiedclang/lib/CodeGen/CodeGenModule.cpp
The file was modifiedclang/test/CodeGenCUDA/static-device-var-no-rdc.cu
The file was modifiedclang/lib/AST/ASTContext.cpp
Commit 1336c5ae2fea48bcb54a5050a01b59333fd502aa by rupprecht
[llvm-cov][test] Add test coverage for "gcov" implying "llvm-cov gcov" compatibility.

Much like other LLVM binary utilities, `llvm-cov` has a symlink compatibility feature where it runs in `gcov` compatibility mode if the binary name ends in `gcov`. This is identical to invoking `llvm-cov gcov ...`.

Differential Revision: https://reviews.llvm.org/D102299
The file was addedllvm/test/tools/llvm-cov/tool-name.test
Commit 58d18dde5cca3417e3d52670775c95d2f6fe9d05 by anastasia.stulova
[OpenCL] Remove pragma requirement from Arm dot extension.

This removed the pointless need for extension pragma since
it doesn't disable anything properly and it doesn't need to
enable anything that is not possible to disable.

The change doesn't break existing kernels since it allows to
compile more cases i.e. without pragma statements but the
pragma continues to be accepted.

Differential Revision: https://reviews.llvm.org/D100985
The file was modifiedclang/test/SemaOpenCL/arm-integer-dot-product.cl
The file was modifiedclang/test/CodeGenOpenCL/arm-integer-dot-product.cl
The file was modifiedclang/lib/Headers/opencl-c.h
Commit 6110b667b0537104ee139a5c6efc726f902db4de by clementval
[mlir][openacc] Conversion of data operand to LLVM IR dialect

Add a conversion pass to convert higher-level type before translation.
This conversion extract meangingful information and pack it into a struct that
the translation (D101504) will be able to understand.

Reviewed By: ftynse

Differential Revision: https://reviews.llvm.org/D102170
The file was modifiedmlir/include/mlir/Dialect/OpenACC/OpenACCOps.td
The file was modifiedmlir/lib/Dialect/OpenACC/IR/OpenACC.cpp
The file was modifiedmlir/lib/Conversion/CMakeLists.txt
The file was modifiedmlir/include/mlir/Conversion/Passes.h
The file was addedmlir/lib/Conversion/OpenACCToLLVM/CMakeLists.txt
The file was addedmlir/include/mlir/Conversion/OpenACCToLLVM/ConvertOpenACCToLLVM.h
The file was addedmlir/lib/Conversion/OpenACCToLLVM/OpenACCToLLVM.cpp
The file was modifiedmlir/include/mlir/Conversion/Passes.td
The file was addedmlir/test/Conversion/OpenACCToLLVM/convert-standalone-data-to-llvmir.mlir
Commit c5ec00e62b0e7b91eb07e25441c7ed38227f5bf3 by fraser
[TargetLowering] Improve legalization of scalable vector types

This patch extends the vector type-conversion and legalization capabilities of
scalable vector types.

Firstly, `vscale x 1` types now behave more like the corresponding `vscale x
2+` types. This enables the integer promotion legalization of extended scalable
types, such as the promotion of `<vscale x 1 x i5>` to `<vscale x 1 x i8>`.

These `vscale x 1` types are also now better handled by
`getVectorTypeBreakdown`, where what looks like older handling for 1-element
fixed-length vector types was spuriously updated to include scalable types.

Widening of scalable types is now better supported, by using `INSERT_SUBVECTOR`
to insert the smaller scalable vector "value" type into the wider scalable
vector "part" type. This allows AArch64 to pass and return `vscale x 1` types
by value by widening.

There are still cases where we are unable to legalize `vscale x 1` types, such
as where expansion would require splitting the vector in two.

Reviewed By: sdesmalen

Differential Revision: https://reviews.llvm.org/D102073
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
The file was addedllvm/test/CodeGen/AArch64/sve-widen-scalable-vectortype.ll
The file was addedllvm/test/CodeGen/RISCV/rvv/legalize-scalable-vectortype.ll
The file was modifiedllvm/lib/CodeGen/TargetLoweringBase.cpp
Commit 778562ada39f5353b735c4ac204eddedb072a94b by llvm-dev
[X86][AVX] Add v4i64 shift-by-32 tests

AVX1 could perform this as a v8f32 shuffle instead of splitting - based off PR46621
The file was modifiedllvm/test/CodeGen/X86/vector-shift-lshr-256.ll
The file was modifiedllvm/test/CodeGen/X86/vector-shift-shl-256.ll
The file was modifiedllvm/test/CodeGen/X86/vector-shift-ashr-256.ll
Commit 7bff9bdd34d53a660f80eb1cdc9da885fd2702e1 by llvm-dev
[X86][AVX] combineConcatVectorOps - add ConcatSubOperand helper. NFCI.

Pull out repeated code to create a concat_vectors of the same operand from all subvecs.
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
Commit 47a11a97d0c28e6b1235907780c998f141497e0a by paul.robinson
Fix grammar in README.md
The file was modifiedREADME.md
Commit 5885f1a4cb0bec91ea106e4f300c860c8d061d56 by baptiste.saleil
[AMDGPU] Disable the SIFormMemoryClauses pass at -O1

This patch disables the SIFormMemoryClauses pass at -O1. This pass has a
significant impact on compilation time, so we only want it to be enabled
starting from -O2.

Differential Revision: https://reviews.llvm.org/D101939
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/llc-pipeline.ll
Commit cf4610d27bbb5c3a744374440e2fdf77caa12040 by wei.huang
[PowerPC] Fix definitions of CMPRB8, CMPEQB, CMPRB, SETB in PPCInstr64Bit.td and PPCInstrInfo.td
The file was modifiedllvm/lib/Target/PowerPC/PPCInstr64Bit.td
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrInfo.td
Commit 33f908c42881fa02963f0c64f8be5088717664cc by fabian
[MLIR] Factor pass timing out into a dedicated timing manager

This factors out the pass timing code into a separate `TimingManager`
that can be plugged into the `PassManager` from the outside. Users are
able to provide their own implementation of this manager, and use it to
time additional code paths outside of the pass manager. Also allows for
multiple `PassManager`s to run and contribute to a single timing report.

More specifically, moves most of the existing infrastructure in
`Pass/PassTiming.cpp` into a new `Support/Timing.cpp` file and adds a
public interface in `Support/Timing.h`. The `PassTiming` instrumentation
becomes a wrapper around the new timing infrastructure which adapts the
instrumentation callbacks to the new timers.

Reviewed By: rriddle, lattner

Differential Revision: https://reviews.llvm.org/D100647
The file was modifiedmlir/lib/Pass/PassManagerOptions.cpp
The file was modifiedmlir/lib/Pass/PassTiming.cpp
The file was modifiedmlir/include/mlir/Pass/PassManager.h
The file was addedmlir/lib/Support/Timing.cpp
The file was modifiedmlir/lib/Pass/Pass.cpp
The file was modifiedmlir/test/Pass/pass-timing.mlir
The file was modifiedmlir/docs/PassManagement.md
The file was modifiedmlir/test/Pass/pipeline-parsing.mlir
The file was modifiedmlir/lib/Support/MlirOptMain.cpp
The file was addedmlir/include/mlir/Support/Timing.h
The file was modifiedmlir/include/mlir/Pass/Pass.h
The file was modifiedmlir/lib/Support/CMakeLists.txt
Commit 5389a05836e74e3acab6dbda7e80ea43e3bc6304 by malcolm.parsons
[docs] Fix documentation for bugprone-dangling-handle

string_view isn't experimental anymore.
This check has always handled both forms.

Reviewed By: aaron.ballman

Differential Revision: https://reviews.llvm.org/D102313
The file was modifiedclang-tools-extra/docs/clang-tidy/checks/bugprone-dangling-handle.rst
Commit cbed6e5b2ff026e4d64de8f6ee19bc902b6e0e23 by Abhina.Sreeskantharajan
[SystemZ][z/OS] Fix warning caused by umask returning a signed integer type

On z/OS, umask() returns an int because mode_t is type int, however it is being compared to an unsigned int. This patch fixes the following warning we see when compiling Path.cpp.

```
comparison of integers of different signs: 'const int' and 'const unsigned int'
```

Reviewed By: muiez

Differential Revision: https://reviews.llvm.org/D102326
The file was modifiedllvm/unittests/Support/Path.cpp
Commit 9934571eab9c6b3be22c4c8857bd3f4280b77843 by jonathanchesterfield
[libomptarget][amdgpu][nfc] Expand errorcheck macros

[libomptarget][amdgpu][nfc] Expand errorcheck macros

These macros expand to continue, which is confusing, or exit,
which is incompatible with continuing execution on offloading fail.

Expanding the macros in place makes the code look untidy but the
control flow obvious and amenable to improving. In particular, exit
becomes easier to eliminate.

Reviewed By: pdhaliwal

Differential Revision: https://reviews.llvm.org/D102230
The file was modifiedopenmp/libomptarget/plugins/amdgpu/impl/data.cpp
The file was modifiedopenmp/libomptarget/plugins/amdgpu/impl/system.cpp
The file was modifiedopenmp/libomptarget/plugins/amdgpu/impl/internal.h
The file was modifiedopenmp/libomptarget/plugins/amdgpu/src/rtl.cpp
Commit 93c8559baf551a7a30ab17654569ac5ac92986f4 by gkm
[lld-macho] Implement branch-range-extension thunks

Extend the range of calls beyond an architecture's limited branch range by first calling a thunk, which loads the far address into a scratch register (x16 on ARM64) and branches through it.

Other ports (COFF, ELF) use multiple passes with successively-refined guesses regarding the expansion of text-space imposed by thunk-space overhead. This MachO algorithm places thunks during MergedOutputSection::finalize() in a single pass using exact thunk-space overheads. Thunks are kept in a separate vector to avoid the overhead of inserting into the `inputs` vector of `MergedOutputSection`.

FIXME:
* arm64-stubs.s test is broken
* add thunk tests
* Handle thunks to DylibSymbol in MergedOutputSection::finalize()

Differential Revision: https://reviews.llvm.org/D100818
The file was modifiedlld/MachO/MergedOutputSection.cpp
The file was modifiedlld/MachO/Arch/ARM64.cpp
The file was modifiedlld/MachO/Symbols.h
The file was modifiedlld/MachO/Symbols.cpp
The file was modifiedlld/MachO/MergedOutputSection.h
The file was modifiedlld/MachO/Target.h
The file was modifiedlld/MachO/Options.td
The file was modifiedlld/MachO/InputSection.cpp
The file was modifiedlld/MachO/Writer.cpp
The file was addedlld/test/MachO/tools/generate-thunkable-program.py
The file was modifiedlld/MachO/Driver.cpp
The file was modifiedlld/MachO/SyntheticSections.h
The file was modifiedlld/MachO/SyntheticSections.cpp
The file was addedlld/test/MachO/arm64-thunks.s
The file was modifiedlld/MachO/InputSection.h
Commit dc8d16c03f4fcdc0dbfc2925621f6d0064bca31c by Amara Emerson
[AArch64][GlobalISel] Add MMOs to constant pool loads to allow LICM hoisting.

This caused performance regressions vs SDAG on SingleSource/Benchmarks/Adobe-C++
The file was addedllvm/test/CodeGen/AArch64/GlobalISel/select-const-pool.mir
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
Commit ca5d0a7310bfb21730ac6dd735e06502e7e45099 by ajcbik
[mlir][sparse] keep runtime support library signature consistent

Reviewed By: bixia

Differential Revision: https://reviews.llvm.org/D102285
The file was modifiedmlir/lib/Dialect/SparseTensor/Transforms/CMakeLists.txt
The file was modifiedmlir/lib/Dialect/SparseTensor/Transforms/SparseTensorConversion.cpp
The file was modifiedmlir/test/Dialect/SparseTensor/conversion.mlir
The file was modifiedmlir/lib/Dialect/SparseTensor/Transforms/SparseTensorPasses.cpp
Commit fb1d61b7257ccd5ba0c96bcea78d6516384ce5b6 by llvm-dev
[X86][AVX] Fold concat(ps*lq(x,32),ps*lq(y,32)) -> shuffle(concat(x,y),zero) (PR46621)

On AVX1 targets we can handle v4i64 logical shifts by 32 bits as a pair of v8f32 shuffles with zero.

I was hoping to put this in LowerScalarImmediateShift, but performing that early causes regressions where other instructions were respliting the subvectors.
The file was modifiedllvm/test/CodeGen/X86/vector-shift-lshr-256.ll
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was modifiedllvm/test/CodeGen/X86/vector-shift-shl-256.ll
The file was modifiedllvm/test/CodeGen/X86/vec_int_to_fp.ll
Commit 5480ea6c84633b7a5548cfe48fc09c6b57cecfb9 by hanchung
Update static bound checker for Linalg to cover decreasing cases

The current static checker for linalg does not work on the decreasing
index cases well. So, this is to Update the current static bound checker
for linalg to cover decreasing index cases.

Reviewed By: hanchung

Differential Revision: https://reviews.llvm.org/D102302
The file was modifiedmlir/lib/Dialect/Linalg/IR/LinalgInterfaces.cpp
The file was modifiedmlir/test/Dialect/Linalg/invalid.mlir
Commit 3bf1acab5b454ad7fb2074b34663108b53620695 by i
[CMake][ELF] Add -fno-semantic-interposition and -Bsymbolic-functions

llvm-dev message: https://lists.llvm.org/pipermail/llvm-dev/2021-May/150465.html

In an ELF shared object, a default visibility defined symbol is preemptible by default.
This creates some missed optimization opportunities. -fno-semantic-interposition can optimize -fPIC:

* in Clang: avoid GOT/PLT cost for variable access/function calls to external linkage definition in the same TU
* in GCC: enable interprocedural optimizations (including inlining) and avoid PLT

See https://gist.github.com/MaskRay/2d4dfcfc897341163f734afb59f689c6 for more information.

-Bsymbolic-functions is more aggressive than -fvisibility-inlines-hidden (present since 2012) as it applies
to all function definitions.  It can

* avoid PLT for cross-TU function calls && reduce dynamic symbol lookup
* reduce dynamic symbol lookup for taking function addresses and optimize out GOT/TOC on x86-64/ppc64

With both options, the libLLVM.so and libclang-cpp.so performance should
be closer to PIE binary linking against `libLLVM*.a` and `libclang*.a`

(In a -DLLVM_TARGETS_TO_BUILD=X86 build, the number of JUMP_SLOT decreases from 12716 to 1628, and the number of GLOB_DAT decreases from 1918 to 1313
The built clang with `-DLLVM_LINK_LLVM_DYLIB=on -DCLANG_LINK_CLANG_DYLIB=on` is significantly faster.
See the Linux kernel build result https://bugs.archlinux.org/task/70697
)

Some implication:

Interposing a subset of functions is no longer supported.
(This is fragile anyway and cannot really be supported. For Mach-O we don't use
`ld -interpose`, so interposition is not supported on Mach-O at all.)

Compiling a program which takes the address of any LLVM function with
`{gcc,clang} -fno-pic` and expects the address to equal to the address taken
from libLLVM.so or libclang-cpp.so is unsupported. I am fairly confident that
llvm-project shouldn't have different behaviors depending on such pointer
equality (as we've been using -fvisibility-inlines-hidden which applies to
inline functions for a long time), but if we accidentally do, users should be
aware that they should not make assumption on pointer equality in `-fno-pic`
mode.

Reviewed By: phosek

Differential Revision: https://reviews.llvm.org/D102090
The file was modifiedllvm/tools/llvm-shlib/CMakeLists.txt
The file was modifiedllvm/cmake/modules/HandleLLVMOptions.cmake
The file was modifiedclang/tools/clang-shlib/CMakeLists.txt
Commit 0fe6649bc5b1824e87e418b2b18f61c1ed1025ce by i
[X86] Fix -Wunused-lambda-capture
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
Commit 2d84195d60b0cb5ea43b18ab8f6770a84bf32da4 by lebedev.ri
[NFCI][clang][Codegen] CodeGenVTables::addVTableComponent(): use getGlobalDecl

It does the same thing.
Split off from https://reviews.llvm.org/D100388
The file was modifiedclang/lib/CodeGen/CGVTables.cpp
Commit 81f56a2eb3797eb5be61d65a8f7d7e19456e67d1 by lebedev.ri
[NFC][clang][Codegen] Split ThunkInfo into it's own header

Otherwise we'll have issues with forward definition of GlobalDecl.

Split off from https://reviews.llvm.org/D100388
The file was modifiedclang/lib/AST/ItaniumMangle.cpp
The file was modifiedclang/include/clang/Basic/ABI.h
The file was addedclang/include/clang/Basic/Thunk.h
The file was modifiedclang/include/clang/AST/VTableBuilder.h
Commit 113b807017847f7d9e79db724f09968b51459cf0 by clementval
[mlir][openacc] Add OpenACC translation to LLVM IR (enter_data op create/copyin)

This patch begins to translate acc.enter_data operation to call to tgt runtime call.
It currently only translate create/copyin operands of memref type. This acts as a basis to add support
for FIR types in the Flang/OpenACC support. It follows more or less a similar path than clang
with `omp target enter data map` directives.
This patch is taking a different approach than D100678 and perform a translation to LLVM IR
and make use of the OpenMPIRBuilder instead of doing a conversion to the LLVMIR dialect.

OpenACC support in Flang will rely on the current OpenMP runtime where 1:1 lowering can be
applied. Some extension will be added where features are not available yet.

Big part of this code will be shared for other standalone data operations in the OpenACC
dialect such as acc.exit_data and acc.update.

It is likely that parts of the lowering can also be shared later with the ops for
standalone data directives in the OpenMP dialect when they are introduced.

This is an initial translation and it probably needs more work.

Reviewed By: ftynse

Differential Revision: https://reviews.llvm.org/D101504
The file was addedmlir/include/mlir/Target/LLVMIR/Dialect/OpenACC/OpenACCToLLVMIRTranslation.h
The file was addedmlir/lib/Target/LLVMIR/Dialect/OpenACC/OpenACCToLLVMIRTranslation.cpp
The file was modifiedmlir/lib/Target/LLVMIR/CMakeLists.txt
The file was addedmlir/lib/Target/LLVMIR/Dialect/OpenACC/CMakeLists.txt
The file was modifiedmlir/include/mlir/Target/LLVMIR/Dialect/All.h
The file was modifiedmlir/lib/Target/LLVMIR/Dialect/CMakeLists.txt
The file was addedmlir/test/Target/LLVMIR/openacc-llvm.mlir
Commit 1470b8587f6fdc357163c2258747b77ae9ad6d7a by benny.kra
Remove AST inclusion from Basic include

That's a cyclic dependency. NFC.
The file was modifiedclang/include/clang/Basic/Thunk.h
Commit 7b57517507929a5d23fde4776aeb792ee0e9c293 by rob.suderman
[mlir][linalg] Fixed issue generating reassociation map with Rank-0 types

Rank-0 case causes a graph during linalg reshape operation.

Differential Revision: https://reviews.llvm.org/D102282
The file was modifiedmlir/lib/Dialect/Linalg/IR/LinalgOps.cpp
The file was modifiedmlir/test/Dialect/Linalg/canonicalize.mlir
Commit 56f7e5a822b43578e086c40d063af2a2c0d214ee by smeenai
[cmake] Add support for multiple distributions

LLVM's build system contains support for configuring a distribution, but
it can often be useful to be able to configure multiple distributions
(e.g. if you want separate distributions for the tools and the
libraries). Add this support to the build system, along with
documentation and usage examples.

Reviewed By: phosek

Differential Revision: https://reviews.llvm.org/D89177
The file was modifiedllvm/cmake/modules/LLVMDistributionSupport.cmake
The file was modifiedclang/cmake/modules/AddClang.cmake
The file was modifiedlld/cmake/modules/LLDConfig.cmake.in
The file was modifiedllvm/cmake/modules/AddLLVM.cmake
The file was modifiedclang/cmake/modules/ClangConfig.cmake.in
The file was modifiedflang/cmake/modules/FlangConfig.cmake.in
The file was modifiedlld/cmake/modules/CMakeLists.txt
The file was addedclang/cmake/caches/MultiDistributionExample.cmake
The file was modifiedlld/cmake/modules/AddLLD.cmake
The file was modifiedllvm/cmake/modules/CMakeLists.txt
The file was modifiedmlir/cmake/modules/AddMLIR.cmake
The file was modifiedllvm/docs/BuildingADistribution.rst
The file was modifiedflang/cmake/modules/AddFlang.cmake
The file was modifiedflang/cmake/modules/CMakeLists.txt
The file was modifiedllvm/cmake/modules/LLVMConfig.cmake.in
The file was modifiedmlir/cmake/modules/CMakeLists.txt
The file was modifiedclang/cmake/modules/CMakeLists.txt
The file was modifiedllvm/docs/ReleaseNotes.rst
The file was modifiedmlir/cmake/modules/MLIRConfig.cmake.in
Commit 1124ad2f5d47aa468a0d00b6d82853a6d4eda8d1 by stelios.ioannou
[LoopFlatten] Simplify loops so that the pass can operate on unsimplified loops.

The loop flattening pass requires loops to be in simplified form. If the
loops are not in simplified form, the pass cannot operate. This patch
simplifies all loops before flattening. As a result, all loops will be
simplified regardless of whether anything ends up being flattened.

This change was inspired by observing a certain loop that was not flatten
because the loops were not in simplified form. This loop is added as a
test to verify that it is now flattened.

Differential Revision: https://reviews.llvm.org/D102249

Change-Id: I45bcabe70fb99b0d89f0effafc82eb9e0585ec30
The file was addedllvm/test/Transforms/LoopFlatten/loop-flatten-simplify-cfg.ll
The file was modifiedllvm/lib/Transforms/Scalar/LoopFlatten.cpp
Commit 96c1fa2a041d352d2b6eb202f3c419323239514f by flo
[SCEV] Add loop-guard pessimizing test with step = 2.
The file was modifiedllvm/test/Analysis/ScalarEvolution/max-backedge-taken-count-guard-info.ll
Commit ed9e1a7dcc2eceb4596a5f2ede7daabcb1fdf4ab by flo
[PhaseOrdering] Add test for missing vectorization with NewPM.
The file was addedllvm/test/Transforms/PhaseOrdering/AArch64/globals-aa-required-for-vectorization.ll
Commit 211761332e4381c37edd91be7c59fc048014ff4e by hokein.wu
[clang-tidy] Allow opt-in or out of some commonly occuring patterns in NarrowingConversionsCheck.

Within clang-tidy's NarrowingConversionsCheck.
* Allow opt-out of some common occurring patterns, such as:
  - Implicit casts between types of equivalent bit widths.
  - Implicit casts occurring from the return of a ::size() method.
  - Implicit casts on size_type and difference_type.
* Allow opt-in of errors within template instantiations.

This will help projects adopt these guidelines iteratively.
Developed in conjunction with Yitzhak Mandelbaum (ymandel).

Patch by Stephen Concannon!

Differential Revision: https://reviews.llvm.org/D99543
The file was modifiedclang-tools-extra/docs/clang-tidy/checks/cppcoreguidelines-narrowing-conversions.rst
The file was addedclang-tools-extra/test/clang-tidy/checkers/cppcoreguidelines-narrowing-conversions-intemplates-option.cpp
The file was modifiedclang-tools-extra/clang-tidy/cppcoreguidelines/NarrowingConversionsCheck.h
The file was addedclang-tools-extra/test/clang-tidy/checkers/cppcoreguidelines-narrowing-conversions-ignoreconversionfromtypes-option.cpp
The file was modifiedclang-tools-extra/clang-tidy/cppcoreguidelines/NarrowingConversionsCheck.cpp
The file was addedclang-tools-extra/test/clang-tidy/checkers/cppcoreguidelines-narrowing-conversions-equivalentbitwidth-option.cpp
Commit d8c227ba05d065046bdb8671f1df73dabaffa222 by thakis
Revert "Produce warning for performing pointer arithmetic on a null pointer."

This reverts commit dfc1e31d49fe1380c9bab43373995df5fed15e6d.
See discussion on https://reviews.llvm.org/D98798
The file was removedclang/test/Sema/pointer-addition.cpp
The file was modifiedclang/test/Sema/pointer-addition.c
The file was modifiedclang/lib/Sema/SemaExpr.cpp
Commit 99d63ccff04b672694f8a2b3eed024b873dc163d by v.g.vassilev
Add type information to integral template argument if required.

Non-comprehensive list of cases:
* Dumping template arguments;
* Corresponding parameter contains a deduced type;
* Template arguments are for a DeclRefExpr that hadMultipleCandidates()

Type information is added in the form of prefixes (u8, u, U, L),
suffixes (U, L, UL, LL, ULL) or explicit casts to printed integral template
argument, if MSVC codeview mode is disabled.

Differential revision: https://reviews.llvm.org/D77598
The file was modifiedclang/lib/Analysis/PathDiagnostic.cpp
The file was addedclang/test/CodeGenCXX/debug-info-codeview-template-type.cpp
The file was modifiedclang/test/SemaTemplate/temp_arg_nontype.cpp
The file was modifiedclang/include/clang/AST/StmtDataCollectors.td
The file was modifiedclang/lib/AST/TypePrinter.cpp
The file was addedclang/test/CXX/lex/lex.literal/lex.ext/p13.cpp
The file was modifiedclang/test/SemaTemplate/matrix-type.cpp
The file was modifiedclang/test/SemaCXX/matrix-type-operators.cpp
The file was modifiedclang-tools-extra/clangd/Hover.cpp
The file was modifiedclang/lib/AST/DeclTemplate.cpp
The file was modifiedclang/include/clang/AST/TemplateBase.h
The file was modifiedclang/tools/libclang/CIndex.cpp
The file was modifiedclang/test/SemaTemplate/delegating-constructors.cpp
The file was modifiedclang/test/SemaTemplate/temp_arg_enum_printing.cpp
The file was modifiedclang/unittests/Tooling/RecursiveASTVisitorTests/TemplateArgumentLocTraverser.cpp
The file was modifiedclang/test/SemaTemplate/temp_arg_nontype_cxx1z.cpp
The file was modifiedclang/lib/AST/TemplateBase.cpp
The file was modifiedclang/test/SemaCXX/cxx11-ast-print.cpp
The file was modifiedclang/test/CXX/lex/lex.literal/lex.ext/p12.cpp
The file was addedclang/test/CodeGenCXX/debug-info-codeview-template-literal.cpp
The file was modifiedclang/lib/Sema/SemaDeclCXX.cpp
The file was modifiedclang/lib/AST/DeclPrinter.cpp
The file was modifiedclang/test/SemaCXX/builtin-align-cxx.cpp
The file was addedclang/test/SemaCXX/cxx1z-ast-print.cpp
The file was addedclang/test/SemaTemplate/default-arguments-ast-print.cpp
The file was modifiedclang/lib/AST/Expr.cpp
The file was modifiedclang/test/SemaCXX/matrix-type-builtins.cpp
The file was modifiedclang/include/clang/AST/Expr.h
The file was modifiedclang/test/Analysis/eval-predefined-exprs.cpp
The file was modifiedclang/lib/Sema/SemaTemplateInstantiate.cpp
The file was modifiedclang/lib/AST/NestedNameSpecifier.cpp
The file was modifiedclang/test/SemaTemplate/address_space-dependent.cpp
The file was modifiedclang/include/clang/AST/DeclTemplate.h
The file was addedclang/test/CXX/lex/lex.literal/lex.ext/p14.cpp
The file was modifiedclang/lib/AST/StmtPrinter.cpp
The file was modifiedclang/lib/AST/ASTTypeTraits.cpp
The file was modifiedclang/lib/Sema/SemaTemplate.cpp
The file was modifiedclang/lib/Sema/SemaTemplateDeduction.cpp
Commit a8f7dee1dffbf8c18acbcc7b1f6d659bf808798e by nikita.ppv
[InstCombine] Support one-hot merge for logical and/or

If a logical and/or is used, we need to be careful not to propagate
a potential poison value from the RHS by inserting a freeze
instruction. Otherwise it works the same way as bitwise and/or.

This is intended to address the regression reported at
https://reviews.llvm.org/D101191#2751002.

Differential Revision: https://reviews.llvm.org/D102279
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
The file was modifiedllvm/test/Transforms/InstCombine/onehot_merge.ll
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineInternal.h
Commit c273f5ef7d3f5ac05f67ec899e25830cd9543e56 by koraq
[libc++][nfc] remove duplicated __to_unsigned.

Both `<type_traits>` and `<charconv>` implemented this function with
different names and a slightly different behavior. This removes the
version in `<charconv>` and improves the version in `<typetraits>`.

- The code can be used again in C++11.
-  The original claimed C++14 support, but `[[nodiscard]]` is not
   available in  C++14.
- Adds `_LIBCPP_INLINE_VISIBILITY`.

Reviewed By: zoecarver, #libc, Quuxplusone

Differential Revision: https://reviews.llvm.org/D102332
The file was modifiedlibcxx/include/__ranges/size.h
The file was modifiedlibcxx/include/type_traits
The file was modifiedlibcxx/include/charconv
Commit 77997f28d5954fa2417806586f2c5c9d1a0ffeef by smeenai
[cmake] Fix typo in function name

Not sure how my local testing didn't trigger this path. Should fix
https://lab.llvm.org/buildbot/#/builders/132/builds/5494
The file was modifiedllvm/cmake/modules/AddLLVM.cmake
Commit 6bd3d8a17cef9108a338ada9b3dbed201bf9c158 by martin
[libcxx] [test] Fix fs.op.last_write_time for Windows

Don't use stat and lstat on Windows; lstat is missing, stat only provides
the modification times with second granularity (and does the wrong thing
regarding symlinks). Instead do a minimal reimplementation using the
native windows APIs.

Differential Revision: https://reviews.llvm.org/D101731
The file was modifiedlibcxx/test/support/filesystem_test_helper.h
The file was modifiedlibcxx/test/std/input.output/filesystems/fs.op.funcs/fs.op.last_write_time/last_write_time.pass.cpp
Commit 7e0768329ca347e37c7bdb0da16b51cb3e7b7d8b by martin
[LLD] [COFF] Fix including the personality function for DWARF EH when linking with --gc-sections

Since c579a5b1d92a9bc2046d00ee2d427832e0f5ddec we don't traverse
.eh_frame when doing GC. But the exception handling personality
function needs to be included, and is only referenced from within
.eh_frame.

Differential Revision: https://reviews.llvm.org/D102138
The file was addedlld/test/COFF/gc-dwarf-eh.s
The file was modifiedlld/COFF/Driver.cpp
Commit a8053399cde847dfce88d7d1fa2a2099f3a58c40 by i
[ELF][AVR] Add explicit relocation types to getRelExpr
The file was modifiedlld/ELF/Arch/AVR.cpp
Commit 4b014352308f7244b86438fff7c61c632934a1ff by rob.suderman
[mlir][tosa] Remove tosa.identityn operator

Removes the identityn operator from TOSA MLIR definition.
Removes TosaToLinAlg mappings

Reviewed By: rsuderman

Differential Revision: https://reviews.llvm.org/D102329
The file was modifiedmlir/include/mlir/Dialect/Tosa/IR/TosaOps.td
The file was modifiedmlir/lib/Conversion/TosaToLinalg/TosaToLinalg.cpp
The file was modifiedmlir/test/Dialect/Tosa/ops.mlir
The file was modifiedmlir/docs/Dialects/TOSA.md
The file was modifiedmlir/test/Conversion/TosaToLinalg/tosa-to-linalg.mlir
Commit 08ba9ce1ef7214623d4104e72d817c73644a0884 by erich.keane
Suppress Deferred Diagnostics in discarded statements.

It doesn't really make sense to emit language specific diagnostics
in a discarded statement, and suppressing these diagnostics results in a
programming pattern that many users will feel is quite useful.

Basically, this makes sure we only emit errors from the 'true' side of a
'constexpr if'.

It does this by making the ExprEvaluatorBase type have an opt-in option
as to whether it should visit discarded cases.

Differential Revision: https://reviews.llvm.org/D102251
The file was modifiedclang/lib/Sema/Sema.cpp
The file was modifiedclang/include/clang/AST/Stmt.h
The file was modifiedclang/lib/AST/Stmt.cpp
The file was modifiedclang/include/clang/AST/EvaluatedExprVisitor.h
The file was modifiedclang/test/SemaCUDA/deferred-diags.cu
Commit 30b7dfafdb620420ad3498aae01130bc7e2fb9cd by smeenai
[flang] Fix standalone builds

Flang's CMake modules directory was being added to the CMake module path
twice, and AddFlang was being included after the first addition. Remove
the unnecessary first addition and move the AddFlang include down to the
second one. This way, it occurs after LLVM's CMake modules have been
included for a standalone build, so it can make use of those modules.
The file was modifiedflang/CMakeLists.txt
Commit b3911cdfc89f3b560fc00048d6f99280268fa63c by riddleriver
[mlir-lsp-server] Add support for sending diagnostics to the client

This allows for diagnostics emitted during parsing/verification to be surfaced to the user by the language client, as opposed to just being emitted to the logs like they are now.

Differential Revision: https://reviews.llvm.org/D102293
The file was modifiedmlir/lib/Tools/mlir-lsp-server/MLIRServer.cpp
The file was modifiedmlir/lib/Tools/mlir-lsp-server/lsp/Transport.h
The file was modifiedmlir/lib/Tools/mlir-lsp-server/MLIRServer.h
The file was addedmlir/test/mlir-lsp-server/diagnostics.test
The file was modifiedmlir/lib/Parser/AsmParserState.cpp
The file was modifiedmlir/lib/Tools/mlir-lsp-server/LSPServer.cpp
The file was modifiedmlir/lib/Tools/mlir-lsp-server/lsp/Protocol.cpp
The file was modifiedmlir/lib/Tools/mlir-lsp-server/lsp/Protocol.h
The file was modifiedmlir/lib/Tools/mlir-lsp-server/lsp/Transport.cpp
The file was modifiedmlir/include/mlir/Parser/AsmParserState.h
Commit 29ac15ab380b6d9853d4cdc9c220107e90375cb9 by riddleriver
[mlir-lsp-server][NFC] Add newline between Protocol JSON serialization methods and class definitions.
The file was modifiedmlir/lib/Tools/mlir-lsp-server/lsp/Protocol.h
Commit 5bb7e81c64bd29edd1c9ebadd4e4717919def0bf by richard
Fix bad mangling of <data-member-prefix> for a closure in the initializer of a variable at global namespace scope.

This implements the direction proposed in
https://github.com/itanium-cxx-abi/cxx-abi/pull/126.

Differential Revision: https://reviews.llvm.org/D101968
The file was modifiedclang/test/CodeGenCXX/clang-abi-compat.cpp
The file was modifiedclang/test/CodeGenCXX/mangle-lambda-explicit-template-params.cpp
The file was modifiedclang/lib/Frontend/CompilerInvocation.cpp
The file was modifiedclang/include/clang/Basic/CodeGenOptions.h
The file was modifiedclang/include/clang/Basic/LangOptions.h
The file was modifiedclang/test/CodeGenCXX/lambda-expressions-nested-linkage.cpp
The file was modifiedclang/lib/AST/ItaniumMangle.cpp
Commit 9c345407b4999e62e51667927f531b891363569b by craig.topper
[RISCV] Remove RISCVII:VSEW enum. Make encodeVYPE operate directly on SEW.

The VSEW encoding isn't a useful value to pass around. It's better
to use SEW or log2(SEW) directly. The only real ugliness is that
the vsetvli IR intrinsics use the VSEW encoding, but it's easy
enough to decode that when the intrinsic is processed.
The file was modifiedllvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
The file was modifiedllvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.cpp
The file was modifiedllvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
The file was modifiedllvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
Commit ba38b72ec2833bf8c54829a0fd7a8c968e6260d4 by aheejin
[WebAssembly] Allow Wasm EH with Emscripten SjLj

We explicitly made it error out in D101403, out of a good intention that
the error message will make people less confusing. Turns out, we weren't
failing all cases of wasm EH + SjLj; only a few cases were failing and
our client was able to get around by fixing source code, but now we made
it fail for all cases, even the cases that previously succeeded fail,
which we didn't intend. This reverts that change.

Reviewed By: tlively

Differential Revision: https://reviews.llvm.org/D102364
The file was modifiedllvm/test/CodeGen/WebAssembly/lower-em-ehsjlj-options.ll
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyLowerEmscriptenEHSjLj.cpp
Commit 3041b16f7322a0392810e4a14b13cacac1929ad8 by sbc
[WebAssembly] Add TLS data segment flag: WASM_SEG_FLAG_TLS

Previously the linker was relying solely on the name of the segment
to imply TLS.

Differential Revision: https://reviews.llvm.org/D102202
The file was modifiedlld/test/wasm/tls.s
The file was modifiedllvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
The file was modifiedllvm/test/MC/WebAssembly/tls.s
The file was modifiedllvm/include/llvm/BinaryFormat/Wasm.h
The file was modifiedllvm/lib/MC/MCParser/WasmAsmParser.cpp
The file was modifiedllvm/lib/ObjectYAML/WasmYAML.cpp
The file was modifiedllvm/test/CodeGen/WebAssembly/tls-general-dynamic.ll
The file was modifiedlld/wasm/InputChunks.h
The file was modifiedllvm/lib/MC/MCSectionWasm.cpp
The file was modifiedllvm/test/CodeGen/WebAssembly/target-features-tls.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/tls-local-exec.ll
The file was modifiedlld/wasm/Writer.cpp
Commit cd01430ff13b5441bc71e6dc3c4e688052f7be82 by sbc
[lld][WebAssembly] Allow data symbols to extend past end of segment

This fixes a bug with string merging with string symbols that contain
NULLs, as is the case in the `merge-string.s` test.

The bug only showed when we run with `--relocatable` and then try read
the resulting object back in.  In this case we would end up with string
symbols that extend past the end of the segment in which they live.

The problem comes from the fact that sections which are flagged as
string mergable assume that all strings are NULL terminated.  The
merging algorithm will drop trailing chars that follow a NULL since they
are essentially unreachable.  However, the "size" attribute (in the
symbol table) of such a truncated symbol is not updated resulting a
symbol size that can overlap the end of the segment.

I verified that this can happen in ELF too given the right conditions
and the its harmless enough.  In practice Strings that contain embedded
null should not be part of a mergable section.

Differential Revision: https://reviews.llvm.org/D102281
The file was modifiedlld/test/wasm/merge-string.s
The file was addedllvm/test/Object/wasm-bad-data-symbol.yaml
The file was modifiedllvm/lib/Object/WasmObjectFile.cpp
Commit fb3a00c327df78eaa534e53ac6f07112e0585121 by riddleriver
[mlir] Fix ssa values naming bug

Address comments in https://reviews.llvm.org/D102226 to fix the bug + style violations

Differential Revision: https://reviews.llvm.org/D102368
The file was modifiedmlir/lib/IR/AsmPrinter.cpp
Commit e5bdacba2e185034979fddd8bff2695bfcdd3056 by gclayton
Optimize GSymCreator::finalize.

The algorithm removing duplicates from the Funcs list used to have
amortized quadratic time complexity because it was potentially
removing each entry using std::vector::erase individually. This
patch is now using a erase-remove idiom with an adapted
removeIfBinary algorithm.

Probably this was made under the assumption that these removals are
rare, but there are cases where the case of duplicate entries is
occurring frequently. In these cases, the actual runtime was very
poor, taking hours to process a single binary of around 1 GiB size
including debug info. Another factor contributing to that is the
frequent output of the warning, which is now removed.

It seems this is particularly an issue with GCC-compiled binaries,
rather than clang-built binaries.

Reviewed By: clayborg

Differential Revision: https://reviews.llvm.org/D102219
The file was modifiedllvm/lib/DebugInfo/GSYM/GsymCreator.cpp
Commit e7d26aceca071d67168062b2f7784c56234b0cb3 by Justin Bogner
Change the context instruction for computeKnownBits in LoadStoreVectorizer pass

This change enables cases for which the index value for the first
load/store instruction in a pair could be a function argument. This
allows using llvm.assume to provide known bits information in such
cases.

Patch by Viacheslav Nikolaev. Thanks!

Differential Revision: https://reviews.llvm.org/D101680
The file was modifiedllvm/test/Transforms/LoadStoreVectorizer/X86/vectorize-i8-nested-add.ll
The file was modifiedllvm/lib/Transforms/Vectorize/LoadStoreVectorizer.cpp
Commit b7911e80d6926f9280ceb23d4e86e25c29370904 by ravishankarm
[mlir][Linalg] Add interface methods to get lhs and rhs of contraction

Differential Revision: https://reviews.llvm.org/D102301
The file was modifiedmlir/include/mlir/Dialect/Linalg/IR/LinalgInterfaces.td
Commit bd00106d1e77e4de769ce0d143c97a076f25c92b by Stanislav.Mekhanoshin
[AMDGPU] Refactor shouldExpandAtomicRMWInIR(). NFC.

This is logic simplification for better readability.

Differential Revision: https://reviews.llvm.org/D102371
The file was modifiedllvm/lib/Target/AMDGPU/SIISelLowering.cpp
Commit 58d12332a4730226d0a640136f06f3bd0861f1a5 by ajcbik
[mlir][sparse][capi][python] add sparse tensor passes

First set of "boilerplate" to get sparse tensor
passes available through CAPI and Python.

Reviewed By: stellaraccident

Differential Revision: https://reviews.llvm.org/D102362
The file was modifiedmlir/include/mlir-c/Dialect/SparseTensor.h
The file was modifiedmlir/python/mlir/dialects/sparse_tensor.py
The file was addedmlir/test/python/dialects/sparse_tensor/passes.py
The file was addedmlir/lib/Bindings/Python/SparseTensorPasses.cpp
The file was addedmlir/lib/CAPI/Dialect/SparseTensorPasses.cpp
The file was modifiedmlir/lib/CAPI/Dialect/CMakeLists.txt
The file was modifiedmlir/lib/Bindings/Python/CMakeLists.txt
The file was modifiedmlir/include/mlir/Dialect/SparseTensor/Transforms/CMakeLists.txt
Commit 46c17429bc86dc5ccddb5512b77bd1ede39c9ccd by cjdb
[libcxx] modifies `_CmpUnspecifiedParam` ignore types outside its domain

D85051's honeypot solution was a bit too aggressive swallowed up the
comparison types, which made comparing objects of different ordering
types ambiguous.

Depends on D101707.

Differential Revision: https://reviews.llvm.org/D101708
The file was modifiedlibcxx/test/std/language.support/cmp/cmp.strongord/strongord.pass.cpp
The file was modifiedlibcxx/test/std/language.support/cmp/cmp.weakord/weakord.pass.cpp
The file was modifiedlibcxx/include/compare
The file was modifiedlibcxx/test/std/language.support/cmp/cmp.partialord/partialord.pass.cpp
The file was modifiedlibcxx/test/std/language.support/cmp/cmp.categories.pre/zero_type.verify.cpp
Commit 6732a5328cf03872d53827d3e0e283fcf16b551a by peter
scudo: Require fault address to be in bounds for UAF.

The bounds check that we previously had here was suitable for secondary
allocations but not for UAF on primary allocations, where it is likely
to result in false positives. Fix it by using a different bounds check
for UAF that requires the fault address to be in bounds.

Differential Revision: https://reviews.llvm.org/D102376
The file was modifiedcompiler-rt/lib/scudo/standalone/combined.h
Commit 10c779d2065f7e216660f1687244269afcee13b1 by Pushpinder.Singh
[AMDGPU][OpenMP] Emit textual IR for -emit-llvm -S

Previously clang would print a binary blob into the bundled file
for amdgcn. With this patch, it will instead print textual IR as
expected.

Reviewed By: JonChesterfield, ronlieb

Differential Revision: https://reviews.llvm.org/D102065

Change-Id: I10c0127ab7357787769fdf9a2edd4b3071e790a1
The file was modifiedclang/lib/Driver/ToolChains/Clang.cpp
The file was modifiedclang/test/Driver/amdgpu-openmp-toolchain.c
Commit 4c88cfb1dc79227be78f8dade966934384914e5e by richard
Add test for substitutability of variable templates in closure type
mangling.
The file was modifiedclang/test/CodeGenCXX/mangle-lambdas.cpp
Commit e0acfed7ed5173b437868f75fc394084487e390a by richard
Clean up handling of constrained parameters in lambdas.

No functionality change intended.
The file was modifiedclang/lib/Sema/SemaTemplateInstantiateDecl.cpp
The file was modifiedclang/lib/AST/TypePrinter.cpp
The file was modifiedclang/lib/Sema/SemaTemplateInstantiate.cpp
The file was modifiedclang/lib/Sema/TreeTransform.h
Commit 2f9d8b08ea658b612065cbf7d4b0fbd7f28bb36a by richard
PR50306: When instantiating a generic lambda with a constrained 'auto',
properly track that it has constraints.

Previously an instantiation of a constrained generic lambda would behave
as if unconstrained because we incorrectly cached a "has no constraints"
value that we computed before the constraints from 'auto' parameters
were attached.
The file was modifiedclang/lib/AST/DeclTemplate.cpp
The file was modifiedclang/test/SemaTemplate/concepts.cpp
Commit e1aa528d3aaf5fcf9c50d1e34b39dbde1e63801d by richard
Handle unexpanded packs appearing in type-constraints.

For a type-constraint in a lambda signature, this makes the lambda
contain an unexpanded pack; for requirements in a requires-expressions
it makes the requires-expression contain an unexpanded pack; otherwise
it's invalid.
The file was modifiedclang/include/clang/Sema/Sema.h
The file was modifiedclang/lib/AST/Type.cpp
The file was modifiedclang/test/SemaTemplate/concepts.cpp
The file was modifiedclang/lib/AST/DeclTemplate.cpp
The file was modifiedclang/lib/Sema/SemaType.cpp
The file was modifiedclang/lib/Sema/SemaExprCXX.cpp
The file was modifiedclang/lib/Sema/SemaTemplate.cpp
The file was modifiedclang/include/clang/AST/DeclTemplate.h
The file was modifiedclang/include/clang/AST/RecursiveASTVisitor.h
Commit 017d7a9e14245e549999c5e3b8bd7398fcf79410 by Adrian Prantl
Rename human-readable name for DW_LANG_Mips_Assembler

The Mips in DW_LANG_Mips_Assembler is a vendor name not an
architecture name and in lack of a proper generic DW_LANG_assembler,
some assemblers emit DWARF using this tag. Due to a warning I recently
introduced users will now be greeted with

  This version of LLDB has no plugin for the mipsassem language. Inspection of frame variables will be limited.

By renaming this to just "Assembler" this error message will make more sense.

Differential Revision: https://reviews.llvm.org/D101406

rdar://77214764
The file was modifiedlldb/source/Target/Process.cpp
The file was modifiedlldb/test/Shell/Process/UnsupportedLanguage.test
The file was modifiedlldb/source/Target/Language.cpp
Commit ce6cc87ce9e96eaa5e5ef0c1f5dc07b41381996d by Yaxun.Liu
[clang] Minor fix for MarkVarDeclODRUsed

Merge two if as follow up of https://reviews.llvm.org/D102270
The file was modifiedclang/lib/Sema/SemaExpr.cpp
Commit c9087788f7e41285445729127dd07ff7f82e3fc0 by springerm
[mlir] Fix masked vector transfer ops with broadcasts

Broadcast dimensions of a vector transfer op have no corresponding dimension in the mask vector. E.g., a 2-D TransferReadOp, where one dimension is a broadcast, can have a 1-D `mask` attribute.

This commit also adds a few additional transfer op integration tests for various combinations of broadcasts, masking, dim transposes, etc.

Differential Revision: https://reviews.llvm.org/D101745
The file was modifiedmlir/test/Integration/Dialect/Vector/CPU/test-transfer-read-3d.mlir
The file was modifiedmlir/lib/Conversion/VectorToSCF/ProgressiveVectorToSCF.cpp
The file was modifiedmlir/test/Integration/Dialect/Vector/CPU/test-transfer-read-1d.mlir
The file was modifiedmlir/test/Integration/Dialect/Vector/CPU/test-transfer-read-2d.mlir
The file was modifiedmlir/lib/Dialect/Vector/VectorOps.cpp
The file was modifiedmlir/include/mlir/Interfaces/VectorInterfaces.h
The file was modifiedmlir/include/mlir/Interfaces/VectorInterfaces.td
The file was modifiedmlir/lib/Interfaces/VectorInterfaces.cpp
Commit 6555e53ab0f2bca3dc30f5ab3a2d6872d50b6ff8 by springerm
Revert "[mlir] Fix masked vector transfer ops with broadcasts"

This reverts commit c9087788f7e41285445729127dd07ff7f82e3fc0.

Accidentally pushed old version of the commit.
The file was modifiedmlir/test/Integration/Dialect/Vector/CPU/test-transfer-read-2d.mlir
The file was modifiedmlir/include/mlir/Interfaces/VectorInterfaces.td
The file was modifiedmlir/test/Integration/Dialect/Vector/CPU/test-transfer-read-3d.mlir
The file was modifiedmlir/include/mlir/Interfaces/VectorInterfaces.h
The file was modifiedmlir/lib/Interfaces/VectorInterfaces.cpp
The file was modifiedmlir/lib/Conversion/VectorToSCF/ProgressiveVectorToSCF.cpp
The file was modifiedmlir/lib/Dialect/Vector/VectorOps.cpp
The file was modifiedmlir/test/Integration/Dialect/Vector/CPU/test-transfer-read-1d.mlir
Commit a0ca4c46ca35957a38a6023fa84afda2fc9ba0ec by czhengsz
[Debug-Info] add -gstrict-dwarf support in backend

Reviewed By: dblaikie, probinson

Differential Revision: https://reviews.llvm.org/D100826
The file was modifiedclang/lib/CodeGen/BackendUtil.cpp
The file was modifiedllvm/include/llvm/Target/TargetOptions.h
The file was modifiedllvm/lib/CodeGen/CommandFlags.cpp
The file was addedllvm/test/DebugInfo/PowerPC/strict-dwarf.ll
The file was modifiedllvm/include/llvm/CodeGen/CommandFlags.h
Commit c52cbe63e42fff8c1a95921effd35d7bb59301d3 by springerm
[mlir] Fix masked vector transfer ops with broadcasts

Broadcast dimensions of a vector transfer op have no corresponding dimension in the mask vector. E.g., a 2-D TransferReadOp, where one dimension is a broadcast, can have a 1-D `mask` attribute.

This commit also adds a few additional transfer op integration tests for various combinations of broadcasts, masking, dim transposes, etc.

Differential Revision: https://reviews.llvm.org/D101745
The file was modifiedmlir/lib/Interfaces/VectorInterfaces.cpp
The file was modifiedmlir/test/Dialect/Vector/invalid.mlir
The file was modifiedmlir/include/mlir/Interfaces/VectorInterfaces.h
The file was modifiedmlir/test/Integration/Dialect/Vector/CPU/test-transfer-read-3d.mlir
The file was modifiedmlir/include/mlir/Interfaces/VectorInterfaces.td
The file was modifiedmlir/test/Dialect/Vector/ops.mlir
The file was modifiedmlir/test/Integration/Dialect/Vector/CPU/test-transfer-read-2d.mlir
The file was modifiedmlir/lib/Conversion/VectorToSCF/ProgressiveVectorToSCF.cpp
The file was modifiedmlir/lib/Dialect/Vector/VectorOps.cpp
The file was modifiedmlir/test/Integration/Dialect/Vector/CPU/test-transfer-read-1d.mlir
Commit 864adf399e58a6bfd823136fc2cbcfe9dff5b4a8 by springerm
[mlir] Allow empty position in vector.insert and vector.extract

Such ops are no-ops and are folded to their respective `source`/`vector` operand.

Differential Revision: https://reviews.llvm.org/D101879
The file was modifiedmlir/lib/Dialect/Vector/VectorOps.cpp
The file was modifiedmlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp
The file was modifiedmlir/test/Dialect/Vector/invalid.mlir
The file was modifiedmlir/test/Dialect/Vector/ops.mlir
The file was modifiedmlir/include/mlir/Dialect/Vector/VectorOps.td
Commit 9b77be5583d2da03f2ccd7319d33a2daedf8b1b3 by springerm
[mlir] Unrolled progressive-vector-to-scf.

Instead of an SCF for loop, these pattern generate fully unrolled loops with no temporary buffer allocations.

Differential Revision: https://reviews.llvm.org/D101981
The file was modifiedmlir/test/Integration/Dialect/Vector/CPU/test-transfer-read-1d.mlir
The file was modifiedmlir/test/lib/Transforms/TestVectorTransforms.cpp
The file was addedmlir/test/Conversion/VectorToSCF/unrolled-vector-to-loops.mlir
The file was modifiedmlir/test/Integration/Dialect/Vector/CPU/test-transfer-read-2d.mlir
The file was modifiedmlir/lib/Conversion/VectorToSCF/ProgressiveVectorToSCF.cpp
The file was modifiedmlir/lib/Interfaces/VectorInterfaces.cpp
The file was modifiedmlir/test/Integration/Dialect/Vector/CPU/test-transfer-read-3d.mlir
The file was modifiedmlir/include/mlir/Conversion/VectorToSCF/ProgressiveVectorToSCF.h
Commit 2a51e9ff2e06d5d7096f826014916b4cc02269fc by springerm
[mlir] Support memref layout maps in vector transfer ops

Differential Revision: https://reviews.llvm.org/D102042
The file was modifiedmlir/lib/Conversion/VectorToSCF/ProgressiveVectorToSCF.cpp
Commit 44a4000181e1a25027e87f2ae4e71cb876a7a275 by v.g.vassilev
[clang-repl] Land initial infrastructure for incremental parsing

In http://lists.llvm.org/pipermail/llvm-dev/2020-July/143257.html we have
mentioned our plans to make some of the incremental compilation facilities
available in llvm mainline.

This patch proposes a minimal version of a repl, clang-repl, which enables
interpreter-like interaction for C++. For instance:

./bin/clang-repl
clang-repl> int i = 42;
clang-repl> extern "C" int printf(const char*,...);
clang-repl> auto r1 = printf("i=%d\n", i);
i=42
clang-repl> quit

The patch allows very limited functionality, for example, it crashes on invalid
C++. The design of the proposed patch follows closely the design of cling. The
idea is to gather feedback and gradually evolve both clang-repl and cling to
what the community agrees upon.

The IncrementalParser class is responsible for driving the clang parser and
codegen and allows the compiler infrastructure to process more than one input.
Every input adds to the “ever-growing” translation unit. That model is enabled
by an IncrementalAction which prevents teardown when HandleTranslationUnit.

The IncrementalExecutor class hides some of the underlying implementation
details of the concrete JIT infrastructure. It exposes the minimal set of
functionality required by our incremental compiler/interpreter.

The Transaction class keeps track of the AST and the LLVM IR for each
incremental input. That tracking information will be later used to implement
error recovery.

The Interpreter class orchestrates the IncrementalParser and the
IncrementalExecutor to model interpreter-like behavior. It provides the public
API which can be used (in future) when using the interpreter library.

Differential revision: https://reviews.llvm.org/D96033
The file was addedclang/lib/Interpreter/Interpreter.cpp
The file was addedclang/unittests/Interpreter/CMakeLists.txt
The file was modifiedclang/unittests/CodeGen/CMakeLists.txt
The file was addedclang/unittests/Interpreter/InterpreterTest.cpp
The file was modifiedclang/lib/CMakeLists.txt
The file was addedclang/include/clang/Interpreter/Transaction.h
The file was modifiedclang/test/lit.cfg.py
The file was modifiedclang/include/clang/Frontend/FrontendAction.h
The file was modifiedclang/unittests/CMakeLists.txt
The file was modifiedclang/lib/Frontend/FrontendAction.cpp
The file was addedclang/unittests/Interpreter/IncrementalProcessingTest.cpp
The file was addedclang/test/Interpreter/sanity.c
The file was modifiedclang/test/CMakeLists.txt
The file was addedclang/test/Interpreter/execute.cpp
The file was addedclang/tools/clang-repl/ClangRepl.cpp
The file was modifiedclang/lib/CodeGen/CodeGenAction.cpp
The file was addedclang/include/clang/Interpreter/Interpreter.h
The file was addedclang/lib/Interpreter/IncrementalExecutor.h
The file was addedclang/lib/Interpreter/IncrementalExecutor.cpp
The file was modifiedclang/tools/CMakeLists.txt
The file was addedclang/tools/clang-repl/CMakeLists.txt
The file was addedclang/lib/Interpreter/CMakeLists.txt
The file was addedclang/lib/Interpreter/IncrementalParser.cpp
The file was addedclang/lib/Interpreter/IncrementalParser.h
The file was modifiedclang/include/clang/CodeGen/CodeGenAction.h
The file was removedclang/unittests/CodeGen/IncrementalProcessingTest.cpp
Commit 00a0595b253f22f5138eb0ceaf892dbe8e670453 by anton.a.afanasyev
[SLP][Test] Fix and precommit tests for D98714
The file was modifiedllvm/test/Transforms/SLPVectorizer/AMDGPU/round.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/AMDGPU/round-inseltpoison.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/AMDGPU/bswap-inseltpoison.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/AMDGPU/bswap.ll
Commit cd9090031c83ee857f82c3344b6efd97185c928e by anton.a.afanasyev
[SLP][Test] Fix and precommit tests for D98714
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/pr47629-inseltpoison.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/pr47629.ll
Commit ab2c499d3a2ed3d3e13d96e456c57fb35a114b31 by anton.a.afanasyev
[SLP] Add insertelement instructions to vectorizable tree

Add new type of tree node for `InsertElementInst` chain forming vector.
These instructions could be either removed, or replaced by shuffles during
vectorization and we can add this node to cost model, so naturally estimating
their cost, getting rid of `CompensateCost` tricks and reducing further work
for InstCombine. This fixes PR40522 and PR35732 in a natural way. Also this
patch is the first step towards revectorization of partially vectorization
(to fix PR42022 completely). After adding inserts to tree the next step is
to add vector instructions there (for instance, to merge `store <2 x float>`
and `store <2 x float>` to `store <4 x float>`).

Fixes PR40522 and PR35732.

Differential Revision: https://reviews.llvm.org/D98714
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/sitofp.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/long_chains.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/zext-inseltpoison.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/AMDGPU/add_sub_sat.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/AArch64/vectorize-free-extracts-inserts.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/PR35865-inseltpoison.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/load-merge-inseltpoison.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/pr44067-inseltpoison.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/AArch64/transpose.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/sitofp-inseltpoison.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/alternate-int.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/AMDGPU/bswap.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/blending-shuffle-inseltpoison.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/alternate-int-inseltpoison.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/vectorizable-functions.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/PR39774.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/fptosi.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/pr44067.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/ARM/extract-insert.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/PR35865.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/sext.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/AArch64/transpose-inseltpoison.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/pr40522.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/AArch64/insertelement-inseltpoison.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/blending-shuffle.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/hadd-inseltpoison.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/hsub-inseltpoison.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/sign-extend-inseltpoison.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/alternate-fp-inseltpoison.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/AArch64/insertelement.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/hsub.ll
The file was modifiedllvm/include/llvm/Transforms/Vectorize/SLPVectorizer.h
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/value-bug.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/AMDGPU/add_sub_sat-inseltpoison.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/alternate-fp.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/AArch64/gather-root.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/phi.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/pr31599-inseltpoison.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/hadd.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/arith-fp-inseltpoison.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/AArch64/accelerate-vector-functions-inseltpoison.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/ARM/extract-insert-inseltpoison.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/pr31599.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/insert-element-build-vector-inseltpoison.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/alternate-cast.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/external_user_jumbled_load.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/resched.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/pr47629-inseltpoison.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/AMDGPU/crash_extract_subvector_cost.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/fptosi-inseltpoison.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/load-merge.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/value-bug-inseltpoison.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/arith-fp.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/sext-inseltpoison.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/zext.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/AMDGPU/bswap-inseltpoison.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/AMDGPU/round-inseltpoison.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/vectorizable-functions-inseltpoison.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/sign-extend.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/AArch64/accelerate-vector-functions.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/insert-element-build-vector.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/AMDGPU/round.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/external_user_jumbled_load-inseltpoison.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/operandorder.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/alternate-cast-inseltpoison.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/pr47629.ll
The file was modifiedllvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Commit 6e5b8f489a27901de4b9dfa152da02dbca13ec31 by yedeng.yd
[Coroutines] Enable printing coroutine frame when dbg info is available

Summary: This patch tries to build debug info for coroutine frame in the
middle end. Although the coroutine frame is constructed and maintained by
the compiler and the programmer shouldn't care about the coroutine frame
by the design of C++20 coroutine,
a lot of programmers told me that they want to see the layout of the
coroutine frame strongly. Although C++ is designed as an abstract layer
so that the programmers shouldn't care about the actual memory in bits,
many experienced C++ programmers  are familiar with assembler and
debugger to see the memory layout in fact, After I was been told they
want to see the coroutine frame about 3 times, I think it is an actual
and desired demand.

However, the debug information is constructed in the front end and
coroutine frame is constructed in the middle end. This is a natural and
clear gap. So I could only try to construct the debug information in the
middle end after coroutine frame constructed. It is unusual, but we are
in consensus that the approch is the best one.

One hard part is we need construct the name for variables since there
isn't a map from llvm variables to DIVar. Then here is the strategy this
patch uses:
- The name `__resume_fn `, `__destroy_fn` and `__coro_index ` are
  constructed by the patch.
- Then the name `__promise` comes from the dbg.variable of corresponding
  dbg.declare of PromiseAlloca, which shows highest priority to
construct the debug information for the member of coroutine frame.
- Then if the member is struct, we would try to get the name of the llvm
  struct directly. Then replace ':' and '.' with '_' to make it
printable for debugger.
- If the member is a basic type like integer or double, we would try to
  emit the corresponding name.
- Then if the member is a Pointer Type, we would add `Ptr` after
  corresponding pointee type.
- Otherwise, we would name it with 'UnknownType'.

Reviewered by: lxfind, aprantl, rjmcall, dblaikie

Differential Revision: https://reviews.llvm.org/D99179
The file was modifiedllvm/lib/Transforms/Coroutines/CoroInternal.h
The file was modifiedllvm/lib/Transforms/Coroutines/CoroFrame.cpp
The file was modifiedllvm/test/Transforms/Coroutines/coro-inline.ll
The file was addedllvm/test/Transforms/Coroutines/coro-debug-coro-frame.ll
Commit f6907152db3d70606817ffe28274c6a90b331bbc by v.g.vassilev
Revert "[clang-repl] Land initial infrastructure for incremental parsing"

This reverts commit 44a4000181e1a25027e87f2ae4e71cb876a7a275.

We are seeing build failures due to missing dependency to libSupport and
CMake Error at tools/clang/tools/clang-repl/cmake_install.cmake
file INSTALL cannot find
The file was modifiedclang/unittests/CodeGen/CMakeLists.txt
The file was modifiedclang/lib/CodeGen/CodeGenAction.cpp
The file was modifiedclang/unittests/CMakeLists.txt
The file was removedclang/lib/Interpreter/IncrementalExecutor.h
The file was removedclang/unittests/Interpreter/IncrementalProcessingTest.cpp
The file was modifiedclang/test/lit.cfg.py
The file was modifiedclang/lib/Frontend/FrontendAction.cpp
The file was removedclang/test/Interpreter/sanity.c
The file was removedclang/unittests/Interpreter/InterpreterTest.cpp
The file was addedclang/unittests/CodeGen/IncrementalProcessingTest.cpp
The file was removedclang/lib/Interpreter/IncrementalExecutor.cpp
The file was modifiedclang/lib/CMakeLists.txt
The file was removedclang/tools/clang-repl/ClangRepl.cpp
The file was removedclang/lib/Interpreter/CMakeLists.txt
The file was removedclang/lib/Interpreter/Interpreter.cpp
The file was removedclang/lib/Interpreter/IncrementalParser.cpp
The file was removedclang/unittests/Interpreter/CMakeLists.txt
The file was removedclang/include/clang/Interpreter/Transaction.h
The file was removedclang/include/clang/Interpreter/Interpreter.h
The file was modifiedclang/test/CMakeLists.txt
The file was modifiedclang/include/clang/Frontend/FrontendAction.h
The file was modifiedclang/tools/CMakeLists.txt
The file was removedclang/tools/clang-repl/CMakeLists.txt
The file was removedclang/lib/Interpreter/IncrementalParser.h
The file was removedclang/test/Interpreter/execute.cpp
The file was modifiedclang/include/clang/CodeGen/CodeGenAction.h
Commit 3f8aafd7902722cc2039c7ef3d6747f8d49f81a6 by rob.suderman
[mlir][tosa] Fix tosa.cast semantics to perform rounding/clipping

Rounding to integers requires rounding (for floating points) and clipping
to the min/max values of the destination range. Added this behavior and
updated tests appropriately.

Reviewed By: sjarus, silvas

Differential Revision: https://reviews.llvm.org/D102375
The file was modifiedmlir/lib/Conversion/TosaToLinalg/TosaToLinalg.cpp
The file was modifiedmlir/test/Conversion/TosaToLinalg/tosa-to-linalg.mlir
Commit c1359ef07e8240b4350802b4998aedc1239a91d0 by yedeng.yd
[Coroutines] Salvege Debug.values

Summary: The previous implementation of coro-split didn't collect values
used by dbg instructions into the spills which made a log debug info
unavailable with optimization on.
This patch tries to collect these uses which are used by dbg.values. In
this way, the debugbility of coroutine could be as powerful as normal
functions with optimization on.

To avoid enlarging the coroutine frame, this patch only collects
`dbg.value` whose value is already in the coroutine frame. This decision
may make some debug info getting unavailable. But if we are with
optimization on, the performance issue should be considered first. And
this patch would make the debugbility of coroutine to be better only
without changing the layout of the frame.

Test-plan: check-llvm

Reviewed By: aprantl, lxfind

Differential Revision: https://reviews.llvm.org/D97673
The file was modifiedllvm/lib/Transforms/Coroutines/CoroSplit.cpp
The file was addedllvm/test/Transforms/Coroutines/coro-debug-dbg.values.ll
The file was modifiedllvm/lib/Transforms/Coroutines/CoroFrame.cpp
The file was addedllvm/test/Transforms/Coroutines/coro-debug-dbg.values-not_used_in_frame.ll
The file was modifiedllvm/lib/Transforms/Coroutines/CoroInternal.h
Commit 0c443e92d3b9bc5a25214f2c8418b72501a15a00 by Jason Molenda
Add some warnings when debugserver is running in translation

A debugserver launched x86_64 cannot control an arm64/arm64e
process on an Apple Silicon system.  Warn when this situation
has happened and return an error for the most common case of
attach.  I think there will be refinements to this in the
future, but start out by making it easy to spot the problem
when it happens.

rdar://76630595
The file was modifiedlldb/tools/debugserver/source/DNB.h
The file was modifiedlldb/tools/debugserver/source/RNBRemote.cpp
The file was modifiedlldb/tools/debugserver/source/DNB.cpp
The file was modifiedlldb/tools/debugserver/source/debugserver.cpp
Commit 4b0f5edd36c685333985698d1a288d2eb641b910 by Lang Hames
[JITLink] Add a transferDefinedSymbol operation.

The transferDefinedSymbol operation updates a Symbol's target block, offset,
and size. This can be convenient when you want to redefine the content of some
symbol(s) pointing at a block, while retaining the original block in the graph.
The file was modifiedllvm/unittests/ExecutionEngine/JITLink/LinkGraphTests.cpp
The file was modifiedllvm/include/llvm/ExecutionEngine/JITLink/JITLink.h
Commit 2f21a272af69321555cdc2794664b5eba8fc3276 by Lang Hames
[JITLink] Expose x86-64 pointer jump stub block construction.

This can be useful for clients who want to define their own symbol for the
stub, or re-use some existing symbol.
The file was modifiedllvm/include/llvm/ExecutionEngine/JITLink/x86_64.h
Commit d8b37de8a478c1b1532e45b0bfd82ecf1c964d9a by mkazantsev
[GC][NFC] Move GCStrategy from CodeGen to IR

We want it to be available in analyzes so that we could use the
CodeGen notion in middle-end passes (for example, to check if
a GC may free some particular pointer).

This is a preparatory patch that simply moves the files around.

Note: if this causes some build issues, this patch must just be reverted.

Differential Revision: https://reviews.llvm.org/D100557
Reviewed By: reames
The file was addedllvm/lib/IR/GCStrategy.cpp
The file was modifiedllvm/include/llvm/CodeGen/GCMetadata.h
The file was modifiedllvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
The file was removedllvm/lib/CodeGen/GCStrategy.cpp
The file was modifiedllvm/lib/CodeGen/AsmPrinter/ErlangGCPrinter.cpp
The file was modifiedllvm/lib/CodeGen/CMakeLists.txt
The file was addedllvm/include/llvm/IR/BuiltinGCs.h
The file was modifiedllvm/lib/IR/CMakeLists.txt
The file was removedllvm/include/llvm/CodeGen/BuiltinGCs.h
The file was modifiedllvm/lib/CodeGen/SelectionDAG/StatepointLowering.cpp
The file was addedllvm/lib/IR/BuiltinGCs.cpp
The file was removedllvm/include/llvm/CodeGen/GCStrategy.h
The file was modifiedllvm/include/llvm/CodeGen/LinkAllCodegenComponents.h
The file was modifiedllvm/lib/CodeGen/GCMetadata.cpp
The file was removedllvm/lib/CodeGen/BuiltinGCs.cpp
The file was modifiedllvm/lib/CodeGen/GCRootLowering.cpp
The file was modifiedllvm/lib/CodeGen/AsmPrinter/OcamlGCPrinter.cpp
The file was addedllvm/include/llvm/IR/GCStrategy.h
The file was modifiedllvm/include/llvm/CodeGen/LinkAllAsmWriterComponents.h
Commit 9bf17619750494ee971c66782039d4102d805c07 by llvmgnsyncbot
[gn build] Port d8b37de8a478
The file was modifiedllvm/utils/gn/secondary/llvm/lib/IR/BUILD.gn
The file was modifiedllvm/utils/gn/secondary/llvm/lib/CodeGen/BUILD.gn
Commit 60da33c2d4b2cd744c70259088b2ab89eb858f33 by springerm
[mlir] Support masks in TransferOpReduceRank and TransferReadPermutationLowering

These two patterns allow for more efficient codegen in VectorToSCF.

Differential Revision: https://reviews.llvm.org/D102222
The file was modifiedmlir/lib/Dialect/Vector/VectorTransforms.cpp
The file was modifiedmlir/test/Dialect/Vector/vector-transfer-lowering.mlir
Commit 92f9852fc99b0a18e8d1329341f36f1708343f05 by v.g.vassilev
[clang-repl] Recommit "Land initial infrastructure for incremental parsing"

Original commit message:

  In http://lists.llvm.org/pipermail/llvm-dev/2020-July/143257.html we have
  mentioned our plans to make some of the incremental compilation facilities
  available in llvm mainline.

  This patch proposes a minimal version of a repl, clang-repl, which enables
  interpreter-like interaction for C++. For instance:

  ./bin/clang-repl
  clang-repl> int i = 42;
  clang-repl> extern "C" int printf(const char*,...);
  clang-repl> auto r1 = printf("i=%d\n", i);
  i=42
  clang-repl> quit

  The patch allows very limited functionality, for example, it crashes on invalid
  C++. The design of the proposed patch follows closely the design of cling. The
  idea is to gather feedback and gradually evolve both clang-repl and cling to
  what the community agrees upon.

  The IncrementalParser class is responsible for driving the clang parser and
  codegen and allows the compiler infrastructure to process more than one input.
  Every input adds to the “ever-growing” translation unit. That model is enabled
  by an IncrementalAction which prevents teardown when HandleTranslationUnit.

  The IncrementalExecutor class hides some of the underlying implementation
  details of the concrete JIT infrastructure. It exposes the minimal set of
  functionality required by our incremental compiler/interpreter.

  The Transaction class keeps track of the AST and the LLVM IR for each
  incremental input. That tracking information will be later used to implement
  error recovery.

  The Interpreter class orchestrates the IncrementalParser and the
  IncrementalExecutor to model interpreter-like behavior. It provides the public
  API which can be used (in future) when using the interpreter library.

  Differential revision: https://reviews.llvm.org/D96033
The file was addedclang/lib/Interpreter/IncrementalParser.h
The file was addedclang/test/Interpreter/sanity.c
The file was modifiedclang/test/CMakeLists.txt
The file was addedclang/test/Interpreter/execute.cpp
The file was modifiedclang/test/lit.cfg.py
The file was addedclang/lib/Interpreter/IncrementalExecutor.h
The file was addedclang/tools/clang-repl/CMakeLists.txt
The file was addedclang/unittests/Interpreter/CMakeLists.txt
The file was modifiedclang/lib/CodeGen/CodeGenAction.cpp
The file was modifiedclang/lib/Frontend/FrontendAction.cpp
The file was modifiedclang/tools/CMakeLists.txt
The file was addedclang/include/clang/Interpreter/Interpreter.h
The file was addedclang/lib/Interpreter/Interpreter.cpp
The file was modifiedclang/unittests/CMakeLists.txt
The file was modifiedclang/include/clang/CodeGen/CodeGenAction.h
The file was addedclang/include/clang/Interpreter/Transaction.h
The file was addedclang/tools/clang-repl/ClangRepl.cpp
The file was addedclang/lib/Interpreter/IncrementalParser.cpp
The file was addedclang/lib/Interpreter/IncrementalExecutor.cpp
The file was modifiedclang/unittests/CodeGen/CMakeLists.txt
The file was removedclang/unittests/CodeGen/IncrementalProcessingTest.cpp
The file was modifiedclang/lib/CMakeLists.txt
The file was addedclang/lib/Interpreter/CMakeLists.txt
The file was modifiedclang/include/clang/Frontend/FrontendAction.h
The file was addedclang/unittests/Interpreter/IncrementalProcessingTest.cpp
The file was addedclang/unittests/Interpreter/InterpreterTest.cpp
Commit 3f4c5185926ad2a07a642b8b0b7a4accffeb7e36 by v.g.vassilev
[clang-repl] Add exhaustive list of libInterpreter dependencies.

This patch should appease the bots building with -DBUILD_SHARED_LIBS=On,
resolving the regression introduced in 92f9852fc99b.
The file was modifiedclang/lib/Interpreter/CMakeLists.txt
Commit 6045cb89e5e8223eea4d7f9c3a3e0d8d25ff909f by sguelton
Use an allow list on reserved macro identifiers

The allow list is based on various official sources (see in-code comment).

This fixes https://bugs.llvm.org/show_bug.cgi?id=50248

Differential Revision: https://reviews.llvm.org/D102168
The file was modifiedclang/lib/Lex/PPDirectives.cpp
The file was modifiedclang/test/Preprocessor/macro-reserved.c
Commit 12537ab77227db8f2b42e6172b24313d8f442e97 by sepavloff
[FPEnv][X86] Implement lowering of llvm.set.rounding

Differential Revision: https://reviews.llvm.org/D74730
The file was modifiedllvm/lib/Target/X86/X86InstrFPStack.td
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.h
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was addedllvm/test/CodeGen/X86/fpenv.ll
Commit 107d19eb017ff6734986af077eb2e9f6600114a9 by jingu.kang
Revert "[SimpleLoopUnswitch] Port partially invariant unswitch from LoopUnswitch to SimpleLoopUnswitch"

This reverts commit 88b259c01463c08ac2575b4432c07ea7751946b5.

It needs to fix below bugs.

https://bugs.llvm.org/show_bug.cgi?id=50279
https://bugs.llvm.org/show_bug.cgi?id=50302
The file was modifiedllvm/test/Transforms/SimpleLoopUnswitch/partial-unswitch.ll
The file was modifiedllvm/lib/Transforms/Scalar/SimpleLoopUnswitch.cpp
The file was removedllvm/test/Transforms/SimpleLoopUnswitch/partial-unswitch-mssa-threshold.ll
The file was removedllvm/test/Transforms/SimpleLoopUnswitch/partial-unswitch-update-memoryssa.ll
Commit afee09751d2d744a753ef4d3e8d83857dcd0f682 by Jason Molenda
[NFC] Add GetInferiorAddrSize method, unify code to compute

MachProcess.mm has a sequence to get the address size in
the inferior in three places; and I'm about to add a fourth
in a future patch.  Not a fan.
The file was modifiedlldb/tools/debugserver/source/MacOSX/MachProcess.mm
The file was modifiedlldb/tools/debugserver/source/MacOSX/MachProcess.h
Commit 8a86787847d92c0b428171d9de748c1cf91b3159 by kbessonova
[libcxx] NFC. Fix misprint unodered -> unordered

Differential Revision: https://reviews.llvm.org/D102354
The file was modifiedlibcxx/include/__hash_table
Commit b2186a69c169c7e39c2a769ba859f656aa4cef1b by v.g.vassilev
[clang-repl] Add final set of missing library dependencies.
The file was modifiedclang/tools/clang-repl/CMakeLists.txt
Commit fd184c062c1a1b4727ddf0452ebab11fb8834880 by bruno.cardoso
[TSAN] Honor failure memory orders in AtomicCAS

LLVM has lifted strong requirements for CAS failure memory orders in 431e3138a and 819e0d105e84.

Add support for honoring them in `AtomicCAS`.

https://github.com/google/sanitizers/issues/970

Differential Revision: https://reviews.llvm.org/D99434
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_interface_atomic.cpp
The file was modifiedllvm/test/Instrumentation/ThreadSanitizer/atomic.ll
The file was addedcompiler-rt/test/tsan/compare_exchange.cpp
Commit e2759f110b6e9a33db449ebdf428480f46db67b8 by flo
[SCEV] Apply guards to max with non-unitary steps.

We already apply loop-guards when computing the maximum with unitary
steps. This extends the code to also do so when dealing with non-unitary
steps.

This allows us to infer a tighter maximum in some cases.

Reviewed By: nikic

Differential Revision: https://reviews.llvm.org/D102267
The file was modifiedllvm/test/Analysis/ScalarEvolution/max-backedge-taken-count-guard-info.ll
The file was modifiedllvm/lib/Analysis/ScalarEvolution.cpp
Commit 39e4676ca798d9aba58823515ac9d48eb64863be by nemanja.i.ibm
[PowerPC] Provide doubleword vector predicate form comparisons on Power7

There are two reasons this shouldn't be restricted to Power8 and up:
1. For XL compatibility
2. Because clang will expand comparison operators to these intrinsics*

*Without this patch, the following causes a selection error:

int test(vector signed long a, vector signed long b) {
  return a < b;
}

This patch provides the handling for the intrinsics in the back
end and removes the Power8 guards from the predicate functions
(vec_{all|any}_{eq|ne|gt|ge|lt|le}).
The file was modifiedclang/test/CodeGen/builtins-ppc-vsx.c
The file was addedllvm/test/CodeGen/PowerPC/vec_cmpd_p7.ll
The file was modifiedclang/test/CodeGen/builtins-ppc-p8vector.c
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrVSX.td
The file was modifiedclang/lib/Headers/altivec.h
The file was modifiedllvm/lib/Target/PowerPC/PPCISelLowering.cpp
Commit 0326d4667ab116588e6f987ceed151e709d263c2 by david.spickett
[Utils] Use whoami to get username for arcanist warning message

959eec1fddc83c90c208789f20cb6573b2a20642 changed the message
to show the local username with "$user" but this is not always set.

Some systems will have USER/USERNAME/LOGNAME, so just use "whoami"
instead.
The file was modifiedutils/arcanist/clang-format.sh
Commit 4624412367f9b591fe90ecec8feed7209cd222ac by v.g.vassilev
[clang-repl] Fix ClangReplInterpreterTests unittest dependency.
The file was modifiedclang/unittests/Interpreter/CMakeLists.txt
Commit 3eaf2358556d377ae5a8f2c942d92af1c1521cfc by flo
[Passes] Use MemorySSA for LICM during LTO.

Split off from D102345 to commit this separately from other changes in
the patch. This aligns the behavior of the new PM with the legacy PM
for LTO, with respect to running LICM.

Together with the remaining changes in D102345, this fixes new PM
regressions where we fail to vectorize loops that are vectorized with
the legacy PM.
The file was modifiedllvm/test/Other/new-pm-lto-defaults.ll
The file was modifiedllvm/lib/Passes/PassBuilder.cpp
Commit 797e580db9837839ab11711733b5de52249f187c by fraser
[RISCV][NFC] Simplify test run lines

Several tests had -verify-machineinstrs twice, and several tests were
explicitly specifying the default FileCheck prefix of CHECK.
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/extractelt-i1.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-splat.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-int.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-setcc.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-conv.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-load-fp.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/stepvector.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-splat.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-load-store.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-fp.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-load-int.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-splat.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-logic.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-vrgather.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-vrgather.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-vnsra-vnsrl.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-exttrunc.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop.ll
Commit 860b37526ae188d02e2dbf68a006eb26f936b5eb by flo
[Passes] Run GlobalsAA before LICM during LTO in new PM.

This patch adjusts the LTO pipeline in the new PM to run GlobalsAA
before LICM to match the legacy PM.

This fixes a regression where the new PM failed to vectorize loops that
require hoisting/sinking by LICM depending on GlobalsAA info.

Reviewed By: aeubanks

Differential Revision: https://reviews.llvm.org/D102345
The file was modifiedllvm/test/Transforms/PhaseOrdering/AArch64/globals-aa-required-for-vectorization.ll
The file was modifiedllvm/test/Other/new-pm-lto-defaults.ll
The file was modifiedllvm/lib/Passes/PassBuilder.cpp
Commit ffc157ea825f75c7b143fdaf23283194c5d829cf by flo
[Passes] Use regex to match GlobalsAA line in test.

On some platforms/compiler combinations, it appears the output is
slightly different. Update the test to use a regex, as is done at other
places in the new-pm-*default.ll tests to address buildbot failures.
The file was modifiedllvm/test/Other/new-pm-lto-defaults.ll
Commit 9dfc4ac41cedd8d7a79d7954b5a54ab33cfca05d by llvm-dev
[X86] VZeroUpperInserter::insertVZeroUpper - avoid DebugLoc creation by embedding in the BuildMI calls. NFCI.

Try to pass DebugLoc by const-ref to avoid costly TrackingMDNodeRef copies.
The file was modifiedllvm/lib/Target/X86/X86VZeroUpper.cpp
Commit 4956655640c19190264b07740499e56ccb33c61f by llvm-dev
[X86] X86InstrInfo.cpp - try to pass DebugLoc by const-ref to avoid costly TrackingMDNodeRef copies. NFCI.
The file was modifiedllvm/lib/Target/X86/X86InstrInfo.cpp
Commit ba0ec1be2916eae1798ad4c56480f471a65f7ce9 by llvm-dev
[X86] X86ExpandPseudo.cpp - try to pass DebugLoc by const-ref to avoid costly TrackingMDNodeRef copies. NFCI.
The file was modifiedllvm/lib/Target/X86/X86ExpandPseudo.cpp
Commit bdada7546e6b4a189a22c7ba9ce2d1b507b9c22e by flo
[VPlan] Adjust assert in splitBlock to allow splitting at end.

SplitAt should only be dereferenced in the assert if it does not point
to the end of the block. This fixes a crash in the added test case.
The file was modifiedllvm/test/Transforms/LoopVectorize/first-order-recurrence-sink-replicate-region.ll
The file was modifiedllvm/lib/Transforms/Vectorize/VPlan.cpp
Commit 15051f0b4a2e0a0af9da7cd5e5cfaabb9f6aaa3d by stefanp
[PowerPC] Handle inline assembly clobber of link regsiter

This patch adds the handling of clobbers of the link register LR for inline
assembly.

This patch is to fix:
https://bugs.llvm.org/show_bug.cgi?id=50147

Reviewed By: nemanjai, #powerpc

Differential Revision: https://reviews.llvm.org/D101657
The file was addedllvm/test/CodeGen/PowerPC/ppc64-inlineasm-clobber.ll
The file was modifiedllvm/lib/Target/PowerPC/PPCISelLowering.h
The file was modifiedllvm/lib/Target/PowerPC/PPCRegisterInfo.td
The file was modifiedllvm/lib/Target/PowerPC/PPCISelLowering.cpp
Commit e07753c8814dba100dcae44e2b47947b340ad0e8 by jubnzv
[clang-tidy] Fix test that requires Windows platofrm

This commit fixes the cppcoreguidelines-pro-type-vararg test when it
runs on a Windows host, but the toolchain is targeted a non-Windows
platform.

Reviewed By: njames93

Differential Revision: https://reviews.llvm.org/D102337
The file was modifiedclang-tools-extra/test/clang-tidy/checkers/cppcoreguidelines-pro-type-vararg-ms.cpp
Commit 9310840cc249ae1aec427948fb09b8056e7094c0 by thakis
[gn build] (manually) port 92f9852fc99b, clang-repl
The file was addedllvm/utils/gn/secondary/clang/unittests/Interpreter/BUILD.gn
The file was addedllvm/utils/gn/secondary/clang/lib/Interpreter/BUILD.gn
The file was modifiedllvm/utils/gn/secondary/clang/unittests/BUILD.gn
The file was modifiedllvm/utils/gn/secondary/clang/unittests/CodeGen/BUILD.gn
The file was modifiedllvm/utils/gn/secondary/clang/test/BUILD.gn
The file was addedllvm/utils/gn/secondary/clang/tools/clang-repl/BUILD.gn
Commit bf068e1077a44fcb52fdf2aeb8f03f80517b64ab by springerm
[mlir] Do not use pass labels in unrolled ProgressiveVectorToSCF

Do not rely on pass labels to detect if the pattern was already applied in the past (which allows for more some extra optimizations to avoid extra InsertOps and ExtractOps). Instead, check if these optimizations can be applied on-the-fly.

This also fixes a bug, where vector.insert and vector.extract ops sometimes disappeared in the middle of the pass because they get folded away, but the next application of the pattern expected them to be there.

Differential Revision: https://reviews.llvm.org/D102206
The file was modifiedmlir/lib/Conversion/VectorToSCF/ProgressiveVectorToSCF.cpp
The file was modifiedmlir/test/Integration/Dialect/Vector/CPU/test-transfer-read-3d.mlir
Commit b1509d067e426bb8451bba789e34c4e65a168aba by Jinsong Ji
[AIX] XFAIL CodeGen/Generic/externally_available.ll

    Globals with “available_externally” linkage should never be emitted into the
    object file corresponding to the LLVM module.

    However, AIX system assembler default print error for undefined reference .
    so AIX chose to emit the available externally symbols into .s,
    so that users won't run into errors in situations like:

    clang -target powerpc-ibm-aix -xc -<<<$'extern inline
    __attribute__((__gnu_inline__)) void foo() {}\nvoid bar() { foo(); }' -O
    -Xclang -disable-llvm-passes

Reviewed By: hubert.reinterpretcast

Differential Revision: https://reviews.llvm.org/D102377
The file was modifiedllvm/test/CodeGen/Generic/externally_available.ll
Commit 4dea3487315ed2870134c303c550152965a0580b by kparzysz
Add entry about Hexagon V68 support to the release notes
The file was modifiedllvm/docs/ReleaseNotes.rst
Commit 92260d7a186425510e96b7036b467a6889d08d97 by oliver.stannard
Revert "[CMake][ELF] Add -fno-semantic-interposition and -Bsymbolic-functions"

This reverts commit 3bf1acab5b454ad7fb2074b34663108b53620695.

This is causing the test `gcov-shared-flush.c' to fail on the 2-stage
aarch64 buildbots (https://lab.llvm.org/buildbot/#/builders/7/builds/2720).
The file was modifiedllvm/tools/llvm-shlib/CMakeLists.txt
The file was modifiedclang/tools/clang-shlib/CMakeLists.txt
The file was modifiedllvm/cmake/modules/HandleLLVMOptions.cmake
Commit 2b20dee59bc8829182235964b02777d54f53bb62 by kparzysz
Fix section title underlining in the release notes
The file was modifiedllvm/docs/ReleaseNotes.rst
Commit d020dd2b21be85b60f935980ab8e93caee7a661a by springerm
[mlir] Migrate vector-to-loops.mlir to ProgressiveVectorToSCF

Create a copy of vector-to-loops.mlir and adapt the test for
ProgressiveVectorToSCF. Fix a small bug in getExtractOp() triggered by
this test.

Differential Revision: https://reviews.llvm.org/D102388
The file was modifiedmlir/lib/Conversion/VectorToSCF/ProgressiveVectorToSCF.cpp
The file was addedmlir/test/Conversion/VectorToSCF/progressive-vector-to-loops.mlir
Commit 395607af3cb80f25ee05420ea5ae0ad0be948533 by nikita.ppv
Reapply [ConstantFold] Fold more operations to poison

This was reverted to mitigate mitigate miscompiles caused by
the logical and/or to bitwise and/or fold. Reapply it now that
the underlying issue has been fixed by D101191.

-----

This patch folds more operations to poison.

Alive2 proof: https://alive2.llvm.org/ce/z/mxcb9G (it does not contain tests about div/rem because they fold to poison when raising UB)

Reviewed By: nikic

Differential Revision: https://reviews.llvm.org/D92270
The file was modifiedllvm/test/Transforms/InstSimplify/ConstProp/vector-undef-elts.ll
The file was modifiedllvm/test/Transforms/InstSimplify/div.ll
The file was modifiedllvm/test/Transforms/VectorCombine/X86/insert-binop-with-constant.ll
The file was modifiedllvm/unittests/IR/ConstantsTest.cpp
The file was modifiedclang/test/Frontend/fixed_point_unary.c
The file was modifiedllvm/test/Transforms/InstSimplify/ConstProp/InsertElement.ll
The file was modifiedllvm/test/Transforms/InstSimplify/ConstProp/poison.ll
The file was modifiedllvm/test/Transforms/InstSimplify/ConstProp/cast.ll
The file was modifiedllvm/test/Transforms/SROA/phi-gep.ll
The file was modifiedllvm/test/Transforms/VectorCombine/X86/insert-binop.ll
The file was modifiedllvm/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-after-truncation-variant-a.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fold-binop-select.ll
The file was modifiedllvm/test/Transforms/InstCombine/shift-add.ll
The file was modifiedllvm/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-after-truncation-variant-d.ll
The file was modifiedllvm/test/Transforms/SROA/select-gep.ll
The file was modifiedllvm/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-variant-e.ll
The file was modifiedllvm/test/Transforms/InstCombine/icmp.ll
The file was modifiedllvm/test/Transforms/InstSimplify/ConstProp/InsertElement-inseltpoison.ll
The file was modifiedllvm/test/Transforms/VectorCombine/X86/insert-binop-inseltpoison.ll
The file was modifiedllvm/test/Transforms/InstSimplify/undef.ll
The file was modifiedllvm/test/Transforms/InstCombine/canonicalize-shl-lshr-to-masking.ll
The file was modifiedllvm/test/Transforms/InstCombine/canonicalize-ashr-shl-to-masking.ll
The file was modifiedllvm/test/Transforms/InstSimplify/ConstProp/vscale.ll
The file was modifiedllvm/test/Transforms/InstCombine/shift-add-inseltpoison.ll
The file was modifiedllvm/test/Transforms/InstCombine/canonicalize-lshr-shl-to-masking.ll
The file was modifiedllvm/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-variant-d.ll
The file was modifiedllvm/test/Transforms/InstCombine/apint-shift.ll
The file was modifiedllvm/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-after-truncation-variant-b.ll
The file was modifiedllvm/test/Transforms/InstSimplify/ConstProp/vector-undef-elts-inseltpoison.ll
The file was modifiedllvm/test/Transforms/InstSimplify/ConstProp/vscale-inseltpoison.ll
The file was modifiedllvm/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-after-truncation-variant-c.ll
The file was modifiedllvm/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-after-truncation-variant-e.ll
The file was modifiedllvm/test/Transforms/InstSimplify/rem.ll
The file was modifiedllvm/test/Transforms/InstSimplify/ConstProp/shift.ll
The file was modifiedllvm/test/Transforms/InstCombine/select-of-bittest.ll
The file was modifiedllvm/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-variant-a.ll
The file was modifiedllvm/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-variant-b.ll
The file was modifiedllvm/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-variant-c.ll
The file was modifiedllvm/lib/IR/ConstantFold.cpp
Commit fe9101c3d8db4d054aade400efae45857f0840da by Paul C. Anagnostopoulos
[TableGen] Make the NUL character invalid in .td files

Now uses tr instead of sed.

Differential Revision: https://reviews.llvm.org/D102254
The file was addedllvm/test/TableGen/nul-char.td
The file was modifiedllvm/lib/TableGen/TGLexer.cpp
Commit f358c372094599bf2a9246a0d2145cd949b4c62d by gysit
[mlir][linalg] Remove IndexedGenericOp support from DropUnitDims...

after introducing the IndexedGenericOp to GenericOp canonicalization (https://reviews.llvm.org/D101612).

Differential Revision: https://reviews.llvm.org/D102235
The file was modifiedmlir/test/Dialect/Linalg/drop-unit-extent-dims.mlir
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/DropUnitDims.cpp
Commit 0f24163870e1a633c1d79377fdd188fe03769dd8 by springerm
[mlir] Replace vector-to-scf with progressive-vector-to-scf

Depends On D102388

Reviewed By: nicolasvasilache

Differential Revision: https://reviews.llvm.org/D102101
The file was modifiedmlir/test/Integration/Dialect/Vector/CPU/test-transfer-read-3d.mlir
The file was modifiedmlir/test/Conversion/VectorToSCF/unrolled-vector-to-loops.mlir
The file was modifiedmlir/test/Integration/Dialect/Vector/CPU/test-transfer-read-2d.mlir
The file was modifiedmlir/test/Integration/Dialect/Vector/CPU/test-transfer-to-loops.mlir
The file was removedmlir/test/Conversion/VectorToSCF/progressive-vector-to-loops.mlir
The file was modifiedmlir/lib/Conversion/VectorToSCF/VectorToSCF.cpp
The file was modifiedmlir/test/Integration/Dialect/Vector/CPU/test-transfer-read-1d.mlir
The file was removedmlir/lib/Conversion/VectorToSCF/ProgressiveVectorToSCF.cpp
The file was modifiedmlir/test/lib/Transforms/TestVectorTransforms.cpp
The file was modifiedmlir/test/Conversion/VectorToSCF/vector-to-loops.mlir
The file was modifiedmlir/test/Integration/Dialect/Vector/CPU/test-transfer-read.mlir
The file was modifiedmlir/lib/Conversion/VectorToSCF/CMakeLists.txt
The file was removedmlir/include/mlir/Conversion/VectorToSCF/ProgressiveVectorToSCF.h
The file was modifiedmlir/include/mlir/Conversion/VectorToSCF/VectorToSCF.h
Commit cf194da1bbf79d392688dba0c74875829e9873f2 by gysit
[mlir][linalg] Remove IndexedGenericOp support from FusionOnTensors...

after introducing the IndexedGenericOp to GenericOp canonicalization (https://reviews.llvm.org/D101612).

Differential Revision: https://reviews.llvm.org/D102163
The file was modifiedmlir/test/Dialect/Linalg/reshape_linearization_fusion.mlir
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/FusionOnTensors.cpp
The file was modifiedmlir/test/Dialect/Linalg/fusion-tensor.mlir
The file was modifiedmlir/include/mlir/Dialect/Linalg/Transforms/Transforms.h
The file was modifiedmlir/test/Dialect/Linalg/reshape_fusion.mlir
Commit b1a074951ff78bf06a2d944c01ca0a0fcd63dd33 by bradley.smith
[AArch64][SVE] Fix missed immediate selection due to mishandling of signedness

The complex selection pattern for add/sub shifted immediates is
incorrect in it's handling of incoming constant values, in that it
does not properly anticipate the values to be signed extended to
32-bits.

Co-authored-by: Graham Hunter <graham.hunter@arm.com>

Differential Revision: https://reviews.llvm.org/D101833
The file was modifiedllvm/test/CodeGen/AArch64/sve-int-imm.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
Commit 8fa168fc50ba4f63b79773c947ef5b3e43d5c02f by zarko
Parse vector bool when stdbool.h and altivec.h are included

Currently when including stdbool.h and altivec.h declaration of `vector bool` leads to
errors due to `bool` being expanded to '_Bool`. This patch allows the parser
to recognize `_Bool`.

Reviewed By: hubert.reinterpretcast, Everybody0523

Differential Revision: https://reviews.llvm.org/D102064
The file was addedclang/test/Parser/altivec-zvector-bool.c
The file was modifiedclang/lib/Parse/ParseDecl.cpp
The file was modifiedclang/lib/Parse/Parser.cpp
The file was modifiedclang/include/clang/Parse/Parser.h
Commit 6a67e05a26eb5f58665bd6d063b9f389e7dd28a7 by enye.shi
[HIP] Add __builtin_amdgcn_groupstaticsize

Differential Revision: https://reviews.llvm.org/D102403
The file was modifiedclang/include/clang/Basic/BuiltinsAMDGPU.def
The file was modifiedclang/test/CodeGenOpenCL/builtins-amdgcn-ci.cl
The file was modifiedclang/test/CodeGenOpenCL/builtins-amdgcn-gfx9.cl
The file was modifiedclang/test/CodeGenOpenCL/builtins-amdgcn-gfx10.cl
The file was modifiedclang/test/CodeGenOpenCL/builtins-amdgcn-vi.cl
Commit 8f98356bb53dca07a86bf098556d446e0d5af6fe by Stanislav.Mekhanoshin
[AMDGPU] Only allow global fp atomics with unsafe option

Previously we were allowing to use FP atomics without
-amdgpu-unsafe-fp-atomics option if a scope is less then
system. This is not safe just as well if we have UC memory.

This change only allows global and flat FP atomics with
the unsafe option. Consequentially that makes a check for
denorm mode redundant since we skip it with the unsafe
option and do not have a way to produce these instructions
without it anyway.

Differential Revision: https://reviews.llvm.org/D102347
The file was modifiedllvm/lib/Target/AMDGPU/SIISelLowering.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/fp64-atomics-gfx90a.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/global-atomics-fp.ll
Commit 34ed3e63378e34f93ada56a19cebc68cf1498092 by llvm-project
[OpenMP] Test unified shared memory tests only on systems that support it.

Add a `REQUIRES: unified_shared_memory` option to tests that use `#pragma omp requires unified_shared_memory`.

For CUDA, the feature tag is derived from LIBOMPTARGET_DEP_CUDA_ARCH which itself is derived using [[ https://cmake.org/cmake/help/latest/module/FindCUDA.html#commands | cuda_select_nvcc_arch_flags ]]. The latter determines which compute capability the GPU in the system supports. To ensure that this is the CUDA arch being used, we could also set the `-Xopenmp-target -march=` flag.
In the absence of an NVIDIA GPU, LIBOMPTARGET_DEP_CUDA_ARCH will be 35. That is, in that case we are assuming unified_shared_memory is not available. CUDA plugin testing could be disabled entirely in this case, but this currently depends on `LIBOMPTARGET_CAN_LINK_LIBCUDA OR LIBOMPTARGET_FORCE_DLOPEN_LIBCUDA`, not on whether the hardware is actually available.

For all other targets, nothing changes and we are assuming unified shared memory is available. This might need refinement if not the case.

This tries to fix the [[ http://meinersbur.de:8011/#/builders/143 | OpenMP Offloading Buildbot ]] that, although brand-new, only has a Pascal-generation (sm_61) GPU installed. Hence, tests that require unified shared memory are currently failing. I wish I had known in advance.

Reviewed By: protze.joachim, tianshilei1992

Differential Revision: https://reviews.llvm.org/D101498
The file was modifiedopenmp/libomptarget/test/lit.site.cfg.in
The file was modifiedopenmp/libomptarget/test/mapping/present/unified_shared_memory.c
The file was modifiedopenmp/libomptarget/test/lit.cfg
The file was modifiedopenmp/libomptarget/test/unified_shared_memory/close_manual.c
The file was modifiedopenmp/libomptarget/test/unified_shared_memory/close_modifier.c
The file was modifiedopenmp/libomptarget/test/unified_shared_memory/close_enter_exit.c
The file was modifiedopenmp/libomptarget/test/unified_shared_memory/shared_update.c
Commit 2ed7db0d206b6af2fffa4cb2704264b76ca61266 by joe.ellis
[InstSimplify] Remove redundant {insert,extract}_vector intrinsic chains

This commit removes some redundant {insert,extract}_vector intrinsic
chains by implementing the following patterns as instsimplifies:

   (insert_vector _, (extract_vector X, 0), 0) -> X
   (extract_vector (insert_vector _, X, 0), 0) -> X

Reviewed By: peterwaller-arm

Differential Revision: https://reviews.llvm.org/D101986
The file was modifiedclang/test/CodeGen/attr-arm-sve-vector-bits-call.c
The file was modifiedllvm/lib/Analysis/InstructionSimplify.cpp
The file was addedllvm/test/Transforms/InstSimplify/insert-vector.ll
The file was modifiedclang/test/CodeGen/attr-arm-sve-vector-bits-cast.c
The file was addedllvm/test/Transforms/InstSimplify/extract-vector.ll
Commit 3f2891db6dd5684ee743055c0e86d0d3dd66c90b by jpienaar
[mlir] Add python test for shape dialect

Add basic test for shape.const_shape op as start.

Differential Revision: https://reviews.llvm.org/D102341
The file was addedmlir/test/python/dialects/shape.py
Commit b049870d3b47a93b0c53f3ad69b11c4731b39d7f by jonathanchesterfield
[libomptarget][amdgpu] Convert an assert to print and offload_fail

[libomptarget][amdgpu] Convert an assert to print and offload_fail

The kernel launched is supposed to be present in the binary, but a not yet
diagnosed bug means it is missing for some of the qmcpack test cases. Changing
from assert to print and offload_fail should help diagnose that and similar bugs.

Reviewed By: jdoerfert

Differential Revision: https://reviews.llvm.org/D102378
The file was modifiedopenmp/libomptarget/plugins/amdgpu/src/rtl.cpp
Commit 10de21720989166a6b51cbf48b21efacbb913f23 by jonathanchesterfield
[libomptarget][amdgpu] Fix truncation error for partial wavefront

[libomptarget][amdgpu] Fix truncation error for partial wavefront

The partial barrier implementation involves one wavefront resetting and N-1
waiting. This change future proofs against launching with a number of threads
that is not a multiple of the wavefront size.

Reviewed By: jdoerfert

Differential Revision: https://reviews.llvm.org/D102407
The file was modifiedopenmp/libomptarget/deviceRTLs/amdgcn/src/target_impl.hip
Commit 9469ff15b77905245e26fe7f166fc127d813a0c0 by lei
[PowerPC] Add clang option -m[no-]prefixed

Add user-facing front end option to turn off power10 prefixed instructions.

Reviewed By: nemanjai

Differential Revision: https://reviews.llvm.org/D102191
The file was modifiedclang/lib/Basic/Targets/PPC.h
The file was addedclang/test/Driver/ppc-prefixed.cpp
The file was modifiedclang/lib/Basic/Targets/PPC.cpp
The file was modifiedclang/include/clang/Driver/Options.td
Commit 98e4fd0701d0c65229db876ce338c723231d8cb4 by zoecarver
[libcxx][ranges] Fix `ranges::empty` when begin, end, and empty members are provided.

Before this commit, we'd get a compilation error because the operator() overload was ambiguous.

Differential Revision: https://reviews.llvm.org/D102263
The file was modifiedlibcxx/test/std/ranges/range.access/range.prim/empty.pass.cpp
The file was modifiedlibcxx/include/__ranges/empty.h
Commit 7c2afd5899df876eaf5ffb485194dc58e92daf89 by Duncan P. N. Exon Smith
Modules: Remove ModuleLoader::OtherUncachedFailure, NFC

5cca622310c10fdf6f921b6cce26f91d9f14c762 refactored
CompilerInstance::loadModule, splitting out
findOrCompileModuleAndReadAST, but was careful to avoid making any
functional changes. It added ModuleLoader::OtherUncachedFailure to
facilitate this and left behind FIXMEs asking why certain failures
weren't cached.

After a closer look, I think we can just remove this and simplify the
code. This changes the behaviour of the following (simplified) code from
CompilerInstance::loadModule, causing a failure to be cached more often:

```
  if (auto MaybeModule = MM.getCachedModuleLoad(*Path[0].first))
    return *MaybeModule;
  if (ModuleName == getLangOpts().CurrentModule)
    return MM.cacheModuleLoad(PP.lookupModule(...));
  ModuleLoadResult Result = findOrCompileModuleAndReadAST(...);
  if (Result.isNormal()) // This will be 'true' more often.
    return MM.cacheModuleLoad(..., Module);
  return Result;
```

`MM` here is a ModuleMap owned by the Preprocessor. Here are the cases
where `findOrCompileModuleAndReadAST` starts returning a "normal" failed
result:
- Emitted `diag::err_module_not_found`, where there's no module map
  found.
- Emitted `diag::err_module_build_disabled`, where implicitly building
  modules is disabled.
- Emitted `diag::err_module_cycle`, which detects module cycles in the
  implicit modules build system.
- Emitted `diag::err_module_not_built`, which avoids building a module
  in this CompilerInstance if another one tried and failed already.
- `compileModuleAndReadAST()` was called and failed to build.

The four errors are all fatal, and last item also reports a fatal error,
so it this extra caching has no functionality change... but even if it
did, it seems fine to cache these failed results within a ModuleMap
instance (note that each CompilerInstance has its own Preprocessor and
ModuleMap).

Differential Revision: https://reviews.llvm.org/D101667
The file was modifiedclang/lib/Frontend/CompilerInstance.cpp
The file was modifiedclang/include/clang/Lex/ModuleLoader.h
Commit 7f607ac6af0e2ee8a7d721d3ba427536deffcd3f by zoecarver
[pstl] Use logical operator for loop condition in tests

Fix a probable typo in two PSTL tests that causes warnings with GCC.

Patch by Jonathan Wakely (jwakely).

Reviewed By: zoecarver

Differential Revision: https://reviews.llvm.org/D102327
The file was modifiedpstl/test/std/algorithms/alg.nonmodifying/search_n.pass.cpp
The file was modifiedpstl/test/std/algorithms/alg.nonmodifying/find_end.pass.cpp
Commit 45212dec01b9be90596d8d6fa7586ce8c84e2622 by vsavchenko
[analyzer][solver] Prevent use of a null state

rdar://77686137

Differential Revision: https://reviews.llvm.org/D102240
The file was modifiedclang/lib/StaticAnalyzer/Core/RangeConstraintManager.cpp
The file was addedclang/test/Analysis/PR50268.c
Commit cd0eeb52ad37d8f55407c548f93f42a0d5b2d08b by weiwei.li1
[mlir][spirv] Define spv.ImageQuerySize operation

Support OpImageQuerySize in spirv dialect

co-authored-by: Alan Liu <alanliu.yf@gmail.com>

Reviewed By: antiagainst

Differential Revision: https://reviews.llvm.org/D102029
The file was modifiedmlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td
The file was modifiedmlir/test/Target/SPIRV/image-ops.mlir
The file was modifiedmlir/lib/Dialect/SPIRV/IR/SPIRVOps.cpp
The file was modifiedmlir/test/Dialect/SPIRV/IR/image-ops.mlir
The file was modifiedmlir/include/mlir/Dialect/SPIRV/IR/SPIRVImageOps.td
Commit 23e9146fba298d38142337b615e17067fb8ccb91 by Duncan P. N. Exon Smith
Modules: Rename ModuleBuildFailed => DisableGeneratingGlobalModuleIndex, NFC

Rename CompilerInstance's ModuleBuildFailed field to
DisableGeneratingGlobalModuleIndex, which more precisely describes its
role. Otherwise, it's hard to suss out how it's different from
ModuleLoader::HadFatalFailure, and what sort of code simplifications are
safe.

Differential Revision: https://reviews.llvm.org/D101670
The file was modifiedclang/lib/Frontend/CompilerInstance.cpp
The file was modifiedclang/include/clang/Frontend/CompilerInstance.h
Commit ce12b52de2fb3f319ff18effc4ea9ff4d369f328 by Jonas Devlieghere
[lldb] Fixup more code addresses

The Swift async task pointers are signed on arm64e and we need to fixup
the addresses in the CFA and DWARF expressions.
The file was modifiedlldb/source/Expression/DWARFExpression.cpp
The file was modifiedlldb/source/Target/RegisterContextUnwind.cpp
Commit f93e9c12bf482dbfe3d4d00fcf8bbc251500dd99 by Jonas Devlieghere
[lldb] Fixup indirect symbols as they are signed.

This fixes a bunch of test failures in Apple Silicon (arm64e).
The file was modifiedlldb/source/Target/Process.cpp
Commit 1011d4ed60d9d32d53e20cbe72e47c9eecb84f49 by david.green
[ARM] Constrain CMPZ shift combine to a single use

We currently prefer t2CMPrs over t2CMPri when the node contains a shift.
This can introduce more nodes if the shift has multiple uses though, as
value from the shift will be needed anyway, and in the case of a t2CMPri
compared with zero will more readily be removed entirely.

Differential Revision: https://reviews.llvm.org/D101688
The file was modifiedllvm/test/CodeGen/Thumb2/mve-vldst4.ll
The file was modifiedllvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
The file was modifiedllvm/lib/Target/ARM/ARMInstrThumb2.td
The file was modifiedllvm/test/CodeGen/Thumb2/mve-postinc-lsr.ll
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/while-loops.ll
The file was modifiedllvm/test/CodeGen/Thumb2/mve-float32regloops.ll
Commit 70aa4623de9fe2f609eab8969d7ef76b4c80084b by lebedev.ri
[NFC][Clang][Codegen] Add tests with wrong attributes on this/return of thunks

From https://reviews.llvm.org/D100388
The file was addedclang/test/CodeGenCXX/thunk-wrong-this.cpp
The file was addedclang/test/CodeGenCXX/thunk-wrong-return-type.cpp
Commit a624cec56d4bf61c1f3cb7daf2d27dac59c56fa4 by lebedev.ri
[Clang][Codegen] Do not annotate thunk's this/return types with align/deref/nonnull attrs

As it was discovered in post-commit feedback
for 0aa0458f1429372038ca6a4edc7e94c96cd9a753,
we handle thunks incorrectly, and end up annotating
their this/return with attributes that are valid
for their callees, not for thunks themselves.

While it would be good to fix this properly,
and keep annotating them on thunks,
i've tried doing that in https://reviews.llvm.org/D100388
with little success, and the patch is stuck for a month now.

So for now, as a stopgap measure, subj.
The file was modifiedclang/test/CodeGenCXX/microsoft-abi-structors.cpp
The file was modifiedclang/lib/CodeGen/MicrosoftCXXABI.cpp
The file was modifiedclang/test/CodeGenCXX/thunks-ehspec.cpp
The file was modifiedclang/lib/CodeGen/CGBlocks.cpp
The file was modifiedclang/lib/CodeGen/CodeGenModule.cpp
The file was modifiedclang/test/CodeGenCXX/thunk-returning-memptr.cpp
The file was modifiedclang/test/CodeGenCXX/thunks.cpp
The file was modifiedclang/test/CodeGenCXX/microsoft-abi-thunks.cpp
The file was modifiedclang/lib/CodeGen/CGVTables.cpp
The file was modifiedclang/test/CodeGenCXX/constructor-destructor-return-this.cpp
The file was modifiedclang/test/CodeGenCXX/microsoft-abi-byval-thunks.cpp
The file was modifiedclang/lib/CodeGen/CGNonTrivialStruct.cpp
The file was modifiedclang/lib/CodeGen/CGExpr.cpp
The file was modifiedclang/lib/CodeGen/CGBuiltin.cpp
The file was modifiedclang/test/CodeGenCXX/thunk-wrong-this.cpp
The file was modifiedclang/lib/CodeGen/CGCall.cpp
The file was modifiedclang/lib/CodeGen/ItaniumCXXABI.cpp
The file was modifiedclang/lib/CodeGen/CGObjC.cpp
The file was modifiedclang/lib/CodeGen/CodeGenModule.h
The file was modifiedclang/test/CodeGenCXX/thunk-wrong-return-type.cpp
Commit 16d03818412415c56efcd482d18c0cbdf712524c by lebedev.ri
Return "[CGCall] Annotate `this` argument with alignment"

The original change was reverted because it was discovered
that clang mishandles thunks, and they receive wrong
attributes for their this/return types - the ones for the function
they will call, not the ones they have.

While i have tried to fix this in https://reviews.llvm.org/D100388
that patch has been up and stuck for a month now,
with little signs of progress.

So while it will be good to solve this for real,
for now we can simply avoid introducing the bug,
by not annotating this/return for thunks.

This reverts commit 6270b3a1eafaba4279e021418c5a2c5a35abc002,
relanding 0aa0458f1429372038ca6a4edc7e94c96cd9a753.
The file was modifiedclang/test/OpenMP/target_teams_distribute_simd_lastprivate_codegen.cpp
The file was modifiedclang/test/OpenMP/teams_distribute_simd_reduction_codegen.cpp
The file was modifiedclang/test/OpenMP/master_taskloop_simd_in_reduction_codegen.cpp
The file was modifiedclang/test/OpenMP/distribute_parallel_for_codegen.cpp
The file was modifiedclang/test/OpenMP/sections_firstprivate_codegen.cpp
The file was modifiedclang/test/OpenMP/for_linear_codegen.cpp
The file was modifiedclang/test/OpenMP/single_private_codegen.cpp
The file was modifiedclang/test/OpenMP/reduction_compound_op.cpp
The file was modifiedclang/test/OpenMP/distribute_simd_private_codegen.cpp
The file was modifiedclang/test/OpenMP/target_teams_distribute_simd_reduction_codegen.cpp
The file was modifiedclang/test/OpenMP/target_teams_distribute_lastprivate_codegen.cpp
The file was modifiedclang/test/OpenMP/target_teams_distribute_parallel_for_dist_schedule_codegen.cpp
The file was modifiedclang/test/OpenMP/teams_distribute_parallel_for_firstprivate_codegen.cpp
The file was modifiedclang/test/OpenMP/distribute_parallel_for_lastprivate_codegen.cpp
The file was modifiedclang/test/OpenMP/distribute_parallel_for_private_codegen.cpp
The file was modifiedclang/test/OpenMP/task_in_reduction_codegen.cpp
The file was modifiedclang/test/OpenMP/target_teams_distribute_reduction_codegen.cpp
The file was modifiedclang/test/OpenMP/for_reduction_codegen_UDR.cpp
The file was modifiedclang/test/OpenMP/teams_distribute_parallel_for_simd_codegen.cpp
The file was modifiedclang/test/OpenMP/distribute_simd_reduction_codegen.cpp
The file was modifiedclang/test/OpenMP/teams_distribute_simd_codegen.cpp
The file was modifiedclang/test/OpenMP/target_parallel_codegen.cpp
The file was modifiedclang/test/OpenMP/teams_distribute_dist_schedule_codegen.cpp
The file was modifiedclang/test/OpenMP/teams_distribute_parallel_for_simd_lastprivate_codegen.cpp
The file was modifiedclang/test/OpenMP/target_teams_distribute_simd_private_codegen.cpp
The file was modifiedclang/test/utils/update_cc_test_checks/Inputs/basic-cplusplus.cpp.expected
The file was modifiedclang/test/OpenMP/target_teams_distribute_parallel_for_collapse_codegen.cpp
The file was modifiedclang/test/OpenMP/target_teams_distribute_parallel_for_simd_reduction_codegen.cpp
The file was modifiedclang/test/OpenMP/teams_distribute_parallel_for_num_threads_codegen.cpp
The file was modifiedclang/test/OpenMP/teams_distribute_parallel_for_simd_collapse_codegen.cpp
The file was modifiedclang/test/OpenMP/distribute_parallel_for_num_threads_codegen.cpp
The file was modifiedclang/test/OpenMP/target_teams_distribute_simd_codegen.cpp
The file was modifiedclang/lib/CodeGen/CGCall.cpp
The file was modifiedclang/test/OpenMP/target_teams_distribute_parallel_for_simd_dist_schedule_codegen.cpp
The file was modifiedclang/test/OpenMP/teams_distribute_parallel_for_simd_num_threads_codegen.cpp
The file was modifiedclang/test/OpenMP/target_teams_distribute_parallel_for_firstprivate_codegen.cpp
The file was modifiedclang/test/OpenMP/target_teams_distribute_parallel_for_simd_firstprivate_codegen.cpp
The file was modifiedclang/test/OpenMP/teams_firstprivate_codegen.cpp
The file was modifiedclang/test/OpenMP/target_teams_distribute_private_codegen.cpp
The file was modifiedclang/test/OpenMP/parallel_reduction_codegen.cpp
The file was modifiedclang/test/OpenMP/target_teams_distribute_parallel_for_simd_schedule_codegen.cpp
The file was modifiedclang/test/OpenMP/target_parallel_for_simd_codegen.cpp
The file was modifiedclang/test/OpenMP/target_teams_distribute_dist_schedule_codegen.cpp
The file was modifiedclang/test/OpenMP/teams_distribute_codegen.cpp
The file was modifiedclang/test/OpenMP/sections_lastprivate_codegen.cpp
The file was modifiedclang/test/OpenMP/task_codegen.cpp
The file was modifiedclang/test/OpenMP/target_teams_codegen.cpp
The file was modifiedclang/test/OpenMP/target_teams_distribute_codegen.cpp
The file was modifiedclang/test/OpenMP/teams_distribute_parallel_for_simd_schedule_codegen.cpp
The file was modifiedclang/test/OpenMP/nvptx_target_parallel_reduction_codegen_tbaa_PR46146.cpp
The file was modifiedclang/test/OpenMP/teams_distribute_parallel_for_schedule_codegen.cpp
The file was modifiedclang/test/OpenMP/distribute_simd_firstprivate_codegen.cpp
The file was modifiedclang/test/OpenMP/target_teams_distribute_parallel_for_schedule_codegen.cpp
The file was modifiedclang/test/OpenMP/target_teams_distribute_parallel_for_lastprivate_codegen.cpp
The file was modifiedclang/test/OpenMP/teams_distribute_parallel_for_lastprivate_codegen.cpp
The file was modifiedclang/test/OpenMP/distribute_firstprivate_codegen.cpp
The file was modifiedclang/test/OpenMP/teams_distribute_parallel_for_reduction_codegen.cpp
The file was modifiedclang/test/OpenMP/target_teams_distribute_simd_dist_schedule_codegen.cpp
The file was modifiedclang/test/OpenMP/teams_distribute_firstprivate_codegen.cpp
The file was modifiedclang/test/OpenMP/target_parallel_num_threads_codegen.cpp
The file was modifiedclang/test/OpenMP/distribute_parallel_for_simd_num_threads_codegen.cpp
The file was modifiedclang/test/OpenMP/for_private_codegen.cpp
The file was modifiedclang/test/OpenMP/single_codegen.cpp
The file was modifiedclang/test/OpenMP/master_taskloop_in_reduction_codegen.cpp
The file was modifiedclang/test/OpenMP/teams_distribute_simd_dist_schedule_codegen.cpp
The file was modifiedclang/test/OpenMP/teams_distribute_parallel_for_simd_reduction_codegen.cpp
The file was modifiedclang/test/OpenMP/distribute_parallel_for_simd_firstprivate_codegen.cpp
The file was modifiedclang/test/OpenMP/target_teams_distribute_parallel_for_simd_collapse_codegen.cpp
The file was modifiedclang/test/CodeGenCXX/attr-musttail.cpp
The file was modifiedclang/test/OpenMP/target_teams_distribute_simd_firstprivate_codegen.cpp
The file was modifiedclang/test/OpenMP/distribute_lastprivate_codegen.cpp
The file was modifiedclang/test/OpenMP/teams_distribute_simd_private_codegen.cpp
The file was modifiedclang/test/OpenMP/target_parallel_for_codegen.cpp
The file was modifiedclang/test/OpenMP/distribute_parallel_for_simd_codegen.cpp
The file was modifiedclang/test/OpenMP/irbuilder_for_rangefor.cpp
The file was modifiedclang/test/OpenMP/target_teams_distribute_parallel_for_simd_lastprivate_codegen.cpp
The file was modifiedclang/test/OpenMP/taskloop_in_reduction_codegen.cpp
The file was modifiedclang/test/OpenMP/sections_private_codegen.cpp
The file was modifiedclang/test/CodeGenCXX/this-nonnull.cpp
The file was modifiedclang/test/OpenMP/nvptx_lambda_capturing.cpp
The file was modifiedclang/test/OpenMP/irbuilder_for_iterator.cpp
The file was modifiedclang/test/OpenMP/teams_distribute_parallel_for_copyin_codegen.cpp
The file was modifiedclang/test/OpenMP/parallel_firstprivate_codegen.cpp
The file was modifiedclang/test/OpenMP/nvptx_target_codegen.cpp
The file was modifiedclang/test/OpenMP/target_teams_distribute_collapse_codegen.cpp
The file was modifiedclang/test/OpenMP/target_teams_num_teams_codegen.cpp
The file was modifiedclang/test/OpenMP/target_teams_distribute_simd_collapse_codegen.cpp
The file was modifiedclang/test/OpenMP/parallel_master_taskloop_codegen.cpp
The file was modifiedclang/test/OpenMP/parallel_master_codegen.cpp
The file was modifiedclang/test/OpenMP/threadprivate_codegen.cpp
The file was modifiedclang/test/OpenMP/for_firstprivate_codegen.cpp
The file was modifiedclang/test/OpenMP/distribute_parallel_for_firstprivate_codegen.cpp
The file was modifiedclang/test/OpenMP/target_teams_distribute_parallel_for_simd_private_codegen.cpp
The file was modifiedclang/test/CodeGenCXX/thunk-wrong-this.cpp
The file was modifiedclang/test/OpenMP/distribute_simd_lastprivate_codegen.cpp
The file was modifiedclang/test/OpenMP/taskloop_simd_in_reduction_codegen.cpp
The file was modifiedclang/test/OpenMP/teams_codegen.cpp
The file was modifiedclang/test/OpenMP/teams_distribute_parallel_for_collapse_codegen.cpp
The file was modifiedclang/test/OpenMP/teams_distribute_reduction_codegen.cpp
The file was modifiedclang/test/OpenMP/distribute_parallel_for_simd_lastprivate_codegen.cpp
The file was modifiedclang/test/OpenMP/parallel_master_taskloop_simd_lastprivate_codegen.cpp
The file was modifiedclang/test/OpenMP/parallel_for_linear_codegen.cpp
The file was modifiedclang/test/OpenMP/sections_reduction_codegen.cpp
The file was modifiedclang/test/OpenMP/teams_distribute_simd_lastprivate_codegen.cpp
The file was modifiedclang/test/OpenMP/teams_distribute_lastprivate_codegen.cpp
The file was modifiedclang/test/OpenMP/teams_distribute_parallel_for_codegen.cpp
The file was modifiedclang/test/OpenMP/for_lastprivate_codegen.cpp
The file was modifiedclang/test/OpenMP/teams_distribute_simd_collapse_codegen.cpp
The file was modifiedclang/test/CodeGenObjCXX/objc-struct-cxx-abi.mm
The file was modifiedclang/test/OpenMP/teams_distribute_simd_firstprivate_codegen.cpp
The file was modifiedclang/test/OpenMP/teams_distribute_parallel_for_simd_firstprivate_codegen.cpp
The file was modifiedclang/test/OpenMP/target_teams_distribute_parallel_for_reduction_codegen.cpp
The file was modifiedclang/test/OpenMP/distribute_parallel_for_simd_private_codegen.cpp
The file was modifiedclang/test/OpenMP/target_parallel_if_codegen.cpp
The file was modifiedclang/test/OpenMP/single_firstprivate_codegen.cpp
The file was modifiedclang/test/CodeGen/attr-nomerge.cpp
The file was modifiedclang/test/OpenMP/teams_private_codegen.cpp
The file was modifiedclang/test/OpenMP/target_teams_distribute_firstprivate_codegen.cpp
The file was modifiedclang/test/OpenMP/parallel_master_taskloop_simd_codegen.cpp
The file was modifiedclang/test/OpenMP/teams_distribute_parallel_for_private_codegen.cpp
The file was modifiedclang/test/OpenMP/for_reduction_codegen.cpp
The file was modifiedclang/test/OpenMP/teams_distribute_parallel_for_simd_dist_schedule_codegen.cpp
The file was modifiedclang/test/CodeGenCoroutines/coro-symmetric-transfer-01.cpp
The file was modifiedclang/test/OpenMP/distribute_private_codegen.cpp
The file was modifiedclang/test/OpenMP/teams_distribute_collapse_codegen.cpp
The file was modifiedclang/test/OpenMP/parallel_copyin_codegen.cpp
The file was modifiedclang/test/OpenMP/parallel_private_codegen.cpp
The file was modifiedclang/test/OpenMP/target_teams_thread_limit_codegen.cpp
The file was modifiedclang/test/OpenMP/parallel_master_taskloop_lastprivate_codegen.cpp
The file was modifiedclang/test/OpenMP/teams_distribute_parallel_for_simd_private_codegen.cpp
The file was modifiedclang/test/OpenMP/teams_distribute_private_codegen.cpp
The file was modifiedclang/test/OpenMP/tile_codegen.cpp
The file was modifiedclang/test/OpenMP/teams_distribute_parallel_for_dist_schedule_codegen.cpp
The file was modifiedclang/test/OpenMP/target_teams_distribute_parallel_for_private_codegen.cpp
Commit 7c57a9bd7d4c976b7a824472c427433359200e02 by Duncan P. N. Exon Smith
Modules: Simplify how DisableGeneratingGlobalModuleIndex is set, likely NFC

DisableGeneratingGlobalModuleIndex was being set by
CompilerInstance::findOrCompileModuleAndReadAST most of (but not all of)
the times it returned `nullptr` as a "normal" failure. Pull that up to
the caller, CompilerInstance::loadModule, to simplify the code. This
resolves a number of FIXMEs added during the refactoring in
5cca622310c10fdf6f921b6cce26f91d9f14c762.

The extra cases where this is set are all some version of a fatal error,
and the only client of the field, shouldBuildGlobalModuleIndex, seems
to be unreachable in that case. Even if there is some corner case where
this has an effect, it seems like the right/consistent behaviour.

Differential Revision: https://reviews.llvm.org/D101672
The file was modifiedclang/lib/Frontend/CompilerInstance.cpp
Commit 50e0b2985e43baf61617c9734df71e949113f911 by pklausler
[flang] Implement DOT_PRODUCT in the runtime

API, implementation, and basic tests for the transformational
reduction intrinsic function DOT_PRODUCT in the runtime support
library.

Differential Revision: https://reviews.llvm.org/D102351
The file was modifiedflang/runtime/CMakeLists.txt
The file was modifiedflang/runtime/tools.h
The file was modifiedflang/runtime/complex-reduction.c
The file was addedflang/runtime/dot-product.cpp
The file was modifiedflang/unittests/RuntimeGTest/Reduction.cpp
The file was modifiedflang/runtime/reduction.cpp
The file was modifiedflang/runtime/complex-reduction.h
The file was modifiedflang/runtime/reduction.h
Commit 54310fc176fde539b15f3cc95d4a3555df446ff6 by stefanp
[PowerPC] Add ROP Protection to prologue and epilogue

Added hashst to the prologue and hashchk to the epilogue.
The hash for the prologue and epilogue must always be stored as the first
element in the local variable space on the stack.

Reviewed By: nemanjai, #powerpc

Differential Revision: https://reviews.llvm.org/D99377
The file was modifiedllvm/lib/Target/PowerPC/PPCFrameLowering.cpp
The file was modifiedllvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
The file was addedllvm/test/CodeGen/PowerPC/ppc64-rop-protection.ll
The file was modifiedllvm/lib/Target/PowerPC/PPCRegisterInfo.h
The file was modifiedllvm/lib/Target/PowerPC/PPCMachineFunctionInfo.h
The file was modifiedllvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
Commit 9d3eb7885d916b22bc673334f71a10e3b2835174 by lebedev.ri
[NFC] Try to fix CodeGenCXX/thunk-wrong-this.cpp test
The file was modifiedclang/test/CodeGenCXX/thunk-wrong-this.cpp
Commit 8ec9fd483949ca3b23053effcac226dcc56e7a95 by amanieu
Support unwinding from inline assembly

I've taken the following steps to add unwinding support from inline assembly:

1) Add a new `unwind` "attribute" (like `sideeffect`) to the asm syntax:

```
invoke void asm sideeffect unwind "call thrower", "~{dirflag},~{fpsr},~{flags}"()
    to label %exit unwind label %uexit
```

2.) Add Bitcode writing/reading support + LLVM-IR parsing.

3.) Emit EHLabels around inline assembly lowering (SelectionDAGBuilder + GlobalISel) when `InlineAsm::canThrow` is enabled.

4.) Tweak InstCombineCalls/InlineFunction pass to not mark inline assembly "calls" as nounwind.

5.) Add clang support by introducing a new clobber: "unwind", which lower to the `canThrow` being enabled.

6.) Don't allow unwinding callbr.

Reviewed By: Amanieu

Differential Revision: https://reviews.llvm.org/D95745
The file was modifiedllvm/bindings/go/llvm/ir.go
The file was modifiedclang/include/clang/Basic/DiagnosticSemaKinds.td
The file was modifiedllvm/lib/IR/AsmWriter.cpp
The file was modifiedllvm/lib/IR/Core.cpp
The file was modifiedclang/lib/Sema/SemaStmtAsm.cpp
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
The file was modifiedllvm/lib/IR/ConstantsContext.h
The file was addedclang/test/CodeGenCXX/unwind-inline-asm.cpp
The file was modifiedllvm/lib/AsmParser/LLParser.cpp
The file was modifiedllvm/lib/IR/InlineAsm.cpp
The file was addedllvm/test/CodeGen/X86/no-seh-unwind-inline-asm-codegen.ll
The file was addedllvm/test/CodeGen/X86/no-unwind-inline-asm-codegen.ll
The file was modifiedllvm/lib/Transforms/Utils/ValueMapper.cpp
The file was addedllvm/test/CodeGen/AArch64/GlobalISel/unwind-inline-asm.ll
The file was addedllvm/test/CodeGen/AArch64/GlobalISel/irtranslator-no-unwind-inline-asm.ll
The file was addedllvm/test/Transforms/Inline/unwind-inline-asm.ll
The file was addedllvm/test/CodeGen/X86/sjlj-unwind-inline-asm-codegen.ll
The file was modifiedclang/lib/Basic/TargetInfo.cpp
The file was modifiedllvm/lib/IR/Verifier.cpp
The file was addedllvm/test/Transforms/InstCombine/no-unwind-inline-asm.ll
The file was modifiedllvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
The file was modifiedllvm/lib/Transforms/Utils/InlineFunction.cpp
The file was addedllvm/test/CodeGen/AArch64/GlobalISel/irtranslator-unwind-inline-asm.ll
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
The file was addedllvm/test/Transforms/InstCombine/unwind-inline-asm.ll
The file was modifiedllvm/include/llvm/IR/InlineAsm.h
The file was modifiedllvm/lib/Bitcode/Writer/BitcodeWriter.cpp
The file was addedllvm/test/Transforms/Inline/no-unwind-inline-asm.ll
The file was modifiedllvm/lib/Bitcode/Reader/BitcodeReader.cpp
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
The file was modifiedclang/lib/CodeGen/CGStmt.cpp
The file was modifiedllvm/include/llvm/Bitcode/LLVMBitCodes.h
The file was addedllvm/test/CodeGen/X86/seh-unwind-inline-asm-codegen.ll
The file was modifiedllvm/include/llvm-c/Core.h
The file was addedllvm/test/CodeGen/X86/unwind-inline-asm-codegen.ll
Commit ecc4e9e8f4cb7581cbc447bc838943176715695c by lebedev.ri
[NFC] Try to fix CodeGenCXX/thunk-wrong-return-type.cpp test
The file was modifiedclang/test/CodeGenCXX/thunk-wrong-this.cpp
The file was modifiedclang/test/CodeGenCXX/thunk-wrong-return-type.cpp
Commit 6829bd3ed0515e17c84c5e72fe1742bd20ee61e5 by pklausler
[flang] (NFC) Expose internal idiom as utility API

Add overloads to AsGenericExpr() in Evaluate/tools.h to take care
of wrapping an untyped DataRef or bare Symbol in a typed Designator
wrapped up in a generic Expr<SomeType>.  Use the new overloads to
replace a few instances of code that was calling TypedWrapper<>()
with a dynamic type.

This new tool will be useful in lowering to drive some code that
works with typed expressions (viz., list-directed I/O list items)
when starting with only a bare Symbol (viz., NAMELIST).

Differential Revision: https://reviews.llvm.org/D102352
The file was modifiedflang/lib/Semantics/check-declarations.cpp
The file was modifiedflang/lib/Evaluate/tools.cpp
The file was modifiedflang/include/flang/Evaluate/tools.h
The file was modifiedflang/lib/Semantics/expression.cpp
The file was modifiedflang/lib/Evaluate/fold-designator.cpp
Commit 0d8f91d2a9994619bb62c548a81eb605f0e768f7 by lebedev.ri
[NFC] Delete two newly-added test cases

Failing on bots in unobvious ways.
The file was removedclang/test/CodeGenCXX/thunk-wrong-this.cpp
The file was removedclang/test/CodeGenCXX/thunk-wrong-return-type.cpp
Commit dd98ea528c0c23f5fee6d3dbafc261b81cca9f0d by Artem Dergachev
[ASTMatchers] NFC: Fix formatting around forFunction().

Differential Revision: https://reviews.llvm.org/D102303
The file was modifiedclang/docs/LibASTMatchersReference.html
The file was modifiedclang/include/clang/ASTMatchers/ASTMatchers.h
Commit 6a079dfdc992706408f2bde84c48bf76e52c4311 by Artem Dergachev
[ASTMatchers] Add forCallable(), a generalization of forFunction().

The new matcher additionally covers blocks and Objective-C methods.

This matcher actually makes sure that the statement truly belongs
to that declaration's body. forFunction() incorrectly reported that
a statement in a nested block belonged to the surrounding function.

forFunction() is now deprecated due to the above footgun, in favor of
forCallable(functionDecl()) when only functions need to be considered.

Differential Revision: https://reviews.llvm.org/D102213
The file was modifiedclang/lib/ASTMatchers/Dynamic/Registry.cpp
The file was modifiedclang/docs/LibASTMatchersReference.html
The file was modifiedclang/include/clang/ASTMatchers/ASTMatchers.h
The file was modifiedclang/unittests/ASTMatchers/ASTMatchersTraversalTest.cpp
Commit 46c6c08c9428a36bdf88f51b1a14164aa4cbb93e by Artem Dergachev
[clang-tidy] bugprone-infinite-loop: forFunction() -> forCallable().

Take advantage of the new ASTMatcher added in D102213 to fix massive false negatives of the infinite loop checker on Objective-C.

Differential Revision: https://reviews.llvm.org/D102214
The file was modifiedclang-tools-extra/clang-tidy/utils/Aliasing.h
The file was modifiedclang-tools-extra/test/clang-tidy/checkers/bugprone-infinite-loop.cpp
The file was modifiedclang-tools-extra/clang-tidy/utils/Aliasing.cpp
The file was modifiedclang-tools-extra/clang-tidy/bugprone/InfiniteLoopCheck.cpp
The file was addedclang-tools-extra/test/clang-tidy/checkers/bugprone-infinite-loop.mm
Commit 5ad2eeeadaf15856332f66ed7c244d52a86b0be7 by Artem Dergachev
[clang-tidy] bugprone-infinite-loop: React to ObjC ivars and messages.

If the loop condition is a value of an instance variable, a property value,
or a message result value, it's a good indication that the loop is not infinite
and we have a really hard time proving the opposite so suppress the warning.

Differential Revision: https://reviews.llvm.org/D102294
The file was modifiedclang-tools-extra/test/clang-tidy/checkers/bugprone-infinite-loop.mm
The file was modifiedclang-tools-extra/clang-tidy/bugprone/InfiniteLoopCheck.cpp
Commit 464e4dc50f4e6e058e12a7020385d5bf29fd1df6 by aakanksha555
[AMDGPU] Add gfx1034 target

Differential Revision: https://reviews.llvm.org/D102306
The file was modifiedclang/test/Driver/amdgpu-mcpu.cl
The file was modifiedclang/include/clang/Basic/Cuda.h
The file was modifiedclang/test/Driver/amdgpu-macros.cl
The file was modifiedclang/test/Misc/target-invalid-cpu-note.c
The file was modifiedllvm/test/CodeGen/AMDGPU/elf-header-flags-mach.ll
The file was modifiedclang/test/CodeGenOpenCL/amdgpu-features.cl
The file was modifiedllvm/test/MC/Disassembler/AMDGPU/gfx1030_dasm_new.txt
The file was modifiedllvm/test/MC/AMDGPU/gfx1011_dlops.s
The file was modifiedllvm/test/tools/llvm-objdump/ELF/AMDGPU/subtarget.ll
The file was modifiedllvm/docs/AMDGPUUsage.rst
The file was modifiedllvm/lib/ObjectYAML/ELFYAML.cpp
The file was modifiedclang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp
The file was modifiedopenmp/libomptarget/plugins/amdgpu/impl/get_elf_mach_gfx_name.cpp
The file was modifiedclang/lib/Basic/Targets/AMDGPU.cpp
The file was modifiedllvm/lib/Object/ELFObjectFile.cpp
The file was modifiedllvm/lib/Support/TargetParser.cpp
The file was modifiedllvm/test/Object/AMDGPU/elf-header-flags-mach.yaml
The file was modifiedllvm/test/CodeGen/AMDGPU/directive-amdgcn-target.ll
The file was modifiedclang/lib/Basic/Targets/NVPTX.cpp
The file was modifiedclang/lib/Basic/Cuda.cpp
The file was modifiedllvm/test/MC/Disassembler/AMDGPU/gfx1011_dasm_dlops.txt
The file was modifiedllvm/lib/Target/AMDGPU/GCNProcessors.td
The file was modifiedllvm/tools/llvm-readobj/ELFDumper.cpp
The file was modifiedllvm/test/MC/AMDGPU/gfx1030_err.s
The file was modifiedllvm/test/tools/llvm-readobj/ELF/amdgpu-elf-headers.test
The file was modifiedllvm/include/llvm/Support/TargetParser.h
The file was modifiedllvm/test/MC/AMDGPU/gfx1030_new.s
The file was modifiedllvm/include/llvm/BinaryFormat/ELF.h
The file was modifiedllvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp
Commit 3ac9ff5577f1d4b032a64aea1c46e95c8a5b8f68 by zoecarver
[libcxx][docs] Update the One Ranges PRoposal Status with open revisions.

1. Moves the names into the names column.
2. Changes the names to reflect who's actually working on what.
3. Adds open revisions.
The file was modifiedlibcxx/docs/OneRangesProposalStatus.csv
Commit fe319a8848f2343829925850a3969861d8d6a64c by zoecarver
[libcxx][docs] Add two locks: transform_view and take_view.

Assign myself both of these views.
The file was modifiedlibcxx/docs/OneRangesProposalStatus.csv
Commit 72abc199772c30ea2cffaa5dd4a8aa2bb2b7f18c by pklausler
[flang] Support legacy extension OPEN(ACCESS='APPEND')

It should of course be POSITION='APPEND' but Sun Fortran
supported it on ACCESS=.

Differential Revision: https://reviews.llvm.org/D102350
The file was modifiedflang/docs/Extensions.md
The file was modifiedflang/include/flang/Common/Fortran-features.h
The file was modifiedflang/lib/Semantics/check-io.cpp
The file was modifiedflang/runtime/io-api.cpp
Commit a249ffa42137431d44d7db1d04f122300bc51533 by enye.shi
[HIP] Clean up llvm intrinsics using __asm

Instead of using inline asm, use clang builtins
for llvm intrinsics.

Differential Revision: https://reviews.llvm.org/D102427
The file was modifiedclang/lib/Headers/__clang_hip_libdevice_declares.h
Commit b766576d38d304c630de5430053d06dfc7784628 by arnamoy.bhattacharyya
[flang][OpenMP] Add semantic check for close nesting of `master` regions

This patch implements the following semantic check:
```
A master region may not be closely nested inside a work-sharing, loop, atomic, task, or taskloop region.
```

Adds a test case and also modifies a couple of existing test cases to include the check.

Reviewed By: kiranchandramohan

Differential Revision: https://reviews.llvm.org/D100228
The file was modifiedflang/lib/Semantics/check-omp-structure.h
The file was modifiedflang/lib/Semantics/check-omp-structure.cpp
The file was modifiedflang/test/Semantics/omp-ordered-simd.f90
The file was addedflang/test/Semantics/omp-nested-master.f90
Commit 861dc75906829a177dc2e5249747771aa3866a06 by sivachandra
[libc] Add x86_64 implementations of double precision cos, sin and tan.

The implementations use the x86_64 FPU instructions. These instructions
are extremely slow compared to a polynomial based software
implementation. Also, their accuracy falls drastically once the input
goes beyond 2PI. To improve both the speed and accuracy, we will be
taking the following approach going forward:
1. As a follow up to this CL, we will implement a range reduction algorithm
which will expand the accuracy to the entire double precision range.
2. After that, we will replace the HW instructions with a polynomial
implementation to improve the run time.

After step 2, the implementations will be accurate, performant and target
architecture independent.

Reviewed By: lntue

Differential Revision: https://reviews.llvm.org/D102384
The file was modifiedlibc/src/math/CMakeLists.txt
The file was modifiedlibc/spec/stdc.td
The file was addedlibc/src/math/x86_64/tan.cpp
The file was modifiedlibc/config/linux/x86_64/entrypoints.txt
The file was modifiedlibc/test/src/math/CMakeLists.txt
The file was modifiedlibc/utils/MPFRWrapper/MPFRUtils.h
The file was addedlibc/src/math/x86_64/sin.cpp
The file was addedlibc/src/math/cos.h
The file was addedlibc/src/math/x86_64/CMakeLists.txt
The file was addedlibc/src/math/tan.h
The file was addedlibc/test/src/math/tan_test.cpp
The file was addedlibc/test/src/math/cos_test.cpp
The file was addedlibc/src/math/x86_64/cos.cpp
The file was addedlibc/test/src/math/sin_test.cpp
The file was addedlibc/src/math/sin.h
The file was modifiedlibc/utils/MPFRWrapper/MPFRUtils.cpp
Commit 7deb5ef44f2865f1b34cff98176a1a723107cf08 by sivachandra
[libc][NFC] Instead of erroring, skip math targets with missing implementations.

Fixes Aarch64 bot.
The file was modifiedlibc/src/math/CMakeLists.txt
Commit b42fb6811e25322f7e55d3f76fe13a6829202219 by martin
[llvm-nm] Support the -V option, print that the tool is compatible with GNU nm

This unlocks some codepaths in libtool.

Differential Revision: https://reviews.llvm.org/D102321
The file was modifiedllvm/tools/llvm-nm/llvm-nm.cpp
The file was modifiedllvm/docs/CommandGuide/llvm-nm.rst
The file was addedllvm/test/tools/llvm-nm/libtool-version.test
Commit 12874e93a15219ccfaff42a0536b2b5368c6f304 by silvasean
[mlir][NFC] Add helper for common pattern of replaceAllUsesExcept

This covers the extremely common case of replacing all uses of a Value
with a new op that is itself a user of the original Value.

This should also be a little bit more efficient than the
`SmallPtrSet<Operation *, 1>{op}` idiom that was being used before.

Differential Revision: https://reviews.llvm.org/D102373
The file was modifiedmlir/lib/Dialect/SCF/Transforms/ParallelLoopTiling.cpp
The file was modifiedmlir/include/mlir/IR/Value.h
The file was modifiedmlir/lib/IR/Value.cpp
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/Tiling.cpp
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/Fusion.cpp
The file was modifiedmlir/lib/Dialect/Affine/Transforms/AffineLoopNormalize.cpp
Commit 0831793ed962105b51057c02df413abef4767e7c by rob.suderman
[mlir][tosa] Add tosa.div integer lowering to linalg.generic.

Lowering div elementwise op to the linalg dialect. Since tosa only supports integer division, that is the only version that is currently implemented.

Reviewed By: rsuderman

Differential Revision: https://reviews.llvm.org/D102430
The file was modifiedmlir/lib/Conversion/TosaToLinalg/TosaToLinalg.cpp
The file was modifiedmlir/test/Conversion/TosaToLinalg/tosa-to-linalg.mlir
Commit 8b57ed09bd238b00b5d096f9be7ef9f831428044 by huberjn
[OpenMP] Prevent Attributor from deleting functions in OpenMPOptCGSCC pass

Summary:
This patch prevents the Attributor instances made in the CGSCC pass from
deleting functions. This prevents the attributor from changing the call
graph while OpenMPOpt is working with it.

Reviewed By: jdoerfert

Differential Revision: https://reviews.llvm.org/D102363
The file was modifiedllvm/lib/Transforms/IPO/OpenMPOpt.cpp
Commit 4f05f4c8e66bc76b1d94f5283494404382e3bacd by i
[CMake][ELF] Link libLLVM.so and libclang-cpp.so with -Bsymbolic-functions

llvm-dev message: https://lists.llvm.org/pipermail/llvm-dev/2021-May/150465.html

In an ELF shared object, a default visibility defined symbol is preemptible by
default. This creates some missed optimization opportunities.
-Bsymbolic-functions is more aggressive than our current -fvisibility-inlines-hidden
(present since 2012) as it applies to all function definitions.  It can

* avoid PLT for cross-TU function calls && reduce dynamic symbol lookup
* reduce dynamic symbol lookup for taking function addresses and optimize out GOT/TOC on x86-64/ppc64

In a -DLLVM_TARGETS_TO_BUILD=X86 build, the number of JUMP_SLOT decreases from 12716 to 1628, and the number of GLOB_DAT decreases from 1918 to 1313
The built clang with `-DLLVM_LINK_LLVM_DYLIB=on -DCLANG_LINK_CLANG_DYLIB=on` is significantly faster.
See the Linux kernel build result https://bugs.archlinux.org/task/70697

Note: the performance of -fno-semantic-interposition -Bsymbolic-functions
libLLVM.so and libclang-cpp.so is close to a PIE binary linking against
`libLLVM*.a` and `libclang*.a`. When the host compiler is Clang,
-Bsymbolic-functions is the major contributor.  On x86-64 (with GOTPCRELX) and
ppc64 ELFv2, the GOT/TOC relocations can be optimized.

Some implication:

Interposing a subset of functions is no longer supported.
(This is fragile on ELF and unsupported on Mach-O at all. For Mach-O we don't
use `ld -interpose` or `-flat_namespace`)

Compiling a program which takes the address of any LLVM function with
`{gcc,clang} -fno-pic` and expects the address to equal to the address taken
from libLLVM.so or libclang-cpp.so is unsupported. I am fairly confident that
llvm-project shouldn't have different behaviors depending on such pointer
equality (as we've been using -fvisibility-inlines-hidden which applies to
inline functions for a long time), but if we accidentally do, users should be
aware that they should not make assumption on pointer equality in `-fno-pic`
mode.

See more on https://maskray.me/blog/2021-05-09-fno-semantic-interposition

Reviewed By: phosek

Differential Revision: https://reviews.llvm.org/D102090
The file was modifiedllvm/tools/llvm-shlib/CMakeLists.txt
The file was modifiedclang/tools/clang-shlib/CMakeLists.txt
Commit b47539a14dc8a40e8710aef2fb75d2486f271dba by sivachandra
[libc] Enable fmaf and fma on x86_64.

They require clang-11 or above for building and hence had to be disabled
as the bots did not have clang-11 or higher. Bots have now been upgraded
so we can enable these functions now.
The file was modifiedlibc/config/linux/x86_64/entrypoints.txt
Commit f97d970a49fb1f95cd3ac599369e53325129f769 by rob.suderman
[mlir][tosa] Add lowering to tosa.abs for integer cases

Integer case requires decomposing to simple LLVM operatons.

Differential Revision: https://reviews.llvm.org/D101809
The file was modifiedmlir/lib/Conversion/TosaToLinalg/TosaToLinalg.cpp
The file was modifiedmlir/test/Conversion/TosaToLinalg/tosa-to-linalg.mlir
Commit 6c4596793d43703923552e791716a3d511e28fe0 by lebedev.ri
[NFC][X86][MCA] AMD Zen 3: add same-reg SSE XMM XORPS test
The file was addedllvm/test/tools/llvm-mca/X86/Znver3/zero-idioms-sse-xmm.s
Commit aa0dcb3ba4b93e4499208def080ced98f3a89ad5 by lebedev.ri
[X86] AMD Zen 3: same-reg SSE XMM XORPS is a 1-cycle(!) dep-breaking one-idiom

While both the SOG and Agner insist that it is zero-cycle,
i can not confirm that claim. While it clearly breaks the dependency,
i can not come up with a snippet, or measurement approach,
to end up with IPC bigger than 4, which, to me, means that it actually
consumes execution resource of an FP unit for a cycle.
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver3/zero-idioms-sse-xmm.s
The file was modifiedllvm/lib/Target/X86/X86ScheduleZnver3.td
Commit 6b95fd199d96e3ba5c28a23b17b74203522bdaa8 by lebedev.ri
Revert "[X86] X86TTIImpl::getInterleavedMemoryOpCostAVX2(): use getMemoryOpCost()"

Depends on a commit that is about to be reverted.

This reverts commit 69ed93a4355123a45c1d7216aea7cd53d07a361b.
The file was modifiedllvm/lib/Target/X86/X86TargetTransformInfo.cpp
The file was modifiedllvm/test/Analysis/CostModel/X86/interleaved-load-i8.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/interleaved-store-i8.ll
Commit 5fddc3312bad7e62493f1605385fad5e589e6450 by lebedev.ri
Revert "[X86][CostModel] X86TTIImpl::getMemoryOpCost(): rewrite vector handling again"

As reported in post-commit feedback, this has issues with e.g. <16 x i1>:
https://llvm.godbolt.org/z/jxPvdGEW4

This reverts commit c02476f3158f2908ef0a6f628210b5380bd33695.
The file was modifiedllvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-3.ll
The file was modifiedllvm/lib/Target/X86/X86TargetTransformInfo.cpp
The file was modifiedllvm/test/Analysis/CostModel/X86/interleaved-store-i16-stride-3.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/load_store.ll
Commit dce158c58d851747c2e1c188dcf4baa4620b5516 by nikita.ppv
[AA] Use isIdentifiedFunctionLocal() (NFC)

This condition is equivalent to isIdentifiedFunctionLocal(),
and this is also what we semantically want to check here.
The file was modifiedllvm/lib/Analysis/AliasAnalysis.cpp
Commit 425781bce01f2f1d5f553d3b2bf9ebbd6e15068c by nikita.ppv
[CaptureTracking] Use isIdentifiedFunctionLocal() (NFC)

These conditions together exactly match isIdentifiedFunctionLocal(),
and this is also what we logically want to check for here.
The file was modifiedllvm/lib/Analysis/CaptureTracking.cpp
Commit 71a0609a2b533dbcd6826ad774b6bee5e9818644 by Lang Hames
[clang-repl] Temporarily disable the execute.cpp test on ppc64.

This test is failing on some builders (see [1]) with the following error:

error: Added modules have incompatible data layouts:
  e-m:e-i64:64-n32:64-S128-v256:256:256-v512:512:512 (module) vs
  E-m:a-i64:64-n32:64-S128-v256:256:256-v512:512:512 (jit)

The JIT layout is correct, but some IR module added to the JIT is using a
little-endian layout instead.

This commit disables the test on ppc64 until we can investigate further and
fix the bug.

[1] https://lab.llvm.org/staging/#/builders/126/builds/371
The file was modifiedclang/test/Interpreter/execute.cpp
Commit 772bdef6afb661dfd67b3e5c77befa56d249bff8 by aeubanks
[docs] Add page on opaque pointer types

Reviewed By: dblaikie, dexonsmith

Differential Revision: https://reviews.llvm.org/D102292
The file was addedllvm/docs/OpaquePointers.rst
The file was modifiedllvm/docs/UserGuides.rst
Commit 93d56922fabaf52eec8d1d4e28e04fa47eb1c797 by amanieu
Don't run MachineVerifier on sjlj-unwind-inline-asm test because of known issue (PR39439)

Fixes buildbot failure (https://lab.llvm.org/buildbot/#/builders/16/builds/10825).

Reviewed By: Amanieu

Differential Revision: https://reviews.llvm.org/D102433
The file was modifiedllvm/test/CodeGen/X86/sjlj-unwind-inline-asm-codegen.ll
Commit 83ff0ff46337422171fb36f934bd56c2bc1be15c by llvm-project
[Clang][OpenMP] Allow unified_shared_memory for Pascal-generation GPUs.

The Pascal architecture supports the page migration engine required for
unified_shared_memory, as indicated by NVIDIA:
* https://developer.nvidia.com/blog/unified-memory-cuda-beginners/
* https://developer.nvidia.com/blog/beyond-gpu-memory-limits-unified-memory-pascal/
* https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#um-requirements

The limitation was introduced in D54493 which justified the cut-off by
the requirement for unified addressing. However, Unified Virtual
Addressing (UVA) is already available with sm20 (Fermi, Kepler,
Maxwell):
* https://docs.nvidia.com/cuda/gpudirect-rdma/index.html#basics-of-uva-cuda-memory-management

Unified shared memory might even be possible with these, but with
migration of entire allocations on kernel startup.

Reviewed By: JonChesterfield

Differential Revision: https://reviews.llvm.org/D101595
The file was modifiedclang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp
The file was modifiedclang/test/OpenMP/requires_codegen.cpp
Commit 2155dc51d700c9fb5f29d79eaacf5e1470e4d8ca by aeubanks
[IR] Introduce the opaque pointer type

The opaque pointer type is essentially just a normal pointer type with a
null pointee type.

This also adds support for the opaque pointer type to the bitcode
reader/writer, as well as to textual IR.

To avoid confusion with existing pointer types, we disallow creating a
pointer to an opaque pointer.

Opaque pointer types should not be widely used at this point since many
parts of LLVM still do not support them. The next steps are to add some
very simple use cases of opaque pointers to make sure they work, then
start pretending that all pointers are opaque pointers and see what
breaks.

https://lists.llvm.org/pipermail/llvm-dev/2021-May/150359.html

Reviewed By: dblaikie, dexonsmith, pcc

Differential Revision: https://reviews.llvm.org/D101704
The file was addedllvm/test/Assembler/invalid-opaque-ptr.ll
The file was modifiedllvm/lib/IR/AsmWriter.cpp
The file was modifiedllvm/lib/IR/LLVMContextImpl.h
The file was addedllvm/test/Assembler/opaque-ptr.ll
The file was modifiedllvm/lib/Bitcode/Writer/BitcodeWriter.cpp
The file was modifiedllvm/lib/AsmParser/LLParser.cpp
The file was modifiedllvm/lib/IR/Type.cpp
The file was modifiedllvm/docs/LangRef.rst
The file was modifiedllvm/lib/Bitcode/Reader/BitcodeReader.cpp
The file was modifiedllvm/include/llvm/Bitcode/LLVMBitCodes.h
The file was modifiedllvm/include/llvm/IR/DerivedTypes.h
The file was modifiedllvm/docs/ReleaseNotes.rst
The file was modifiedllvm/lib/AsmParser/LLLexer.cpp
Commit be5c7c5d8230428f024bd656beb48ef8462985ff by steveire
Widen `name` stencil to support `TypeLoc` nodes.

Differential Revision: https://reviews.llvm.org/D102185
The file was modifiedclang/unittests/Tooling/RangeSelectorTest.cpp
The file was modifiedclang/include/clang/Tooling/Transformer/RangeSelector.h
The file was modifiedclang/lib/Tooling/Transformer/RangeSelector.cpp
Commit 1e01a8919f8d0fdc8c2f5f679fcc541b61381b0f by nicolas.vasilache
[mlir][Linalg] Add ComprehensiveBufferize for functions(step 1/n)

This is the first step towards upstreaming comprehensive bufferization following the
discourse post: https://llvm.discourse.group/t/rfc-linalg-on-tensors-update-and-comprehensive-bufferization-rfc/3373/6.

This first commit introduces a basic pass for bufferizing within function boundaries,
assuming that the inplaceable function boundaries have been marked as such.

Differential revision: https://reviews.llvm.org/D101693
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/CMakeLists.txt
The file was addedmlir/test/Dialect/Linalg/comprehensive-func-bufferize.mlir
The file was modifiedmlir/include/mlir/Dialect/Linalg/IR/LinalgBase.td
The file was addedmlir/lib/Dialect/Linalg/Transforms/ComprehensiveBufferize.cpp
The file was modifiedmlir/lib/Dialect/Linalg/IR/LinalgTypes.cpp
The file was modifiedmlir/include/mlir/Dialect/Linalg/Passes.td
The file was modifiedmlir/include/mlir/Dialect/Linalg/Passes.h
Commit bebf5d56bff75cd5b74b58cbdcb965885a82916f by nicolas.vasilache
[mlir][Linalg] Add support for vector.transfer ops to comprehensive bufferization (2/n).

Differential revision: https://reviews.llvm.org/D102395
The file was modifiedmlir/test/Dialect/Linalg/comprehensive-func-bufferize.mlir
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/ComprehensiveBufferize.cpp
Commit 6a70874d27c73cf8b55a568449fd92f97b5bb7b3 by Matthew.Arsenault
AMDGPU/GlobalISel: Implement tail calls

Or at least the sibling call cases which the DAG already handles.
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-sibling-call.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/call-constant.ll
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-tail-call.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/tail-call-amdgpu-gfx.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUCallLowering.h
Commit 85394d9ed71bea61000a502abc1f89a3981bee59 by Matthew.Arsenault
AMDGPU/GlobalISel: Don't hardcode stack alignment in assert message
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
Commit 5ba4a0e890c8106a10d32b0d34af1b214b9bdf3a by rnk
[gn] Don't pass -fprofile-instr-generate to linker on Windows

Avoids a warning from the linker. The user still has to put the resource
directory on the linker search path, and I can't find a clean way to do
that automatically in gn.
The file was modifiedllvm/utils/gn/build/BUILD.gn
Commit 8fdfead71aba430c163cc9c972a387a17fd8b939 by clementval
[mlir][openacc][NFC] add anonymous namespace around LegalizeDataOpForLLVMTranslation class

Add missing anonymous namespace around LegalizeDataOpForLLVMTranslation class .

Reviewed By: rriddle

Differential Revision: https://reviews.llvm.org/D102380
The file was modifiedmlir/lib/Conversion/OpenACCToLLVM/OpenACCToLLVM.cpp
Commit af6eb1c710ca17f2f9bce667b9fb593b6541f260 by Amara Emerson
[AArch64][GlobalISel] Fix a crash during unsuccessful G_CTPOP <2 x s64> legalization.

The legalization rule for scalar-same-as doesn't handle vectors. Until we
implement custom legalization for this, at least fall back properly.
The file was addedllvm/test/CodeGen/AArch64/GlobalISel/legalize-vector-ctpop.mir
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
Commit 75f3beeedf6343e2ce1e8143e0d037d96cdab0b2 by czhengsz
[Debug-Info] make DIE attributes generation under strict DWARF control

Reviewed By: dblaikie

Differential Revision: https://reviews.llvm.org/D101024
The file was modifiedllvm/lib/CodeGen/AsmPrinter/DwarfUnit.h
The file was modifiedllvm/test/DebugInfo/PowerPC/strict-dwarf.ll
Commit 72797dedb720fae22682fc884cbf741c5a2066c2 by i
[sanitizer] Use size_t on g_tls_size to fix build on x32

On x32 size_t == unsigned int, not unsigned long int:

../../../../../src-master/libsanitizer/sanitizer_common/sanitizer_linux_libcdep.cpp: In function ??void __sanitizer::InitTlsSize()??:
../../../../../src-master/libsanitizer/sanitizer_common/sanitizer_linux_libcdep.cpp:209:55: error: invalid conversion from ??__sanitizer::uptr*?? {aka ??long unsigned int*??} to ??size_t*?? {aka ??unsigned int*??} [-fpermissive]
  209 |   ((void (*)(size_t *, size_t *))get_tls_static_info)(&g_tls_size, &tls_align);
      |                                                       ^~~~~~~~~~~
      |                                                       |
      |                                                       __sanitizer::uptr* {aka long unsigned int*}

by using size_t on g_tls_size.  This is to fix:

https://bugs.llvm.org/show_bug.cgi?id=50332

Reviewed By: MaskRay

Differential Revision: https://reviews.llvm.org/D102446
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_linux_libcdep.cpp
Commit ab6a609d961181bbac0d1ea0a830061049990020 by aeubanks
[test] Fix new-pm-lto-defaults.ll to work on all platforms

https://lab.llvm.org/buildbot/#/builders/119/builds/3775/steps/8/logs/FAIL__LLVM__new-pm-lto-defaults_ll

Followup to D102345.
The file was modifiedllvm/test/Other/new-pm-lto-defaults.ll
Commit 9567131d03650bbaa82251f173bd6959e04d471d by peter
scudo: Check for UAF in ring buffer before OOB in more distant blocks.

It's more likely that we have a UAF than an OOB in blocks that are
more than 1 block away from the fault address, so the UAF should
appear first in the error report.

Differential Revision: https://reviews.llvm.org/D102379
The file was modifiedcompiler-rt/lib/scudo/standalone/combined.h
Commit f79929aceae966f9419cfc00c275e5e60bd0ee54 by peter
scudo: Fix MTE error reporting for zero-sized allocations.

With zero-sized allocations we don't actually end up storing the
address tag to the memory tag space, so store it in the first byte of
the chunk instead so that we can find it later in getInlineErrorInfo().

Differential Revision: https://reviews.llvm.org/D102442
The file was modifiedcompiler-rt/lib/scudo/standalone/combined.h
Commit 61484762e9e95aa430083ceb5bd53fe0c849728e by czhengsz
[Debug-Info] change Tag type to dwarf::Tag for createAndAddDIE; NFC

Reviewed By: dblaikie

Differential Revision: https://reviews.llvm.org/D102207
The file was modifiedllvm/include/llvm/IR/DebugInfoMetadata.h
The file was modifiedllvm/lib/CodeGen/AsmPrinter/CodeViewDebug.cpp
The file was modifiedllvm/lib/CodeGen/AsmPrinter/DwarfUnit.cpp
The file was modifiedllvm/lib/CodeGen/AsmPrinter/DwarfUnit.h
Commit 2ca887de6e3c83f77e3ccde172ff55042cece6ab by springerm
[mlir] VectorToSCF target rank is a pass option

Make "target rank" a pass option of VectorToSCF.

Depends On D102101

Reviewed By: nicolasvasilache

Differential Revision: https://reviews.llvm.org/D102123
The file was modifiedmlir/lib/Conversion/VectorToSCF/VectorToSCF.cpp
The file was modifiedmlir/include/mlir/Conversion/Passes.td
The file was modifiedmlir/include/mlir/Conversion/VectorToSCF/VectorToSCF.h
Commit c76e3c319ebfeecbc2814ae7ac44516b5f0b4027 by Lang Hames
[ORC] Remove some stale unit test utils.

This code was used to test ORCv1, which has been removed. It is not useful for
testing ORCv2.
The file was modifiedllvm/unittests/ExecutionEngine/Orc/OrcTestCommon.h
Commit 527bd6dc1cc1a9ca14f40ef4eb5b5c1493da43b0 by Lang Hames
[ORC] Remove unused RTDyldObjectLinkingLayerExecutionTest class from unit test.
The file was modifiedllvm/unittests/ExecutionEngine/Orc/RTDyldObjectLinkingLayerTest.cpp
Commit 65736ac439beb12313d76c5b8bda12b3d0f469da by Lang Hames
[ORC] Remove the OrcExecutionTest class. It is no longer used.
The file was modifiedllvm/unittests/ExecutionEngine/Orc/OrcTestCommon.h
Commit 23a84e1c602c9ed42f51653805ce9e7f4d49be2a by jurahul
[MLIR] Fix build failures due to unused variables in non-debug builds.

Differential Revision: https://reviews.llvm.org/D102458
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/ComprehensiveBufferize.cpp
Commit a088bed4e3b572f8a3f8a1f7a41942f3005e4811 by springerm
[mlir] VectorToSCF cleanup

Group functions/structs in namespaces for better code readability.

Depends On D102123

Reviewed By: nicolasvasilache

Differential Revision: https://reviews.llvm.org/D102124
The file was modifiedmlir/lib/Conversion/VectorToSCF/VectorToSCF.cpp
Commit ee23f8b36f2c620f54fe5cbd74cbf930cb67c6fb by rnk
[COFF] Remove a truncation assertion from setRVA

LLD already produces a nice error message when sections exceed 4GB, and
this setRVA assertion causes LLD to crash instead of diagnosing the
error properly.

No test because we don't want slow tests that create 4GB files.
The file was modifiedlld/COFF/Chunks.h
Commit d2f4b7d77828dba831f4b7429a7c970d71eb853b by rnk
Use enum comparison instead of generated switch/case, NFC

Clang's coverage data for auto-generated switch cases is really, really
large. Before this change, when I enable code coverage, SemaDeclAttr.obj
is 4.0GB. Naturally, this fails to link.

Replacing the RISCV builtin id check with a comparison reduces object
file size from 4.0GB to 330MB. Replacing the AArch64 SVE range check
reduces the size again down to 17MB, which is reasonable.

I think the RISCV switch is larger in coverage data because it uses more
levels of macro expansion, while the SVE intrinsics only use one. In any
case, please try to avoid switches with 1000+ cases, they usually don't
optimize well.
The file was modifiedclang/lib/Sema/SemaDeclAttr.cpp
Commit 9cf6ff7affad4cd1f3d4d81da64356cb076b0303 by carl.ritson
[AMDGPU] Do not clause NSA instructions

To ensure correct behaviour NSA instructions should not be claused.

Reviewed By: foad

Differential Revision: https://reviews.llvm.org/D102211
The file was modifiedllvm/lib/Target/AMDGPU/GCNSubtarget.h
The file was modifiedllvm/test/CodeGen/AMDGPU/hard-clauses.mir
The file was modifiedllvm/lib/Target/AMDGPU/SIInsertHardClauses.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPU.td
The file was modifiedllvm/test/CodeGen/AMDGPU/cluster_stores.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
Commit 261d6e05d5574bec753ea6b7e9a7f99229927753 by i
[sanitizer] Simplify __sanitizer::BufferedStackTrace::UnwindImpl implementations

Intended to be NFC. D102046 relies on the refactoring for stack boundaries.
The file was modifiedcompiler-rt/lib/msan/msan.cpp
The file was modifiedcompiler-rt/lib/asan/asan_stack.cpp
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_stack_trace.cpp
The file was modifiedcompiler-rt/lib/ubsan/ubsan_diag_standalone.cpp
The file was modifiedcompiler-rt/lib/lsan/lsan.cpp
Commit 9099c9ef78c01145f9cf93671081409a8c4c0394 by Lang Hames
[JITLink] Fix missing 'static' keyword in unit test.
The file was modifiedllvm/unittests/ExecutionEngine/JITLink/LinkGraphTests.cpp
Commit 0fda4c4745b81e8a0eed2b80b0b03f33c16c2b99 by Lang Hames
[ORC] Add support for adding LinkGraphs directly to ObjectLinkingLayer.

This is separate from (but builds on) the support added in ec6b71df70a for
emitting LinkGraphs in the context of an active materialization. This commit
makes LinkGraphs a first-class data structure with features equivalent to
object files within ObjectLinkingLayer.
The file was modifiedllvm/lib/ExecutionEngine/Orc/ObjectLinkingLayer.cpp
The file was addedllvm/unittests/ExecutionEngine/Orc/ObjectLinkingLayerTest.cpp
The file was modifiedllvm/include/llvm/ExecutionEngine/Orc/ObjectLinkingLayer.h
The file was modifiedllvm/unittests/ExecutionEngine/Orc/CMakeLists.txt
Commit de115c3fb25f812ac43a5e1c7986b521ab5847c2 by llvmgnsyncbot
[gn build] Port 0fda4c4745b8
The file was modifiedllvm/utils/gn/secondary/llvm/unittests/ExecutionEngine/Orc/BUILD.gn
Commit c82a0ae70e280c1c40b1af09ef275ddc7ed4254d by Lang Hames
[ORC] Add JITLink dependence for ObjectLinkingLayerTest.

This aims to fix the failure at
https://lab.llvm.org/buildbot/#/builders/61/builds/9590.
The file was modifiedllvm/unittests/ExecutionEngine/Orc/CMakeLists.txt
Commit f7cb654763ec353da56702f4f34ddc3570fb709a by david.green
[DSE] Move isOverwrite into DSEState. NFC

This moves the isOverwrite function into the DSEState so that it can
share the analyses and members from the state.

A few extra loop tests were also added to test stores in and around
multi block loops for D100464.
The file was modifiedllvm/lib/Transforms/Scalar/DeadStoreElimination.cpp
The file was modifiedllvm/test/Transforms/DeadStoreElimination/multiblock-loops.ll
Commit fdae3fc8b3e9570073e7b6ae803195195fbf8bc2 by daniil.fukalov
[GVN] Clobber partially aliased loads.

Use offsets stored in `AliasResult` implemented in D98718.

Updated with fix of issue reported in https://reviews.llvm.org/D95543#2745161

Reviewed By: nikic

Differential Revision: https://reviews.llvm.org/D95543
The file was modifiedllvm/include/llvm/Analysis/MemoryDependenceAnalysis.h
The file was modifiedllvm/test/Transforms/GVN/PRE/rle.ll
The file was modifiedllvm/lib/Analysis/MemoryDependenceAnalysis.cpp
The file was modifiedllvm/lib/Transforms/Scalar/GVN.cpp
Commit 444f02d73c6d21bf9fe990ee922d995a33ef8de5 by alexey.bader
New tag for ittapi - fix an error related to cross-compiling ITTAPI in LLVM with mingw

Fix was implemented in the ittap repo to solve an error about cross-compiling ITTAPI in LLVM with mingw.
The problem occurred in the cross-compilation environment for Julia's dependencies.
The corresponding issue item in ittapi repo: https://github.com/intel/ittapi/issues/19
A new tag was created in ittapi repo for that fix.

This patch contains changes to update the ittapi tag in LLVM.

Reviewed By: bader

Differential Revision: https://reviews.llvm.org/D102471
The file was modifiedllvm/lib/ExecutionEngine/IntelJITEvents/CMakeLists.txt
Commit 2db090a2ebd76f120bfae4fbe4b7241667aa585e by david.spickett
[llvm][AsmPrinter] Restore source location to register clobber warning

Since 5de2d189e6ad466a1f0616195e8c524a4eb3cbc0 this particular warning
hasn't had the location of the source file containing the inline
assembly.

Fix this by reporting via LLVMContext. Which means that we no longer
have the "instantiated into assembly here" lines but they were going to
point to the start of the inline asm string anyway.

This message is already tested via IR in llvm. However we won't have
the required location info there so I've added a C file test in clang
to cover it.
(though strictly, this is testing llvm code)

Reviewed By: ychen

Differential Revision: https://reviews.llvm.org/D102244
The file was addedclang/test/Misc/inline-asm-clobber-warning.c
The file was modifiedllvm/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp
Commit 72d570ca085c809edd70d355cad7129092afbf90 by david.stuttard
[AMDGPU][AsmParser/Disassembler] Correct A16 and G16 handling

A16 support for image instructions assembly/disassembly (gfx10) was missing

Also refactor MIMG op addr size calcs to common function

We'd got 3 places where the same operation was being done.

One test is now marked XFAIL until a related codegen patch is in place

Differential Revision: https://reviews.llvm.org/D102231

Change-Id: I7e86e730ef8c71901457855cba570581f4f576bb
The file was modifiedllvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.cpp
The file was addedllvm/test/MC/Disassembler/AMDGPU/mimg_gfx10.txt
The file was modifiedllvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
The file was modifiedllvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.a16.dim.ll
The file was modifiedllvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
The file was modifiedllvm/lib/Target/AMDGPU/MIMGInstructions.td
The file was modifiedllvm/test/MC/AMDGPU/gfx10_asm_mimg.s
Commit 31b62aa162b464efadef942a801706127dd8a443 by david.stuttard
[AMDGPU] Fix codegen of image intrinsics for g16 and a16

For gfx10 gradient (g16) and address (a16) can be independent. Previous
implementation assumed that a16 implied g16.

There are some other changes that fix the verification (as well as asm/disasm)
that are required for the included test to pass - the XFAIL will be removed in
those changes.

This also includes required fixes for GlobalISel

Differential Revision: https://reviews.llvm.org/D102066

Change-Id: I7d171cc90994de05f41669b66a6d0ffa2ed05d09
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
The file was addedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.g16.a16.dim.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.a16.dim.ll
The file was modifiedllvm/lib/Target/AMDGPU/SIISelLowering.cpp
Commit 4763c8c9e3c7ef2946fa575d5c6bf8dd7fb88639 by shivam98.tkg
[docs] Added llvm/cmake section

Added information about the cmake inside llvm.

Reviewed By: xgupta, jroelofs

Differential Revision: https://reviews.llvm.org/D101925
The file was modifiedllvm/docs/GettingStarted.rst
Commit a9fb321a67943b9fffac6ff2d56ad5acb458b4f4 by lebedev.ri
[NFC][X86][MCA] AMD Zen 3: add same-reg AVX XMM VXORPS tests
The file was addedllvm/test/tools/llvm-mca/X86/Znver3/zero-idioms-avx-xmm.s
Commit 26c1bffe675747d90513033f773c0aef63172608 by lebedev.ri
[X86] AMD Zen 3: same-reg AVX XMM VXORPS is a zero-cycle(!) dep-breaking zero-idiom

Unlike it's legacy SSE XMM XORPS version, which measures as being 1-cycle,
this one is certainly a zero-cycle instruction, in addition to both of them
being dependency breaking.

As confirmed by exegesis measurements, and ref docs.
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver3/zero-idioms-avx-xmm.s
The file was modifiedllvm/lib/Target/X86/X86ScheduleZnver3.td
Commit 2a7c52ff7f8345cbf9956ddbe289326bdde0589b by lebedev.ri
[NFC][X86][MCA] AMD Zen 3: add same-reg AVX YMM VXORPS tests
The file was addedllvm/test/tools/llvm-mca/X86/Znver3/zero-idioms-avx-ymm.s
Commit 59554c01ab7e3f6a9316bbac83544f10f742fa44 by lebedev.ri
[X86] AMD Zen 3: same-reg AVX YMM VXORPS is a zero-cycle(!) dep-breaking zero-idiom

As confirmed by exegesis, and ref docs.
The file was modifiedllvm/lib/Target/X86/X86ScheduleZnver3.td
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver3/zero-idioms-avx-ymm.s
Commit fdc65e46b618acdb06d2bc59e57325b0112c3f71 by lebedev.ri
[NFC][X86][MCA] AMD Zen 3: add same-reg SSE XMM XORPD tests
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver3/zero-idioms-sse-xmm.s
Commit 57eee56d0a9783e5fae7030bf732ffeadf1180e6 by lebedev.ri
[NFC][X86][MCA] AMD Zen 3: add same-reg AVX XMM VXORPD tests
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver3/zero-idioms-avx-xmm.s
Commit 3567c7eda1fce98dd33341002c2062a2338761df by lebedev.ri
[NFC][X86][MCA] AMD Zen 3: add same-reg AVX YMM VXORPD tests
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver3/zero-idioms-avx-ymm.s
Commit 9c596bc5416a16247c4dfb4a564d93c6cb97fb9f by lebedev.ri
[X86] AMD Zen 3: same-reg SSE XMM XORPD is a 1-cycle(!) dep-breaking zero-idiom

Same as with it's float friend, unlike their AVX versions.
As confirmed by exegesis, and ref docs.
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver3/zero-idioms-sse-xmm.s
The file was modifiedllvm/lib/Target/X86/X86ScheduleZnver3.td
Commit 336b9dbe88c1f44e16bf98113e821b4eddcb0d0d by lebedev.ri
[X86] AMD Zen 3: same-reg AVX XMM VXORPD is a zero-cycle(!) dep-breaking zero-idiom

As confirmed by exegesis measurements, and ref docs.
The file was modifiedllvm/lib/Target/X86/X86ScheduleZnver3.td
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver3/zero-idioms-avx-xmm.s
Commit 43a7f130a7440f2c5eaa30faf69b90e2a9c571a0 by lebedev.ri
[X86] AMD Zen 3: same-reg AVX YMM VXORPD is a zero-cycle(!) dep-breaking zero-idiom

As confirmed by exegesis measurements, and ref docs.
The file was modifiedllvm/lib/Target/X86/X86ScheduleZnver3.td
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver3/zero-idioms-avx-ymm.s
Commit c12c8124e14217779eb5b8d3a2a92a6469a799e7 by martin
[libcxx] [test] Change the generic_string_alloc test to test conversions to all char types

On windows, the native path char type is wchar_t - therefore, this test
didn't actually do the conversion that the test was supposed to exercise.

The charset conversions on windows do cause extra allocations outside of
the provided allocator though, so that bit of the test has to be waived
now that the test actually does something. (Other tests have similar
TEST_NOT_WIN32() for allocation checks for charset conversions.)

Also fix a typo, and amend the path.native.obs/string_alloc test to
test char8_t, too.

Differential Revision: https://reviews.llvm.org/D102360
The file was modifiedlibcxx/test/std/input.output/filesystems/class.path/path.member/path.generic.obs/generic_string_alloc.pass.cpp
The file was modifiedlibcxx/test/std/input.output/filesystems/class.path/path.member/path.native.obs/string_alloc.pass.cpp
Commit 10798709713a9b5d4ff8d8f5961b3c2fdb81d887 by alexandros.lamprineas
[llvm-mc][AArch64] HINT instruction disassembled as BTI

The Arm Architecture Reference Manual says that the SystemHintOp_BTI
opcode is prefered when CRm:op2 matches 0100:xx0, but llvm-mc
currently accepts 0100:xxx, which isn't right.

Differential Revision: https://reviews.llvm.org/D102415
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrFormats.td
The file was modifiedllvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
The file was modifiedllvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
The file was modifiedllvm/test/MC/Disassembler/AArch64/armv8.5a-bti.txt
The file was modifiedllvm/lib/Target/AArch64/AArch64SystemOperands.td
Commit 7f81c5a5bae8329379b226d4efff6a44dfdeece9 by jay.foad
[AMDGPU] getMemOperandsWithOffset: add vaddr operand for stack access BUF instructions

A consequence is that checkInstOffsetsDoNotOverlap can now distinguish
sp+offset from fp+offset, so it knows that it shouldn't try to work out
whether the accesses overlap just by comparing the offsets. For example
in these two instructions:

MIR:
BUFFER_STORE_DWORD_OFFSET %0:vgpr_32(s32), $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into stack + 4, addrspace 5)
%4:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN %stack.0.alloca, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, 0, 0, 0, implicit $exec :: (load 4 from `i8 addrspace(5)* undef`, addrspace 5)

ISA:
buffer_store_dword v0, off, s[0:3], s32 offset:4
buffer_load_dword v0, off, s[0:3], s34

Differential Revision: https://reviews.llvm.org/D73957
The file was modifiedllvm/test/CodeGen/AMDGPU/call-argument-types.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/amdpal-callable.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.load.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.load.ll
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.tbuffer.load.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/salu-to-valu.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll
Commit 459c48e04f25a40a81e9e11ccb9c17a88dc39999 by sander.desmalen
NFCI: Remove VF argument from isScalarWithPredication

As discussed in D102437, the VF argument to isScalarWithPredication
seems redundant, so this is intended to be a non-functional change. It
seems wrong to query the widening decision at this point. Removing the
operand and code to get the widening decision causes no unit/regression
tests to fail. I've also found no issues running the LLVM test-suite.

This subsequently removes the VF argument from isPredicatedInst as well,
since it is no longer required.
The file was modifiedllvm/lib/Transforms/Vectorize/LoopVectorize.cpp
Commit 4789fc75d3501f14cfbd5b102f173721d498ff58 by Tim Northover
AArch64: support i128 cmpxchg in GlobalISel.

There are three essentially different cases to handle:

  * -O1, no LSE. The IR is expanded to ldxp/stxp and we need patterns to select
    them.
  * -O0, no LSE. We get G_ATOMIC_CMPXCHG, and need to produce CMP_SWAP_N
    pseudos. The registers are all 64-bit so this is easy.
  * LSE. We get G_ATOMIC_CMPXCHG and need to produce a CASP instruction with
    XSeqPair registers.

The last case is by far the hardest, and and adds 128-bit GPR support as a
byproduct.
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrGISel.td
The file was modifiedllvm/lib/Target/AArch64/AArch64GenRegisterBankInfo.def
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64RegisterBanks.td
The file was addedllvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic-128.ll
The file was addedllvm/test/CodeGen/AArch64/GlobalISel/legalize-cmpxchg-128.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.h
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.h
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/regbank-extract.mir
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
Commit e51ef7f0706ada40d33819d1b3bdca2351e4fb4e by mkazantsev
[Test] Add test on missing opportunity in Loop Deletion

We can break the backedge in some cases when we can evaluate some of the
values and conditions on the 1st iteration.
The file was addedllvm/test/Transforms/LoopDeletion/eval_first_iteration.ll
Commit 5ed56a821c0622869739a3ae752eea97a1ee1f48 by llvm-dev
[X86] Try to pass DebugLoc by const-ref to avoid costly TrackingMDNodeRef copies. NFCI.
The file was modifiedllvm/lib/Target/X86/X86CmovConversion.cpp
The file was modifiedllvm/lib/Target/X86/X86OptimizeLEAs.cpp
The file was modifiedllvm/lib/Target/X86/X86PadShortFunction.cpp
The file was modifiedllvm/lib/Target/X86/X86FloatingPoint.cpp
The file was modifiedllvm/lib/Target/X86/X86CallFrameOptimization.cpp
The file was modifiedllvm/lib/Target/X86/X86WinAllocaExpander.cpp
The file was modifiedllvm/lib/Target/X86/X86FrameLowering.cpp
The file was modifiedllvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp
Commit 207cdd7ed9fc545a615d9bb244a7d9a2158e61ed by anton.a.afanasyev
[SLP] Fix spill cost computation for insertelement tree node

This is follow up for D98714, bugfixing.
The file was modifiedllvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Commit 7ba0e99aec6e461f41ebad608893f8c280836165 by flo
[VectorCombine] Add tests with assumes involvind variable index.

Add test cases with variable indices together with assumes guaranteeing
that the indices are valid.
The file was modifiedllvm/test/Transforms/VectorCombine/load-insert-store.ll
The file was modifiedllvm/test/Transforms/VectorCombine/AArch64/load-extractelement-scalarization.ll
Commit 78c8451cd7b1d789fdd81beac0d3f7172bdce31c by llvm-dev
[Local] collectBitParts - reduce maximum recursion depth.

As noticed on D90170, the recursion depth for matching a maximum of a i128 bitwidth was too high.

@lebedev.ri mentioned that we can probably do better by limiting the number of collected Values instead of just depth, but I'll look at that later.
The file was modifiedllvm/lib/Transforms/Utils/Local.cpp
Commit 079bbea2b20dbfd24e4df654bae1c4324dcde754 by llvm-dev
[Local] collectBitParts - for bswap-only matches, limit shift amounts to whole bytes to reduce compile time.
The file was modifiedllvm/lib/Transforms/Utils/Local.cpp
Commit ea0eec69f16e0f1b00fec413986e4e44f6f627fa by Tim Northover
IR+AArch64: add a "swiftasync" argument attribute.

This extends any frame record created in the function to include that
parameter, passed in X22.

The new record looks like [X22, FP, LR] in memory, and FP is stored with 0b0001
in bits 63:60 (CodeGen assumes they are 0b0000 in normal operation). The effect
of this is that tools walking the stack should expect to see one of three
values there:

  * 0b0000 => a normal, non-extended record with just [FP, LR]
  * 0b0001 => the extended record [X22, FP, LR]
  * 0b1111 => kernel space, and a non-extended record.

All other values are currently reserved.

If compiling for arm64e this context pointer is address-discriminated with the
discriminator 0xc31a and the DB (process-specific) key.

There is also an "i8** @llvm.swift.async.context.addr()" intrinsic providing
front-ends access to this slot (and forcing its creation initialized to nullptr
if necessary).
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrFormats.td
The file was modifiedllvm/test/Bitcode/compatibility.ll
The file was addedllvm/test/Verifier/swiftasync.ll
The file was modifiedllvm/include/llvm/CodeGen/TargetCallingConv.h
The file was modifiedllvm/lib/Target/AArch64/AArch64FrameLowering.cpp
The file was modifiedllvm/include/llvm/Bitcode/LLVMBitCodes.h
The file was modifiedllvm/lib/Target/AArch64/AArch64FastISel.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrInfo.cpp
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
The file was addedllvm/test/CodeGen/AArch64/swift-async-reg.ll
The file was modifiedllvm/lib/Bitcode/Writer/BitcodeWriter.cpp
The file was modifiedllvm/lib/CodeGen/PrologEpilogInserter.cpp
The file was modifiedllvm/lib/CodeGen/SelectionDAG/FastISel.cpp
The file was modifiedllvm/include/llvm/IR/Attributes.td
The file was modifiedllvm/include/llvm/CodeGen/TargetLowering.h
The file was modifiedllvm/lib/Bitcode/Reader/BitcodeReader.cpp
The file was modifiedllvm/docs/LangRef.rst
The file was modifiedllvm/lib/AsmParser/LLLexer.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64MachineFunctionInfo.h
The file was modifiedllvm/lib/Transforms/Utils/CodeExtractor.cpp
The file was addedllvm/test/CodeGen/AArch64/swift-async-unwind.ll
The file was modifiedllvm/lib/AsmParser/LLParser.cpp
The file was modifiedllvm/lib/IR/Verifier.cpp
The file was modifiedllvm/lib/CodeGen/GlobalISel/CallLowering.cpp
The file was modifiedllvm/include/llvm/CodeGen/TargetFrameLowering.h
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
The file was addedllvm/test/CodeGen/AArch64/swift-async.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp
The file was modifiedllvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
The file was modifiedllvm/test/Bitcode/attributes.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64CallingConvention.td
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
The file was modifiedllvm/include/llvm/IR/Intrinsics.td
The file was modifiedllvm/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp
The file was modifiedllvm/lib/IR/Attributes.cpp
The file was modifiedllvm/include/llvm/AsmParser/LLToken.h
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrInfo.td
The file was modifiedllvm/lib/Target/AArch64/AArch64FrameLowering.h
The file was modifiedllvm/include/llvm/Target/TargetCallingConv.td
Commit 8e35a18e4ad416c48c8e48492676fb189ee2c720 by aheejin
[WebAssembly] Support Emscripten EH/SjLj in Wasm64

In wasm64, the signatures of some library functions and global variables
defined in Emscripten change:
- `emscripten_longjmp`: `(i32, i32) -> ()` -> `(i64, i32) -> ()`
  This changes because the first argument is the address of a memory
  buffer. This in turn causes more changes below.
- `setThrew`: `(i32, i32) -> ()` -> `(i64, i32) -> ()`
  `emscripten_longjmp` calls `setThrew` with the i64 buffer argument as
  the first parameter.
- `__THREW__` (global var): `i32` to `i64`
  `setThrew`'s first argument is set to this `__THREW__` variable, so it
  should change to i64 as well.
- `testSetjmp`: `(i32, i32*, i32) -> (i32)` -> `(i64, i32*, i32) -> (i32)`
  In the code transformation done in this pass, the value of `__THREW__`
  is passed as the first parameter of `testSetjmp`.

This patch creates some helper functions to easily get types that become
different depending on the wasm32/wasm64, and uses them to change
various function signatures and code transformations. Also updates the
tests with WASM32/WASM64 check lines.

(Untested) Emscripten side patch: https://github.com/emscripten-core/emscripten/pull/14108

Reviewed By: aardappel

Differential Revision: https://reviews.llvm.org/D101985
The file was modifiedllvm/test/CodeGen/WebAssembly/lower-em-ehsjlj-options.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/lower-em-sjlj.ll
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyLowerEmscriptenEHSjLj.cpp
The file was modifiedllvm/test/CodeGen/WebAssembly/lower-em-exceptions.ll
Commit 71fbfb499aaaefbb2b24e5652df5525684766bfc by aheejin
[WebAssembly] Omit DBG_VALUE after terminator

When a stackified variable has an associated `DBG_VALUE` instruction,
DebugFixup pass adds a `DBG_VALUE` instruction after the stackified
value's last use to clear the variable's debug range info. But when the
last use instruction is a terminator, it can cause a verification
failure (when run with `-verify-machineinstrs`) because there are no
instructions allowed after a terminator.

For example:
```
%myvar = ...
DBG_VALUE target-index(wasm-operand-stack), $noreg, !"myvar", ...
BR_IF 0, %myvar, ...
DBG_VALUE $noreg, $noreg, !"myvar", ...
```
In this test, `%myvar` is stackified, so the first `DBG_VALUE`
instruction's first operand has changed to `wasm-operand-stack` to
denote it. And an additional `DBG_VALUE` instruction is added after its
last use, `BR_IF`, to signal variable `myvar` is not in the operand
stack anymore. But because the `DBG_VALUE` instruction is added after
the `BR_IF`, a terminator, it fails MachineVerifier.

`DBG_VALUE` instructions are used in `DbgEntityHistoryCalculator` to
compute value ranges to emit DWARF info, and it turns out the
`DbgEntityHistoryCalculator` terminates ranges at the end of a BB, so we
don't need to emit `DBG_VALUE` after a terminator.

Fixes https://bugs.llvm.org/show_bug.cgi?id=50175.

Reviewed By: dschuff

Differential Revision: https://reviews.llvm.org/D102309
The file was modifiedllvm/test/CodeGen/WebAssembly/stackified-debug.ll
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyDebugFixup.cpp
Commit f82966d19a8bb8531f71913737fcc751bb6ae3e2 by sander.desmalen
[LoopVectorizationLegality] NFC: Mark some interfaces as 'const'

This patch marks blockNeedsPredication, isConsecutivePtr, isMaskRequired
and getSymbolicStrides as 'const'.
The file was modifiedllvm/include/llvm/Transforms/Vectorize/LoopVectorizationLegality.h
The file was modifiedllvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp
Commit a657808948f2aa886f7f3321bc29c5458091cf1b by lebedev.ri
[NFC][X86][MCA] AMD Zen 3: add same-reg SSE XMM ANDNPS tests
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver3/zero-idioms-sse-xmm.s
Commit a57006d627d312ae0abb9d90a94f023576cf8886 by lebedev.ri
[NFC][X86][MCA] AMD Zen 3: add same-reg AVX XMM VANDNPS tests
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver3/zero-idioms-avx-xmm.s
Commit c79c7bb980054fa7c1ebe5aae0e90755fe9a1314 by lebedev.ri
[NFC][X86][MCA] AMD Zen 3: add same-reg AVX YMM VANDNPS tests
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver3/zero-idioms-avx-ymm.s
Commit f38dcbecb643e30931b56bbcf37254477eac3977 by lebedev.ri
[X86] AMD Zen 3: same-reg SSE XMM ANDNPS is a 1-cycle(!) dep-breaking zero-idiom

Same as SSE XMM XORPS/XORPD, it is not zero-cycle, even though it breaks the deps.
As confirmed by the exegesis measurements, and ref docs.
The file was modifiedllvm/lib/Target/X86/X86ScheduleZnver3.td
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver3/zero-idioms-sse-xmm.s
Commit fd4cbc822b6d4c8ce0e6e162e1c0648686e5a834 by lebedev.ri
[X86] AMD Zen 3: same-reg AVX XMM VANDNPS is a zero-cycle(!) dep-breaking zero-idiom

As confirmed by exegesis measurements, and ref docs.
The file was modifiedllvm/lib/Target/X86/X86ScheduleZnver3.td
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver3/zero-idioms-avx-xmm.s
Commit d8a595b81c114d2c8251790d2d2e55f6659db3bd by lebedev.ri
[X86] AMD Zen 3: same-reg AVX YMM VANDNPS is a zero-cycle(!) dep-breaking zero-idiom

As confirmed by exegesis measurements, and ref docs.
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver3/zero-idioms-avx-ymm.s
The file was modifiedllvm/lib/Target/X86/X86ScheduleZnver3.td
Commit 055fa84cd88fe56161d7a68d1ed0648c4bf2d35d by lebedev.ri
[NFC][X86][MCA] AMD Zen 3: add same-reg SSE XMM ANDNPD tests
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver3/zero-idioms-sse-xmm.s
Commit 0b7e52e7259ca82242c61b0df6336d03ad50b62d by lebedev.ri
[NFC][X86][MCA] AMD Zen 3: add same-reg AVX XMM VANDNPD tests
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver3/zero-idioms-avx-xmm.s
Commit 3221e06e9b8559e8b26a9f4f0a6d1a39c29bc226 by lebedev.ri
[NFC][X86][MCA] AMD Zen 3: add same-reg AVX YMM VANDNPD tests
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver3/zero-idioms-avx-ymm.s
Commit 38ceb46fb03d10e24b83d2261ad70efd555067a2 by lebedev.ri
[X86] AMD Zen 3: same-reg SSE XMM ANDNPD is a 1-cycle(!) dep-breaking zero-idiom

As confirmed by exegesis measurements, and ref docs.
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver3/zero-idioms-sse-xmm.s
The file was modifiedllvm/lib/Target/X86/X86ScheduleZnver3.td
Commit 17f99a8a41c0291081894354b454c16742c29787 by lebedev.ri
[X86] AMD Zen 3: same-reg AVX XMM VANDNPD is a zero-cycle(!) dep-breaking zero-idiom

As confirmed by exegesis measurements, and ref docs.
The file was modifiedllvm/lib/Target/X86/X86ScheduleZnver3.td
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver3/zero-idioms-avx-xmm.s
Commit 4af4afe014a70f6b57a083b0d5565773dae6b094 by lebedev.ri
[X86] AMD Zen 3: same-reg AVX YMM VANDNPD is a zero-cycle(!) dep-breaking zero-idiom

As confirmed by exegesis measurements, and ref docs.
The file was modifiedllvm/lib/Target/X86/X86ScheduleZnver3.td
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver3/zero-idioms-avx-ymm.s
Commit 6ec66f681c3763916933057849587a44cfb8e6da by jay.foad
[TableGen] Remove unneeded forward defs. NFC.
The file was modifiedllvm/include/llvm/Target/Target.td
The file was modifiedllvm/include/llvm/Target/TargetSchedule.td
Commit 01c90bbd4fd12aa86db4a47577addb47e6e84289 by djordje.todorovic
[Transforms][Debugify] Fix "Missing line" false alarm on PHI nodes

This is a fix for https://bugs.llvm.org/show_bug.cgi?id=49959

The "Missing line" false alarm was introduced in D75242.

Patch by Yilong Guo<yilong.guo@intel.com>

Differential Revision: https://reviews.llvm.org/D100446
The file was modifiedllvm/lib/Transforms/Utils/Debugify.cpp
The file was addedllvm/test/DebugInfo/debugify-ignore-phi.ll
Commit 0566f979619cf49a62804a7e3530438f1319fa7c by nathan
[clang][NFC] remove unused return value

In working on p0388 (ary[N] -> ary[] conversion), I discovered neither
use of UnwrapSimilarArrayTypes used the return value. So let's nuke
it.

Differential Revision: https://reviews.llvm.org/D102480
The file was modifiedclang/lib/AST/ASTContext.cpp
The file was modifiedclang/include/clang/AST/ASTContext.h
Commit 9dfd7f9b6775fb6d5e51285ae211b6a77b747d98 by spatel
[SDAG] reduce code duplication for extend_vec_inreg combines; NFC

These are identical so far, and I was looking at adding a fold
for a pattern with scalar_to_vector which would also nd up duplicated.
The file was modifiedllvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Commit 7cd2833311ab614775bc695e7bb808159a02e2a9 by nemanja.i.ibm
[PowerPC] Add vec_vupkhpx and vec_vupklpx for XL compatibility

These are old names for these functions that XL still supports.
The file was modifiedclang/test/CodeGen/builtins-ppc-altivec.c
The file was modifiedclang/lib/Headers/altivec.h
Commit 434b278cde81800eb23a0496d9f6abdbc30e15bc by dmitry.preobrazhensky
[AMDGPU][MC][NFC][DOC] Updated AMD GPU assembler syntax description.

Summary of changes:
- added description of GFX90A;
- minor bugfixing and improvements.
The file was addedllvm/docs/AMDGPU/gfx90a_msg.rst
The file was addedllvm/docs/AMDGPU/gfx90a_vaddr.rst
The file was addedllvm/docs/AMDGPU/gfx90a_vaddr_1.rst
The file was addedllvm/docs/AMDGPU/gfx90a_simm32_2.rst
The file was addedllvm/docs/AMDGPU/gfx90a_vdst_1.rst
The file was addedllvm/docs/AMDGPU/gfx90a_vdata_7.rst
The file was addedllvm/docs/AMDGPU/gfx90a_vdst_12.rst
The file was addedllvm/docs/AMDGPU/gfx90a_vdata_10.rst
The file was addedllvm/docs/AMDGPU/gfx90a_src_1.rst
The file was addedllvm/docs/AMDGPU/gfx90a_vaddr_4.rst
The file was addedllvm/docs/AMDGPU/gfx90a_src_11.rst
The file was addedllvm/docs/AMDGPU/gfx90a_ssrc_1.rst
The file was addedllvm/docs/AMDGPU/gfx90a_vdst_5.rst
The file was modifiedllvm/docs/AMDGPU/gfx10_offset_smem_buf.rst
The file was addedllvm/docs/AMDGPU/gfx90a_soffset_1.rst
The file was addedllvm/docs/AMDGPU/gfx90a_vaddr_2.rst
The file was addedllvm/docs/AMDGPU/gfx90a_waitcnt.rst
The file was addedllvm/docs/AMDGPU/gfx90a_hwreg.rst
The file was addedllvm/docs/AMDGPU/gfx90a_sdata_4.rst
The file was addedllvm/docs/AMDGPU/gfx90a_vsrc_2.rst
The file was addedllvm/docs/AMDGPU/gfx90a_src_6.rst
The file was addedllvm/docs/AMDGPU/gfx90a_sbase_2.rst
The file was addedllvm/docs/AMDGPU/gfx90a_vdst_14.rst
The file was addedllvm/docs/AMDGPU/gfx90a_vcc.rst
The file was addedllvm/docs/AMDGPU/gfx90a_sbase.rst
The file was addedllvm/docs/AMDGPU/gfx90a_vdata_6.rst
The file was addedllvm/docs/AMDGPU/gfx90a_vdst_17.rst
The file was addedllvm/docs/AMDGPU/gfx90a_vdata1_1.rst
The file was addedllvm/docs/AMDGPU/gfx90a_m_1.rst
The file was addedllvm/docs/AMDGPU/gfx90a_src.rst
The file was addedllvm/docs/AMDGPU/gfx90a_soffset.rst
The file was addedllvm/docs/AMDGPU/gfx90a_srsrc.rst
The file was addedllvm/docs/AMDGPU/gfx90a_m.rst
The file was addedllvm/docs/AMDGPU/gfx90a_simm32.rst
The file was addedllvm/docs/AMDGPU/gfx90a_fx_operand.rst
The file was addedllvm/docs/AMDGPU/gfx90a_sdst.rst
The file was addedllvm/docs/AMDGPU/gfx90a_type_deviation.rst
The file was addedllvm/docs/AMDGPU/gfx90a_src_9.rst
The file was addedllvm/docs/AMDGPU/gfx90a_vdata_3.rst
The file was addedllvm/docs/AMDGPU/gfx90a_vdata_9.rst
The file was addedllvm/docs/AMDGPU/gfx90a_sdst_6.rst
The file was addedllvm/docs/AMDGPU/gfx90a_src_5.rst
The file was addedllvm/docs/AMDGPU/gfx90a_vdst_13.rst
The file was addedllvm/docs/AMDGPU/gfx90a_ssrc_5.rst
The file was addedllvm/docs/AMDGPU/gfx90a_sdata_5.rst
The file was addedllvm/docs/AMDGPU/gfx90a_vsrc_3.rst
The file was addedllvm/docs/AMDGPU/gfx90a_saddr_1.rst
The file was addedllvm/docs/AMDGPU/gfx90a_vsrc_1.rst
The file was addedllvm/docs/AMDGPU/gfx90a_vdst_16.rst
The file was addedllvm/docs/AMDGPU/gfx90a_vsrc.rst
The file was modifiedllvm/docs/AMDGPUUsage.rst
The file was addedllvm/docs/AMDGPU/gfx90a_sdst_3.rst
The file was addedllvm/docs/AMDGPU/gfx90a_ssrc_4.rst
The file was addedllvm/docs/AMDGPU/gfx90a_simm32_1.rst
The file was addedllvm/docs/AMDGPU/gfx90a_vdata_4.rst
The file was modifiedllvm/docs/AMDGPUModifierSyntax.rst
The file was addedllvm/docs/AMDGPU/gfx90a_probe.rst
The file was addedllvm/docs/AMDGPU/gfx90a_imm16_1.rst
The file was addedllvm/docs/AMDGPU/gfx90a_sdst_4.rst
The file was modifiedllvm/docs/AMDGPUOperandSyntax.rst
The file was addedllvm/docs/AMDGPU/gfx90a_ssrc_2.rst
The file was addedllvm/docs/AMDGPU/gfx90a_imask.rst
The file was addedllvm/docs/AMDGPU/gfx90a_vdst_7.rst
The file was addedllvm/docs/AMDGPU/gfx90a_ssrc_3.rst
The file was addedllvm/docs/AMDGPU/gfx90a_sdst_7.rst
The file was addedllvm/docs/AMDGPU/gfx90a_ssrc_6.rst
The file was addedllvm/docs/AMDGPU/gfx90a_src_10.rst
The file was modifiedllvm/docs/AMDGPU/gfx10_offset_smem_plain.rst
The file was addedllvm/docs/AMDGPU/gfx90a_vdata1.rst
The file was addedllvm/docs/AMDGPU/gfx90a_vsrc_5.rst
The file was addedllvm/docs/AMDGPU/gfx90a_vdata0.rst
The file was addedllvm/docs/AMDGPU/gfx90a_dst.rst
The file was addedllvm/docs/AMDGPU/gfx90a_vdst_3.rst
The file was addedllvm/docs/AMDGPU/AMDGPUAsmGFX90a.rst
The file was addedllvm/docs/AMDGPU/gfx90a_src_8.rst
The file was addedllvm/docs/AMDGPU/gfx90a_vdst_9.rst
The file was addedllvm/docs/AMDGPU/gfx90a_vdst_19.rst
The file was addedllvm/docs/AMDGPU/gfx90a_imm16.rst
The file was addedllvm/docs/AMDGPU/gfx90a_vdst_15.rst
The file was addedllvm/docs/AMDGPU/gfx90a_sdata_2.rst
The file was addedllvm/docs/AMDGPU/gfx90a_vdst_4.rst
The file was addedllvm/docs/AMDGPU/gfx90a_vdata_5.rst
The file was addedllvm/docs/AMDGPU/gfx90a_imm16_2.rst
The file was addedllvm/docs/AMDGPU/gfx90a_opt.rst
The file was addedllvm/docs/AMDGPU/gfx90a_sdst_1.rst
The file was addedllvm/docs/AMDGPU/gfx90a_src_2.rst
The file was addedllvm/docs/AMDGPU/gfx90a_ssrc_7.rst
The file was addedllvm/docs/AMDGPU/gfx90a_ssrc_8.rst
The file was addedllvm/docs/AMDGPU/gfx90a_vdst_6.rst
The file was addedllvm/docs/AMDGPU/gfx90a_ssrc.rst
The file was addedllvm/docs/AMDGPU/gfx90a_vdst_8.rst
The file was addedllvm/docs/AMDGPU/gfx90a_label.rst
The file was addedllvm/docs/AMDGPU/gfx90a_vdata_8.rst
The file was addedllvm/docs/AMDGPU/gfx90a_vdata0_1.rst
The file was addedllvm/docs/AMDGPU/gfx90a_src_7.rst
The file was addedllvm/docs/AMDGPU/gfx90a_src_4.rst
The file was addedllvm/docs/AMDGPU/gfx90a_vdst_11.rst
The file was addedllvm/docs/AMDGPU/gfx90a_saddr.rst
The file was addedllvm/docs/AMDGPU/gfx90a_src_3.rst
The file was addedllvm/docs/AMDGPU/gfx90a_vaddr_3.rst
The file was addedllvm/docs/AMDGPU/gfx90a_vdst.rst
The file was addedllvm/docs/AMDGPU/gfx90a_sdata_1.rst
The file was addedllvm/docs/AMDGPU/gfx90a_vsrc_4.rst
The file was addedllvm/docs/AMDGPU/gfx90a_sdst_2.rst
The file was addedllvm/docs/AMDGPU/gfx90a_sdata.rst
The file was addedllvm/docs/AMDGPU/gfx90a_sdst_5.rst
The file was addedllvm/docs/AMDGPU/gfx90a_vdst_18.rst
The file was addedllvm/docs/AMDGPU/gfx90a_vdata.rst
The file was addedllvm/docs/AMDGPU/gfx90a_vdata_2.rst
The file was addedllvm/docs/AMDGPU/gfx90a_vdst_2.rst
The file was modifiedllvm/docs/AMDGPU/gfx9_offset_smem_plain.rst
The file was addedllvm/docs/AMDGPU/gfx90a_sdata_3.rst
The file was addedllvm/docs/AMDGPU/gfx90a_soffset_2.rst
The file was addedllvm/docs/AMDGPU/gfx90a_vaddr_5.rst
The file was addedllvm/docs/AMDGPU/gfx90a_ssamp.rst
The file was addedllvm/docs/AMDGPU/gfx90a_srsrc_1.rst
The file was modifiedllvm/docs/AMDGPU/gfx9_offset_smem_buf.rst
The file was addedllvm/docs/AMDGPU/gfx90a_vdata_1.rst
The file was addedllvm/docs/AMDGPU/gfx90a_vdst_10.rst
The file was addedllvm/docs/AMDGPU/gfx90a_sbase_1.rst
Commit 3d59f9d22440645ca0237dfc5d91ca09f749174b by david.candler
[ARM][AArch64] Correct __ARM_FEATURE_CRYPTO macro and crypto feature

This patch contains a couple of minor corrections to my previous
crypto patch:

Since both AArch32 and AArch64 are now correctly setting the aes and
sha2 features individually, it is not necessary to continue to check
the crypto feature when defining feature macros.

In the AArch32 driver, the feature vector is only modified when the
crypto feature is actually in the vector. If crypto is not present,
there is no need to split it and explicitly define crypto/sha2/aes.

Reviewed By: lenary

Differential Revision: https://reviews.llvm.org/D102406
The file was modifiedclang/lib/Driver/ToolChains/Arch/ARM.cpp
The file was modifiedclang/lib/Basic/Targets/ARM.cpp
The file was modifiedclang/lib/Basic/Targets/AArch64.cpp
Commit b41e1306b80f20a857f0e285e51ea453eb7888a1 by kai.wang
[RISCV] Add the DebugLoc parameter to getVLENFactoredAmount().

The MachineBasicBlock::iterator is continuously changing during
generating the frame handling instructions. We should use the DebugLoc
from the caller, instead of getting it from the changing iterator.

If the prologue instructions located in a basic block without any other
instructions after these prologue instructions, the iterator will be
updated to the boundary of the basic block and it is invalid to use the
iterator to access DebugLoc. This patch also fixes the crash when
accessing DebugLoc using the iterator.

Differential Revision: https://reviews.llvm.org/D102386
The file was modifiedllvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
The file was modifiedllvm/lib/Target/RISCV/RISCVFrameLowering.cpp
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfo.h
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfo.cpp
The file was addedllvm/test/CodeGen/RISCV/rvv/get-vlen-debugloc.mir
Commit 11b34e78c1e2fd5e7cec224d99400216334e2893 by david.green
[ARM] Define CPSR on MEMCPY pseudos

These pseudos are converted post-isel into t2WhileLoopStart and
t2LoopEnd/LoopDec instructions, which themselves are defined to clobber
CPSR. Doing the same with the MEMCPY nodes will make sure they are
scheduled correctly to not end up with incorrect uses.
The file was modifiedllvm/lib/Target/ARM/ARMISelLowering.cpp
The file was modifiedllvm/test/CodeGen/Thumb2/mve-tp-loop.ll
The file was modifiedllvm/test/CodeGen/Thumb2/mve-tp-loop.mir
The file was modifiedllvm/lib/Target/ARM/ARMInstrMVE.td
Commit ce76093c3c860599ceb3d588fb80700cd69f1b46 by david.green
[ARM] Expand predecessor search to multiple blocks when reverting WhileLoopStarts

We were previously only searching a single preheader for call
instructions when reverting WhileLoopStarts to DoLoopStarts. This
extends that to multiple blocks that can come up when, for example a
loop is expanded from a memcpy. It also expends the instructions from
just Call's to also include other LoopStarts, to catch other low
overhead loops in the preheader.

Differential Revision: https://reviews.llvm.org/D102269
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/memcall.ll
The file was addedllvm/test/CodeGen/Thumb2/LowOverheadLoops/wls-search-pred.mir
The file was modifiedllvm/lib/Target/ARM/MVETPAndVPTOptimisationsPass.cpp
Commit 810d4a6ff6d0b9c90f7720a7825a65f5356e4bba by david.spickett
[utils] Don't print username in arcanist clang format message

I didn't realise this message was also posted to the phabricator review.

Just say "the user's local path". "local" is the important part,
the username is not important.
The file was modifiedutils/arcanist/clang-format.sh
Commit ed339111bff690c6ba87d5e25c50bcad6793a309 by kadircet
[clangd] Always default to raw pch format

Clang would emit a fatal error when it encounters an unregistered PCH
format. This change ensures clangd will always use raw format no matter what
user specifies.

As side effects:

- serializing an AST in an unknown format might throw off build
systems. I suppose this would only be an issue when build system and clangd are
racing for same PCM modules, hopefully this should be rare and both clangd or
the build system should recover on the next run.

- whenever clang reads a serialized AST it seems to be checking for file
signature and emitting non-fatal errors. so this should be fine again.

The only other valid module format in clang is `obj` but it is part of codegen,
i don't think it is worth the dependency. Hence chosing to not register it, at
least yet.

Differential Revision: https://reviews.llvm.org/D102418
The file was modifiedclang-tools-extra/clangd/Compiler.cpp
The file was modifiedclang-tools-extra/clangd/unittests/ModulesTests.cpp
Commit 3f1c218318ed2e4f37d169f1bfbb39be657dc0b4 by listmail
[rs4gc] Strip memory related attributes consistently

I noticed that rs4gc is not stripping a number of memory aliasing related attributes. We do strip some from call sites, but don't strip the same ones from declarations or parameters.

Why do we need to strip these? Two answers:

    Safepoints conceptually read and write to the entire garbage collected heap in the physical model. We need this to preserve ordering of all loads and stores with respect to possible relocation.
    We can infer other attributes from these. For instance, readnone can imply both nofree and nosync. Both of which don't hold after physical rewriting.

Note: This exposed a latent issue which was fixed a couple weeks back in 01801d5274.

Differential Revision: https://reviews.llvm.org/D99802
The file was modifiedllvm/lib/Transforms/Scalar/RewriteStatepointsForGC.cpp
The file was modifiedllvm/test/Transforms/RewriteStatepointsForGC/strip-invalid-attributes.ll
Commit 90ffcb124566eba54e50ff29f479a6adcd726ae4 by bradley.smith
[AArch64][SVE] Add unpredicated vector BIC ISD node

Addition of this node allows us to better utilize the different forms of
the SVE BIC instructions, including using the alias to an AND (immediate).

Differential Revision: https://reviews.llvm.org/D101831
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
The file was modifiedllvm/lib/Target/AArch64/SVEInstrFormats.td
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp
The file was modifiedllvm/test/CodeGen/AArch64/sve-intrinsics-logical-imm.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
The file was modifiedllvm/test/CodeGen/AArch64/sve-intrinsics-unpred-form.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.h
Commit 4dd546131ad2749fbde3e048583cf29d615b9851 by benny.kra
Bump googletest to 1.8.1

We've accumulated a scary amount of local patches to this directory. I
tried to merge them all, but if your favorite change is missing please
reapply it manually (and send it upstream).
The file was modifiedllvm/utils/unittest/googlemock/src/gmock-internal-utils.cc
The file was modifiedllvm/utils/unittest/googletest/include/gtest/gtest-message.h
The file was modifiedllvm/utils/unittest/googletest/include/gtest/gtest-test-part.h
The file was modifiedllvm/utils/unittest/googletest/include/gtest/internal/gtest-tuple.h
The file was modifiedllvm/utils/unittest/googletest/include/gtest/gtest-typed-test.h
The file was modifiedllvm/utils/unittest/googlemock/src/gmock-all.cc
The file was modifiedllvm/utils/unittest/googlemock/include/gmock/internal/gmock-port.h
The file was modifiedllvm/utils/unittest/googletest/include/gtest/internal/gtest-internal.h
The file was modifiedllvm/utils/unittest/googlemock/include/gmock/gmock-spec-builders.h
The file was modifiedllvm/utils/unittest/googlemock/src/gmock.cc
The file was modifiedllvm/utils/unittest/googletest/README.LLVM
The file was modifiedllvm/utils/unittest/googletest/include/gtest/internal/custom/gtest-port.h
The file was modifiedllvm/utils/unittest/googletest/include/gtest/internal/gtest-type-util.h
The file was modifiedllvm/utils/unittest/googletest/src/gtest-internal-inl.h
The file was modifiedllvm/utils/unittest/googlemock/include/gmock/gmock-generated-nice-strict.h
The file was modifiedllvm/utils/unittest/googlemock/README.LLVM
The file was modifiedllvm/utils/unittest/googletest/src/gtest.cc
The file was modifiedclang/unittests/Format/FormatTest.cpp
The file was modifiedllvm/utils/unittest/googletest/src/gtest-filepath.cc
The file was modifiedllvm/utils/unittest/googletest/include/gtest/internal/gtest-death-test-internal.h
The file was modifiedllvm/utils/unittest/googlemock/include/gmock/gmock.h
The file was modifiedllvm/utils/unittest/googletest/include/gtest/internal/gtest-filepath.h
The file was modifiedllvm/utils/unittest/googlemock/src/gmock-cardinalities.cc
The file was modifiedllvm/utils/unittest/googletest/src/gtest-death-test.cc
The file was modifiedllvm/utils/unittest/googlemock/include/gmock/gmock-generated-actions.h
The file was modifiedllvm/utils/unittest/googletest/include/gtest/gtest_pred_impl.h
The file was modifiedllvm/utils/unittest/googletest/src/gtest-typed-test.cc
The file was modifiedllvm/utils/unittest/googlemock/include/gmock/gmock-generated-matchers.h
The file was modifiedllvm/utils/unittest/googletest/include/gtest/gtest_prod.h
The file was modifiedllvm/utils/unittest/googlemock/include/gmock/internal/custom/gmock-matchers.h
The file was modifiedllvm/utils/unittest/googletest/include/gtest/internal/gtest-port.h
The file was modifiedllvm/utils/unittest/googletest/include/gtest/internal/custom/gtest-printers.h
The file was modifiedllvm/utils/unittest/googletest/include/gtest/internal/gtest-string.h
The file was modifiedllvm/utils/unittest/googletest/src/gtest-all.cc
The file was modifiedllvm/utils/unittest/googlemock/include/gmock/gmock-actions.h
The file was modifiedllvm/utils/unittest/googlemock/src/gmock-matchers.cc
The file was modifiedllvm/utils/unittest/googlemock/include/gmock/gmock-cardinalities.h
The file was modifiedllvm/utils/unittest/googlemock/include/gmock/gmock-matchers.h
The file was modifiedllvm/utils/unittest/googlemock/include/gmock/internal/gmock-generated-internal-utils.h
The file was modifiedllvm/utils/unittest/googlemock/include/gmock/internal/custom/gmock-port.h
The file was modifiedllvm/utils/unittest/googletest/include/gtest/internal/custom/gtest.h
The file was modifiedllvm/utils/unittest/googletest/include/gtest/internal/gtest-port-arch.h
The file was modifiedllvm/utils/unittest/googlemock/src/gmock-spec-builders.cc
The file was modifiedllvm/utils/unittest/googletest/include/gtest/gtest.h
The file was modifiedclang/unittests/Format/FormatTestObjC.cpp
The file was modifiedllvm/utils/unittest/googletest/include/gtest/gtest-printers.h
The file was modifiedllvm/utils/unittest/googletest/src/gtest-test-part.cc
The file was modifiedllvm/utils/unittest/googletest/include/gtest/gtest-death-test.h
The file was modifiedllvm/utils/unittest/googletest/include/gtest/gtest-param-test.h
The file was modifiedllvm/unittests/ADT/OptionalTest.cpp
The file was modifiedllvm/utils/unittest/googletest/include/gtest/internal/gtest-param-util-generated.h
The file was modifiedllvm/utils/unittest/googletest/include/gtest/gtest-spi.h
The file was modifiedllvm/utils/unittest/googlemock/include/gmock/internal/custom/gmock-generated-actions.h
The file was modifiedllvm/utils/unittest/googlemock/include/gmock/internal/gmock-internal-utils.h
The file was modifiedllvm/utils/unittest/googletest/src/gtest-printers.cc
The file was modifiedllvm/utils/unittest/googlemock/include/gmock/gmock-more-matchers.h
The file was modifiedllvm/utils/unittest/googletest/include/gtest/internal/gtest-linked_ptr.h
The file was modifiedllvm/utils/unittest/googlemock/include/gmock/gmock-generated-function-mockers.h
The file was modifiedllvm/utils/unittest/googlemock/include/gmock/gmock-more-actions.h
The file was modifiedllvm/utils/unittest/googletest/include/gtest/internal/gtest-param-util.h
The file was modifiedllvm/utils/unittest/googletest/src/gtest-port.cc
Commit a85b1320b6565714dc60b574f86988f4726b9352 by koraq
[libc++] Improve make_string test support.

Adds MAKE_CSTRING and makes the operators of `MultiStringType` `constexpr`.

The code is copied from D96664 so it can be used in D80895.

Differential Revision: https://reviews.llvm.org/D102414
The file was modifiedlibcxx/test/support/make_string.h
Commit b95a103808acfd8f33290d3e80e28af434454b28 by llvm-dev
[X86][SSE] Pull out combineToHorizontalAddSub helper from inside (F)ADD/SUB combines. NFCI.

The intention is to be able to run this from additional locations (such as shuffle combining) in the future.
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
Commit e0a88db545b6ddd7bcde85502ab0fa4c393b7164 by shivam98.tkg
Fix some typos.

Fix some typos

Reviewed By: nicolasvasilache

Differential Revision: https://reviews.llvm.org/D102503
The file was modifiedmlir/include/mlir/Dialect/ArmNeon/ArmNeon.td
The file was modifiedmlir/test/Target/LLVMIR/arm-neon.mlir
Commit 12a74137b3c48bb7e47ce39a8bc76c97c3f115be by bradley.smith
[AArch64][SVE] Combine cntp intrinsics with add/sub to produce incp/decp

Depends on D101062

Differential Revision: https://reviews.llvm.org/D102077
The file was modifiedllvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
The file was addedllvm/test/CodeGen/AArch64/sve-cntp-combine.ll
The file was modifiedllvm/lib/Target/AArch64/SVEInstrFormats.td
Commit c62f984814c4994911dee75bad28cb7346ca3c07 by flo
[LV] Add a few more complex first-order recurrence tests.
The file was modifiedllvm/test/Transforms/LoopVectorize/first-order-recurrence-complex.ll
Commit 6594bac06cee91002ab2a28ccb597e2b7d6f8e06 by listmail
Autogen a test for ease of update
The file was modifiedllvm/test/Transforms/LoopUnroll/unroll-unconditional-latch.ll
Commit da9b6d0656d8b859fc314a42168358d85f1e03bc by i
[ELF][test] Improve -Bsymbolic & -Bsymbolic-functions test

Previously there was no test checking that -Bsymbolic-functions only applies to STT_FUNC symbols.

Reviewed By: jhenderson

Differential Revision: https://reviews.llvm.org/D102461
The file was modifiedlld/test/ELF/bsymbolic.s
Commit 4adf7a7604069331849c26c0f808a9bb6e22e461 by i
[ELF] Add -Bno-symbolic

This option will be available in GNU ld 2.27 (https://sourceware.org/bugzilla/show_bug.cgi?id=27834).
This option can cancel previously specified -Bsymbolic and
-Bsymbolic-functions.  This is useful for excluding some links when the
default uses -Bsymbolic-functions.

Reviewed By: jhenderson, peter.smith

Differential Revision: https://reviews.llvm.org/D102383
The file was modifiedlld/ELF/Config.h
The file was modifiedlld/docs/ReleaseNotes.rst
The file was modifiedlld/docs/ld.lld.1
The file was modifiedlld/ELF/Driver.cpp
The file was modifiedlld/ELF/Options.td
The file was modifiedlld/test/ELF/bsymbolic.s
Commit 769cc335e6e63e5eac0c0ac849de44714326e20b by anastasia.stulova
[OpenCL] Simplify use of C11 atomic types.

Remove requirements on extension pragma in atomic types
because it has not respected the spec wrt disabling types
and hasn't been useful either. With this change, the
developers can use atomic types from the extensions if they
are supported without enabling the pragma just like the builtin
functions

This patch does not break backward compatibility since the
extension pragma is still supported and it makes the behavior of
the compiler less strict by accepting code without needless and
inconsistent pragma statements.

Differential Revision: https://reviews.llvm.org/D100976
The file was modifiedclang/lib/Sema/Sema.cpp
The file was modifiedclang/test/Parser/opencl-atomics-cl20.cl
Commit b7d1ab75cf474fb3ffc7e7173762c4d83eb2ef8e by mascasa
[HWASan] Add aliasing flag and enable HWASan to use it.

-fsanitize-hwaddress-experimental-aliasing is intended to distinguish
aliasing mode from LAM mode on x86_64.  check-hwasan is configured
to use aliasing mode while check-hwasan-lam is configured to use LAM
mode.

The current patch doesn't actually do anything differently in the two
modes.  A subsequent patch will actually build the separate runtimes
and use them in each mode.

Currently LAM mode tests must be run in an emulator that
has LAM support.  To ensure LAM mode isn't broken by future patches, I
will next set up a QEMU buildbot to run the HWASan tests in LAM.

Reviewed By: vitalybuka

Differential Revision: https://reviews.llvm.org/D102288
The file was modifiedclang/include/clang/Driver/Options.td
The file was modifiedcompiler-rt/test/hwasan/lit.cfg.py
The file was modifiedclang/include/clang/Driver/SanitizerArgs.h
The file was modifiedcompiler-rt/test/hwasan/TestCases/Linux/vfork.c
The file was modifiedcompiler-rt/test/hwasan/lit.site.cfg.py.in
The file was modifiedclang/lib/Driver/SanitizerArgs.cpp
The file was modifiedcompiler-rt/test/hwasan/CMakeLists.txt
Commit 9d1a61e695eb01298e26c76867d65592f1e1968c by listmail
Do actual DCE in LoopUnroll

LoopUnroll does a limited DCE pass after unrolling, but if you have a chain of dead instructions, it only deletes the last one. Improve the code to recursively delete all trivially dead instructions.

Differential Revision: https://reviews.llvm.org/D102511
The file was modifiedllvm/test/Transforms/LoopUnroll/optsize-loop-size.ll
The file was modifiedllvm/test/Transforms/LoopUnroll/unroll-unconditional-latch.ll
The file was modifiedllvm/test/Transforms/LoopUnrollAndJam/unroll-and-jam.ll
The file was modifiedllvm/lib/Transforms/Utils/LoopUnroll.cpp
The file was modifiedllvm/test/Transforms/LoopUnroll/scevunroll.ll
The file was modifiedllvm/test/Transforms/LoopUnroll/unroll-header-exiting-with-phis.ll
The file was modifiedllvm/test/Transforms/LoopUnroll/nonlatchcondbr.ll
The file was modifiedllvm/test/Transforms/LoopUnroll/pr45939-peel-count-and-complete-unroll.ll
Commit e488bf815fbdb78a1182cbde8a9e01a4a7ea4028 by listmail
Revert "Do actual DCE in LoopUnroll"

This reverts commit 9d1a61e695eb01298e26c76867d65592f1e1968c.

I'd missed some review feedback, and had missed updating an aarch64 test.  Reverting while I fix both.
The file was modifiedllvm/test/Transforms/LoopUnroll/unroll-header-exiting-with-phis.ll
The file was modifiedllvm/test/Transforms/LoopUnroll/optsize-loop-size.ll
The file was modifiedllvm/test/Transforms/LoopUnrollAndJam/unroll-and-jam.ll
The file was modifiedllvm/lib/Transforms/Utils/LoopUnroll.cpp
The file was modifiedllvm/test/Transforms/LoopUnroll/unroll-unconditional-latch.ll
The file was modifiedllvm/test/Transforms/LoopUnroll/scevunroll.ll
The file was modifiedllvm/test/Transforms/LoopUnroll/nonlatchcondbr.ll
The file was modifiedllvm/test/Transforms/LoopUnroll/pr45939-peel-count-and-complete-unroll.ll
Commit d4d80a2903c1d074008cac653cdb0b5fe39b8a00 by benny.kra
Bump googletest to 1.10.0
The file was modifiedllvm/unittests/ADT/PriorityWorklistTest.cpp
The file was modifiedllvm/unittests/ADT/DenseSetTest.cpp
The file was modifiedflang/unittests/RuntimeGTest/ListInputTest.cpp
The file was removedllvm/utils/unittest/googlemock/include/gmock/internal/gmock-generated-internal-utils.h
The file was modifiedclang/unittests/Rename/RenameEnumTest.cpp
The file was modifiedllvm/utils/unittest/googletest/src/gtest-typed-test.cc
The file was modifiedclang/unittests/Tooling/Syntax/BuildTreeTest.cpp
The file was modifiedllvm/utils/unittest/googlemock/include/gmock/gmock-actions.h
The file was modifiedllvm/unittests/ADT/DenseMapTest.cpp
The file was modifiedllvm/utils/unittest/googletest/include/gtest/internal/gtest-string.h
The file was modifiedlldb/unittests/Host/SocketTest.cpp
The file was modifiedclang/unittests/Tooling/Syntax/SynthesisTest.cpp
The file was modifiedllvm/utils/unittest/googletest/include/gtest/gtest-typed-test.h
The file was modifiedllvm/unittests/ADT/BitVectorTest.cpp
The file was modifiedllvm/unittests/FileCheck/FileCheckTest.cpp
The file was modifiedllvm/unittests/IR/ValueMapTest.cpp
The file was modifiedllvm/utils/unittest/googletest/src/gtest-death-test.cc
The file was modifiedllvm/utils/unittest/googlemock/include/gmock/gmock-cardinalities.h
The file was modifiedllvm/unittests/CodeGen/DIETest.cpp
The file was modifiedllvm/utils/unittest/googletest/include/gtest/internal/gtest-internal.h
The file was modifiedllvm/utils/unittest/googletest/src/gtest.cc
The file was modifiedllvm/unittests/ProfileData/CoverageMappingTest.cpp
The file was removedllvm/utils/unittest/googlemock/include/gmock/gmock-generated-nice-strict.h
The file was modifiedllvm/utils/unittest/googlemock/src/gmock-internal-utils.cc
The file was modifiedllvm/utils/unittest/googletest/include/gtest/gtest-test-part.h
The file was modifiedllvm/utils/unittest/googletest/include/gtest/gtest-message.h
The file was modifiedllvm/utils/unittest/googletest/src/gtest-all.cc
The file was modifiedllvm/utils/unittest/googletest/src/gtest-port.cc
The file was modifiedllvm/utils/unittest/googlemock/include/gmock/gmock-generated-actions.h
The file was modifiedllvm/utils/unittest/googletest/include/gtest/gtest-param-test.h
The file was modifiedllvm/unittests/Frontend/OpenMPIRBuilderTest.cpp
The file was modifiedclang/unittests/AST/ASTImporterODRStrategiesTest.cpp
The file was modifiedclang/unittests/Rename/RenameClassTest.cpp
The file was modifiedllvm/utils/unittest/googlemock/include/gmock/internal/gmock-port.h
The file was modifiedclang/unittests/Rename/RenameMemberTest.cpp
The file was modifiedllvm/utils/unittest/googletest/include/gtest/internal/gtest-type-util.h
The file was modifiedllvm/utils/unittest/googletest/include/gtest/internal/gtest-filepath.h
The file was modifiedclang/unittests/Rename/RenameAliasTest.cpp
The file was modifiedllvm/unittests/ADT/MapVectorTest.cpp
The file was modifiedllvm/utils/unittest/googletest/include/gtest/internal/gtest-port-arch.h
The file was modifiedllvm/unittests/Support/TargetParserTest.cpp
The file was modifiedllvm/utils/unittest/googletest/include/gtest/gtest-death-test.h
The file was modifiedclang/unittests/Tooling/Syntax/MutationsTest.cpp
The file was addedllvm/utils/unittest/googlemock/include/gmock/internal/gmock-pp.h
The file was modifiedllvm/utils/unittest/googletest/src/gtest-printers.cc
The file was modifiedllvm/unittests/ADT/IntrusiveRefCntPtrTest.cpp
The file was modifiedllvm/utils/unittest/googletest/include/gtest/internal/gtest-port.h
The file was modifiedllvm/unittests/ADT/STLForwardCompatTest.cpp
The file was modifiedllvm/utils/unittest/googletest/src/gtest-filepath.cc
The file was modifiedllvm/unittests/Analysis/ValueTrackingTest.cpp
The file was modifiedllvm/unittests/IR/PatternMatch.cpp
The file was addedllvm/utils/unittest/googlemock/include/gmock/gmock-nice-strict.h
The file was modifiedllvm/unittests/Support/DynamicLibrary/DynamicLibraryTest.cpp
The file was modifiedllvm/utils/unittest/googlemock/include/gmock/gmock-generated-function-mockers.h
The file was modifiedllvm/utils/unittest/googletest/include/gtest/gtest-spi.h
The file was modifiedllvm/utils/unittest/googlemock/src/gmock-cardinalities.cc
The file was modifiedllvm/utils/unittest/googlemock/src/gmock-spec-builders.cc
The file was removedllvm/utils/unittest/googletest/include/gtest/internal/gtest-tuple.h
The file was modifiedllvm/utils/unittest/googletest/include/gtest/gtest.h
The file was modifiedllvm/unittests/ADT/RangeAdapterTest.cpp
The file was modifiedllvm/unittests/IR/PassBuilderCallbacksTest.cpp
The file was modifiedclang/unittests/AST/ASTImporterTest.cpp
The file was modifiedllvm/utils/unittest/googletest/include/gtest/internal/gtest-death-test-internal.h
The file was modifiedllvm/unittests/ADT/SmallVectorTest.cpp
The file was modifiedllvm/unittests/Support/MathExtrasTest.cpp
The file was modifiedllvm/utils/unittest/googlemock/include/gmock/gmock.h
The file was modifiedllvm/utils/unittest/googlemock/src/gmock.cc
The file was removedllvm/utils/unittest/googletest/include/gtest/internal/gtest-linked_ptr.h
The file was modifiedllvm/utils/unittest/googlemock/include/gmock/internal/gmock-internal-utils.h
The file was modifiedllvm/utils/unittest/googletest/src/gtest-test-part.cc
The file was modifiedllvm/include/llvm/Testing/Support/Error.h
The file was modifiedlldb/unittests/Process/Utility/LinuxProcMapsTest.cpp
The file was addedllvm/utils/unittest/googletest/include/gtest/gtest-matchers.h
The file was modifiedclang/unittests/Analysis/ExprMutationAnalyzerTest.cpp
The file was modifiedllvm/utils/unittest/googlemock/include/gmock/gmock-generated-matchers.h
The file was modifiedllvm/utils/unittest/googletest/include/gtest/gtest_pred_impl.h
The file was modifiedllvm/unittests/Passes/PluginsTest.cpp
The file was modifiedllvm/unittests/DebugInfo/DWARF/DWARFDebugLineTest.cpp
The file was modifiedclang/unittests/AST/ASTImporterVisibilityTest.cpp
The file was addedllvm/utils/unittest/googletest/src/gtest-matchers.cc
The file was modifiedclang/unittests/ASTMatchers/ASTMatchersNodeTest.cpp
The file was modifiedllvm/utils/unittest/googlemock/include/gmock/gmock-matchers.h
The file was modifiedllvm/unittests/XRay/FDRProducerConsumerTest.cpp
The file was modifiedclang/unittests/AST/ASTImporterObjCTest.cpp
The file was modifiedllvm/unittests/DebugInfo/DWARF/DWARFFormValueTest.cpp
The file was modifiedllvm/utils/unittest/googlemock/include/gmock/gmock-more-actions.h
The file was modifiedllvm/utils/unittest/googlemock/src/gmock-matchers.cc
The file was modifiedllvm/utils/unittest/googlemock/include/gmock/gmock-spec-builders.h
The file was modifiedllvm/unittests/XRay/FDRRecordPrinterTest.cpp
The file was modifiedclang/unittests/StaticAnalyzer/RangeSetTest.cpp
The file was modifiedllvm/unittests/XRay/GraphTest.cpp
The file was modifiedclang/unittests/Tooling/Syntax/TreeTest.cpp
The file was modifiedllvm/unittests/ADT/IListBaseTest.cpp
The file was modifiedllvm/unittests/ProfileData/InstrProfTest.cpp
The file was modifiedllvm/utils/unittest/googletest/include/gtest/gtest-printers.h
The file was removedllvm/utils/unittest/googletest/include/gtest/internal/gtest-param-util-generated.h
The file was modifiedllvm/utils/unittest/googletest/src/gtest-internal-inl.h
The file was modifiedllvm/unittests/Support/MemoryTest.cpp
The file was modifiedclang/unittests/AST/ASTImporterGenericRedeclTest.cpp
The file was modifiedllvm/utils/unittest/googletest/include/gtest/internal/gtest-param-util.h
The file was addedllvm/utils/unittest/googlemock/include/gmock/gmock-function-mocker.h
The file was modifiedllvm/unittests/ADT/TinyPtrVectorTest.cpp
Commit 0f7a595095b8fbd5f09079125c99889dbce34ce5 by lebedev.ri
[NFC][X86][MCA] AMD Zen 3: add same-reg SSE XMM PXOR tests
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver3/zero-idioms-sse-xmm.s
Commit d58d020b6c711582676ba3f8e23fd5dce6aacbd4 by lebedev.ri
[NFC][X86][MCA] AMD Zen 3: add same-reg AVX XMM VPXOR tests
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver3/zero-idioms-avx-xmm.s
Commit 3009f8a383fa5904d944cd5f1dbe6747cc204f5f by lebedev.ri
[NFC][X86][MCA] AMD Zen 3: add same-reg AVX YMM VPXOR tests
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver3/zero-idioms-avx-ymm.s
Commit 498bf365f42b2aadba019215150b157e8ff0efb2 by lebedev.ri
[X86] AMD Zen 3: same-reg SSE XMM PXOR is a 1-cycle(!) dep-breaking zero-idiom

As confirmed by the exegesis measurements, and ref docs.
The file was modifiedllvm/lib/Target/X86/X86ScheduleZnver3.td
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver3/zero-idioms-sse-xmm.s
Commit 31669b50738d3ec0e400ae2b25106b0090f4477b by lebedev.ri
[X86] AMD Zen 3: same-reg AVX XMM VPXOR is a zero-cycle(!) dep-breaking zero-idiom

As confirmed by exegesis measurements, and ref docs.
The file was modifiedllvm/lib/Target/X86/X86ScheduleZnver3.td
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver3/zero-idioms-avx-xmm.s
Commit 1d73c2b8cfa3418ac07f376afb1a30c397d69e49 by lebedev.ri
[X86] AMD Zen 3: same-reg AVX YMM VPXOR is a zero-cycle(!) dep-breaking zero-idiom

As confirmed by exegesis measurements, and ref docs.
The file was modifiedllvm/lib/Target/X86/X86ScheduleZnver3.td
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver3/zero-idioms-avx-ymm.s
Commit 3f235a0b8457b78589e580219f31d05f442f11bf by lebedev.ri
[NFC][X86][MCA] AMD Zen 3: add same-reg SSE XMM PANDN tests
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver3/zero-idioms-sse-xmm.s
Commit a3617138c2cb17b3c659613620321dff29da7c1b by lebedev.ri
[NFC][X86][MCA] AMD Zen 3: add same-reg AVX XMM VPANDN tests
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver3/zero-idioms-avx-xmm.s
Commit 9acc589e5acedf61f627840241d347d10eba2bb2 by lebedev.ri
[NFC][X86][MCA] AMD Zen 3: add same-reg AVX YMM VPANDN tests
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver3/zero-idioms-avx-ymm.s
Commit a72cacb53f42704e7621b6f9e7fa9b21b49fdf76 by lebedev.ri
[X86] AMD Zen 3: same-reg SSE XMM PANDN is a 1-cycle(!) dep-breaking zero-idiom

As confirmed by the exegesis measurements, and ref docs.
The file was modifiedllvm/lib/Target/X86/X86ScheduleZnver3.td
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver3/zero-idioms-sse-xmm.s
Commit 44c2b4fe91de00bce63ea4f0fbe47ce612cae69a by lebedev.ri
[X86] AMD Zen 3: same-reg AVX XMM VPANDN is a zero-cycle(!) dep-breaking zero-idiom

As confirmed by exegesis measurements, and ref docs.
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver3/zero-idioms-avx-xmm.s
The file was modifiedllvm/lib/Target/X86/X86ScheduleZnver3.td
Commit ce22f53916af105893a747ea4f1b432c2624840f by lebedev.ri
[X86] AMD Zen 3: same-reg AVX YMM VPANDN is a zero-cycle(!) dep-breaking zero-idiom

As confirmed by exegesis measurements, and ref docs.
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver3/zero-idioms-avx-ymm.s
The file was modifiedllvm/lib/Target/X86/X86ScheduleZnver3.td
Commit a6f5351443d540f9c6e04f4076dbbec756f2a545 by lebedev.ri
[NFC][X86][MCA] AMD Zen 3: add same-reg SSE XMM PSUB{B,W,D,Q} tests
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver3/zero-idioms-sse-xmm.s
Commit d08909d1cb733e5536f736022c0725d97d156c95 by lebedev.ri
[NFC][X86][MCA] AMD Zen 3: add same-reg AVX XMM VPSUB{B,W,D,Q} tests
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver3/zero-idioms-avx-xmm.s
Commit bbd2117c34a5cf0f2593fc0a16d9f7b9db2d18ea by lebedev.ri
[NFC][X86][MCA] AMD Zen 3: add same-reg AVX YMM VPSUB{B,W,D,Q} tests
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver3/zero-idioms-avx-ymm.s
Commit 1ea8be214f67903cf466f40310c76ba9a428e1d5 by lebedev.ri
[X86] AMD Zen 3: same-reg SSE XMM PSUB{B,W,D,Q} is a 1-cycle(!) dep-breaking zero-idiom

As confirmed by the exegesis measurements, and ref docs.
The file was modifiedllvm/lib/Target/X86/X86ScheduleZnver3.td
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver3/zero-idioms-sse-xmm.s
Commit 7a45b96e04182ea47e2b28108494c4ac9f64580c by lebedev.ri
[X86] AMD Zen 3: same-reg AVX XMM VPSUB{B,W,D,Q} is a zero-cycle(!) dep-breaking zero-idiom

As confirmed by the exegesis measurements, and ref docs.
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver3/zero-idioms-avx-xmm.s
The file was modifiedllvm/lib/Target/X86/X86ScheduleZnver3.td
Commit 93f26428712769bbe2b58171d150d2c6b7357b0b by lebedev.ri
[X86] AMD Zen 3: same-reg AVX YMM VPSUB{B,W,D,Q} is a zero-cycle(!) dep-breaking zero-idiom

As confirmed by the exegesis measurements, and ref docs.
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver3/zero-idioms-avx-ymm.s
The file was modifiedllvm/lib/Target/X86/X86ScheduleZnver3.td
Commit 4673af527ecd7cfded16f9ba4e0bf0bff7eabae1 by lebedev.ri
[NFC][X86][MCA] AMD Zen 3: add same-reg SSE XMM PSUBS{B,W} tests
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver3/zero-idioms-sse-xmm.s
Commit 14e48cf8eeeec1d4983f6552cf75de488d5d23f6 by lebedev.ri
[NFC][X86][MCA] AMD Zen 3: add same-reg AVX XMM VPSUBS{B,W} tests
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver3/zero-idioms-avx-xmm.s
Commit 0e20d1f0ef33034a6049df3d10fad680580162ff by lebedev.ri
[NFC][X86][MCA] AMD Zen 3: add same-reg AVX YMM VPSUBS{B,W} tests
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver3/zero-idioms-avx-ymm.s
Commit 29c4f892febcb67589c93aa5d52109961322dda4 by lebedev.ri
[X86] AMD Zen 3: same-reg SSE XMM PSUBS{B,W} is a 1-cycle(!) dep-breaking zero-idiom

Not really mentioned in ref docs, but measures as such.
The file was modifiedllvm/lib/Target/X86/X86ScheduleZnver3.td
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver3/zero-idioms-sse-xmm.s
Commit 012417c98026134b97713c7e21b40abe1604c449 by lebedev.ri
[X86] AMD Zen 3: same-reg AVX XMM VPSUBS{B,W} is a 1-cycle(!) dep-breaking zero-idiom

Not really mentioned in ref docs, but measures as such.
Yes, this one is also not zero-cycle.
The file was modifiedllvm/lib/Target/X86/X86ScheduleZnver3.td
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver3/zero-idioms-avx-xmm.s
Commit 555e1d2987e22e97bc4a96f8d58f0cb603b53211 by lebedev.ri
[X86] AMD Zen 3: same-reg AVX YMM VPSUBS{B,W} is a 1-cycle(!) dep-breaking zero-idiom

Not really mentioned in ref docs, but measures as such.
Yes, this one is also not zero-cycle.
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver3/zero-idioms-avx-ymm.s
The file was modifiedllvm/lib/Target/X86/X86ScheduleZnver3.td
Commit 128d9c6bbdef0f463acaba696ea0cc6602bb3b1d by lebedev.ri
[NFC][X86][MCA] AMD Zen 3: add same-reg SSE XMM PSUBUS{B,W} tests
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver3/zero-idioms-sse-xmm.s
Commit b6a0449b34a60cb57c33996366f8f057cacfadf0 by