SuccessChanges

Changes from Git (git http://labmaster3.local/git/llvm-project.git)

Summary

  1. [NFC][InstCombine] Add tests for smin reduction w/ i1 element type (PR51259) (details)
  2. [InstCombine] `vector_reduce_smin(?ext(<n x i1>))` --> `?ext(vector_reduce_{or,and}(<n x i1>))` (PR51259) (details)
  3. [NFC][InstCombine] Add tests for smax reduction w/ i1 element type (PR51259) (details)
  4. [InstCombine] `vector_reduce_smax(?ext(<n x i1>))` --> `?ext(vector_reduce_{and,or}(<n x i1>))` (PR51259) (details)
  5. [AArch64][GlobalISel] Emit extloads for ZExt/SExt values in assignValueToAddress (details)
  6. [NFC][InstCombine] Add tests for and reduction w/ i1 element type (PR51259) (details)
  7. [NFC][InstCombine] Add tests for or reduction w/ i1 element type (PR51259) (details)
  8. [InstCombine] `vector_reduce_{or,and}(?ext(<n x i1>))` --> `?ext(vector_reduce_{or,and}(<n x i1>))` (PR51259) (details)
  9. [BasicTTIImpl][LoopUnroll] getUnrollingPreferences(): emit ORE remark when advising against unrolling due to a call in a loop (details)
  10. Improve UBSan documentation (details)
Commit 4551a4184700cce21d3e63b03ccedefab6dd205f by lebedev.ri
[NFC][InstCombine] Add tests for smin reduction w/ i1 element type (PR51259)
The file was addedllvm/test/Transforms/InstCombine/reduction-smin-sext-zext-i1.ll
Commit f47b7b6d10c77cce77c9456f788bcc77b3a19ebb by lebedev.ri
[InstCombine] `vector_reduce_smin(?ext(<n x i1>))` --> `?ext(vector_reduce_{or,and}(<n x i1>))` (PR51259)

Alive2 agrees:
https://alive2.llvm.org/ce/z/noXtZ8 (self)
https://alive2.llvm.org/ce/z/JNrN6C (zext)
https://alive2.llvm.org/ce/z/58snuN (sext)

We already handle `vector_reduce_and(<n x i1>)`,
so let's just combine into the already-handled pattern
and let the existing fold do the rest.
The file was modifiedllvm/test/Transforms/InstCombine/reduction-smin-sext-zext-i1.ll
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
Commit d7482a2bded334710816ea0fc9fbbb6ec09d673e by lebedev.ri
[NFC][InstCombine] Add tests for smax reduction w/ i1 element type (PR51259)
The file was addedllvm/test/Transforms/InstCombine/reduction-smax-sext-zext-i1.ll
Commit 554fc9ad0a24f6689c61d080c9451edd2ddc90b1 by lebedev.ri
[InstCombine] `vector_reduce_smax(?ext(<n x i1>))` --> `?ext(vector_reduce_{and,or}(<n x i1>))` (PR51259)

Alive2 agrees:
https://alive2.llvm.org/ce/z/3oqir9 (self)
https://alive2.llvm.org/ce/z/6cuI5m (zext)
https://alive2.llvm.org/ce/z/4FL8rD (sext)

We already handle `vector_reduce_and(<n x i1>)`,
so let's just combine into the already-handled pattern
and let the existing fold do the rest.
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
The file was modifiedllvm/test/Transforms/InstCombine/reduction-smax-sext-zext-i1.ll
Commit bd13c8e610cad6c60e2b35264bcff9a4e4934615 by Jessica Paquette
[AArch64][GlobalISel] Emit extloads for ZExt/SExt values in assignValueToAddress

When a value is expected to be extended, we should emit an extended load rather
than a normal G_LOAD.

Add checklines to arm64-abi.ll which show that we now emit the correct loads.

For ease of comparison: https://godbolt.org/z/8WvY6EfdE

Differential Revision: https://reviews.llvm.org/D107313
The file was modifiedllvm/test/CodeGen/AArch64/arm64-abi.ll
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/call-lowering-signext.ll
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/call-lowering-zeroext.ll
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/call-translator-ios.ll
Commit a22449336ed918ef5946d5f89c50df9404a2c062 by lebedev.ri
[NFC][InstCombine] Add tests for and reduction w/ i1 element type (PR51259)
The file was addedllvm/test/Transforms/InstCombine/reduction-and-sext-zext-i1.ll
Commit cdb0dfdffaaf061ba1b4e5653e6179db152ed891 by lebedev.ri
[NFC][InstCombine] Add tests for or reduction w/ i1 element type (PR51259)
The file was addedllvm/test/Transforms/InstCombine/reduction-or-sext-zext-i1.ll
Commit 4ba3326f17ddabc1f427508a927a987d812ac543 by lebedev.ri
[InstCombine] `vector_reduce_{or,and}(?ext(<n x i1>))` --> `?ext(vector_reduce_{or,and}(<n x i1>))` (PR51259)

This allows the expansion logic to actually trigger if the argument
was extended from i1 element type, like the rest of the reductions expect.

Alive2 agrees:
https://alive2.llvm.org/ce/z/wcfews (or zext)
https://alive2.llvm.org/ce/z/FCXNFx (or sext)
https://alive2.llvm.org/ce/z/f26zUY (and zext)
https://alive2.llvm.org/ce/z/jprViN (and sext)
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
The file was modifiedllvm/test/Transforms/InstCombine/reduction-and-sext-zext-i1.ll
The file was modifiedllvm/test/Transforms/InstCombine/reduction-or-sext-zext-i1.ll
Commit 6f6e9a867f2ace8c8b99eb8008e17dd63116bcde by lebedev.ri
[BasicTTIImpl][LoopUnroll] getUnrollingPreferences(): emit ORE remark when advising against unrolling due to a call in a loop

I'm not sure this is the best way to approach this,
but the situation is rather not very detectable unless we explicitly call it out when refusing to advise to unroll.

Reviewed By: efriedma

Differential Revision: https://reviews.llvm.org/D107271
The file was modifiedllvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
The file was modifiedllvm/lib/Transforms/Scalar/LoopUnrollPass.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.cpp
The file was modifiedllvm/lib/Transforms/Scalar/LoopUnrollAndJamPass.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
The file was modifiedllvm/lib/Target/ARM/ARMTargetTransformInfo.h
The file was modifiedllvm/include/llvm/Analysis/TargetTransformInfo.h
The file was modifiedllvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
The file was modifiedllvm/include/llvm/CodeGen/BasicTTIImpl.h
The file was modifiedllvm/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp
The file was modifiedllvm/lib/Target/SystemZ/SystemZTargetTransformInfo.h
The file was modifiedllvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
The file was modifiedllvm/include/llvm/Transforms/Utils/UnrollLoop.h
The file was modifiedllvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.h
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.h
The file was modifiedllvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.cpp
The file was modifiedllvm/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp
The file was addedllvm/test/Transforms/LoopUnroll/X86/call-remark.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
The file was modifiedllvm/include/llvm/Analysis/TargetTransformInfoImpl.h
The file was modifiedllvm/lib/Target/Hexagon/HexagonTargetTransformInfo.h
The file was modifiedllvm/lib/Target/PowerPC/PPCTargetTransformInfo.h
The file was modifiedllvm/lib/Analysis/TargetTransformInfo.cpp
Commit 65e9d7efb090756e16bbb5ff929efbc795a8b0d4 by 31459023+hctim
Improve UBSan documentation

Add more checks, info on -fno-sanitize=..., and reference to 5/2021 UBSan Oracle blog.

Authored By: DianeMeirowitz
Reviewed By: hctim

Differential Revision: https://reviews.llvm.org/D106908
The file was modifiedclang/docs/UndefinedBehaviorSanitizer.rst