Started 1 mo 21 days ago
Took 3 hr 4 min

Build clang-d401457-gbacb0cac1580-t24636-b24636.tar.gz (Oct 11, 2021 9:32:34 AM)

Issues

No known issues detected

Build Log

Changes
  1. clang-ve-ninja: check compiler-rt (details / githubweb)
  2. mlir-s390x-linux: collapse requests (details / githubweb)
Changes
  1. [Clang] Enable IC/IF mode for __ibm128 (details)
  2. [LLDB] Remove xfail decorator TestInferiorAssert.py AArch64/Linux (details)
  3. [lldb] [ConnectionFileDescriptorPosix] Combine m_read_sp & m_write_sp (details)
  4. [lldb] [DynamicRegisterInfo] Remove non-const GetRegisterInfoAtIndex() (details)
  5. [lldb] Make char[N] formatters respect the end of the array (PR44649) (details)
  6. [AArch64][SVE] Ensure LowerEXTRACT_SUBVECTOR is not called for illegal types (details)
  7. [lldb] Don't print to stderr in TypeSystemClang::GetBuiltinTypeForDWARFEncodingAndBitSize (details)
  8. [lldb] Add support for DW_AT_calling_convention to the DWARF parser (details)
  9. [flang][driver] Add actions that execute despite semantic errors (details)
  10. [fir] Update clang-tidy for the Optimizer directory (details)
  11. [lldb] [test] Rewrite g/p/G/P tests not to rely on hardcoded ARM regs (details)
  12. [LLD] [TEST] Add test case for patching an absolute relocation to a weak undef (details)
  13. [lldb][NFCI] Refactor out attribute parsing from DWARFASTParserClang::ParseSingleMember (details)
  14. [X86][AVX] Add test case for PR52122 (details)
  15. [fir] Clean up InitFIR.h (details)
  16. [lldb][NFC] Remove unnecessary reference from ParseChildMembers's default_accessibility parameter (details)
  17. [X86][AVX] Ensure we retain zero elements in select(pshufb,pshufb) -> or(pshufb,pshufb) fold (PR52122) (details)
  18. [fir] Add fir.convert canonicalization patterns (details)
  19. [Object] Deduplicate the three createError functions (details)
  20. [lldb] [ABI] Apply AugmentRegisterInfo() to DynamicRegisterInfo::Registers (details)
  21. [lldb] [Target] Make addSupplementaryRegister() work on Register vector (details)
  22. [lldb] [ABI/AArch64] Add pseudo-regs if missing (details)
  23. [lldb] [DynamicRegisterInfo] Support setting from vector<Register> (details)
  24. [MS compat] Handle #pragma fenv_access like #pragma STDC FENV_ACCESS (PR50694) (details)
  25. [mlir] add user-level documentation for Python bindings (details)
Changes
  1. Added parameter missed during rebase. (details / githubweb)

Started by upstream project relay-lnt-ctmark build number 13294
originally caused by:

This run spent:

  • 2 hr 53 min waiting;
  • 3 hr 4 min build duration;
  • 3 hr 4 min total from scheduled to completion.
Revision: dfd41aa8267c78dd71b8dd01187bbb3c87ae25e3
Repository: https://github.com/llvm/llvm-zorg.git
  • refs/remotes/origin/main
Revision: bacb0cac1580a0cd83a0d3c5cb12f3f80d26a0f4
Repository: http://labmaster3.local/git/llvm-project.git
  • detached
Revision: be3643cefc52cb74373ae1b0bc5c62391f4f73b6
Repository: https://github.com/llvm/llvm-lnt.git
  • refs/remotes/origin/main
Revision: b983131b7e46d34f0eb2be399baf6c2e48d5734c
Repository: https://github.com/llvm/llvm-test-suite.git
  • refs/remotes/origin/main