Commit
04d083b19e6eb80587cc27fa3996121c8c4bddbc
by akuegel[mlir][NFC] Use const reference for loop variables.
|
 | mlir/lib/Dialect/Linalg/ComprehensiveBufferize/ModuleBufferization.cpp |
| mlir/lib/Dialect/Linalg/ComprehensiveBufferize/BufferizableOpInterface.cpp |
Commit
cca8e1e415c89358841693967f9e013da2eb9c44
by github[libc][NFC] Fix typo in CMakeLists documentation
|
| libc/src/math/CMakeLists.txt |
Commit
af86aa798083e483311d0d661d3f8a84936d0494
by flo[MemoryLocation] Use None instead of {}. (NFC)
|
| llvm/lib/Analysis/MemoryLocation.cpp |
Commit
d133a21b71316175bab2f616f57727801daae471
by jay.foad[SelectionDAG] Add newline to a debug message
|
| llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp |
Commit
ed8c63115ed7bdb31812a7a02dc8480def0a1ea4
by springerm[mlir][linalg][bufferize][NFC] Provide default implementation of getAliasingOpOperand
This simplifies op interface implementations.
Differential Revision: https://reviews.llvm.org/D115025
|
| mlir/lib/Dialect/Linalg/ComprehensiveBufferize/LinalgInterfaceImpl.cpp |
| mlir/lib/Dialect/Linalg/ComprehensiveBufferize/ModuleBufferization.cpp |
| mlir/lib/Dialect/Linalg/ComprehensiveBufferize/TensorInterfaceImpl.cpp |
| mlir/include/mlir/Dialect/Linalg/ComprehensiveBufferize/BufferizableOpInterface.td |
| mlir/lib/Dialect/Linalg/ComprehensiveBufferize/SCFInterfaceImpl.cpp |
| mlir/lib/Dialect/Linalg/ComprehensiveBufferize/VectorInterfaceImpl.cpp |
| mlir/lib/Dialect/Linalg/ComprehensiveBufferize/ArithInterfaceImpl.cpp |
| mlir/lib/Dialect/Linalg/ComprehensiveBufferize/BufferizationInterfaceImpl.cpp |
Commit
b29b6f92af29f677cc096ff80c48d1e6e6c1138a
by jay.foad[AMDGPU] Add some more GFX10 GlobalISel test coverage
|
| llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ashr.mir |
| llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.init.exec.wave32.ll |
| llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmul.mir |
Commit
c32421c925131da39f028d3ea39a6cc5e9e1b365
by clementval[fir] Add fir derived type runtime builder
This patch adds the builder to generate derived type runtime API calls.
This patch is part of the upstreaming effort from fir-dev branch.
Reviewed By: rovka
Differential Revision: https://reviews.llvm.org/D114472
Co-authored-by: Peter Klausler <pklausler@nvidia.com>
Co-authored-by: Jean Perier <jperier@nvidia.com>
|
 | flang/include/flang/Optimizer/Builder/Runtime/Derived.h |
| flang/lib/Optimizer/Builder/Runtime/Derived.cpp |
| flang/unittests/Optimizer/CMakeLists.txt |
| flang/lib/Optimizer/Builder/CMakeLists.txt |
| flang/unittests/Optimizer/Builder/Runtime/DerivedTest.cpp |
Commit
d59a0f58f49a4289a7bbef2855cc0d5845715a2b
by clementval[fir] Add fir character builder
This patch adds the FIR builder to generate the numeric intrinsic
runtime call.
This patch is part of the upstreaming effort from fir-dev branch.
Reviewed By: rovka
Differential Revision: https://reviews.llvm.org/D114900
Co-authored-by: Jean Perier <jperier@nvidia.com>
Co-authored-by: mleair <leairmark@gmail.com>
|
| flang/unittests/Optimizer/CMakeLists.txt |
| flang/include/flang/Optimizer/Builder/Runtime/Character.h |
| flang/unittests/Optimizer/Builder/Runtime/CharacterTest.cpp |
| flang/lib/Optimizer/Builder/Runtime/Character.cpp |
| flang/lib/Optimizer/Builder/CMakeLists.txt |
| flang/unittests/Optimizer/Builder/Runtime/RuntimeCallTestBase.h |
Commit
b670dcb81b035babf92d8e6433d89c810ba97d59
by jay.foad[AMDGPU] Add some more GFX10 test coverage
|
| llvm/test/CodeGen/AMDGPU/add.v2i16.ll |
| llvm/test/CodeGen/AMDGPU/add.ll |
| llvm/test/CodeGen/AMDGPU/llvm.amdgcn.init.exec.wave32.ll |
Commit
255ad7342436ff4901d39579f694857f83386dad
by david.green[ARM] Make MVE v2i1 predicates legal
MVE can treat v16i1, v8i1, v4i1 and v2i1 as different views onto the
same 16bit VPR.P0 register, with v2i1 holding two 8 bit values for the
two halves. This was never treated as a legal type in llvm in the past
as there are not many 64bit instructions and no 64bit compares. There
are a few instructions that could use it though, notably a VSELECT (as
it can handle any size using the underlying v16i8 VPSEL), AND/OR/XOR for
similar reasons, some gathers/scatter and long multiplies and VCTP64
instructions.
This patch goes through and makes v2i1 a legal type, handling all the
cases that fall out of that. It also makes VSELECT legal for v2i64 as a
side benefit. A lot of the codegen changes as a result - usually in way
that is a little better or a little worse, but still expensive. Costs
can change a little too in the process, again in a way that expensive
things remain expensive. A lot of the tests that changed are mainly to
ensure correctness - the code can hopefully be improved in the future
where it comes up in practice.
The intrinsics currently remain using the v4i1 they previously did to
emulate a v2i1. This will be changed in a followup patch but this one
was already large enough.
Differential Revision: https://reviews.llvm.org/D114449
|
| llvm/test/Analysis/CostModel/ARM/arith-ssat.ll |
| llvm/test/CodeGen/Thumb2/mve-minmaxi.ll |
| llvm/test/CodeGen/Thumb2/mve-vmovimm.ll |
| llvm/test/Analysis/CostModel/ARM/mve-minmax.ll |
| llvm/test/CodeGen/Thumb2/mve-vcmpr.ll |
| llvm/test/CodeGen/Thumb2/mve-vabdus.ll |
| llvm/test/CodeGen/Thumb2/mve-vctp.ll |
| llvm/test/CodeGen/Thumb2/mve-pred-shuffle.ll |
| llvm/test/CodeGen/Thumb2/mve-vcmp.ll |
| llvm/test/CodeGen/Thumb2/mve-fptoui-sat-vector.ll |
| llvm/test/CodeGen/Thumb2/mve-masked-load.ll |
| llvm/lib/Target/ARM/ARMInstrMVE.td |
| llvm/test/Analysis/CostModel/ARM/reduce-smax.ll |
| llvm/test/CodeGen/Thumb2/mve-pred-loadstore.ll |
| llvm/test/CodeGen/Thumb2/mve-masked-store.ll |
| llvm/test/CodeGen/Thumb2/mve-laneinterleaving.ll |
| llvm/test/CodeGen/Thumb2/mve-minmax.ll |
| llvm/test/CodeGen/Thumb2/mve-vqshrn.ll |
| llvm/lib/Target/ARM/ARMRegisterInfo.td |
| llvm/test/Transforms/LoopVectorize/ARM/mve-icmpcost.ll |
| llvm/test/CodeGen/Thumb2/mve-pred-spill.ll |
| llvm/test/CodeGen/Thumb2/mve-pred-build-var.ll |
| llvm/test/CodeGen/Thumb2/mve-pred-or.ll |
| llvm/test/CodeGen/Thumb2/mve-pred-vselect.ll |
| llvm/test/CodeGen/Thumb2/mve-vqmovn.ll |
| llvm/test/CodeGen/Thumb2/mve-intrinsics/predicates.ll |
| llvm/test/CodeGen/Thumb2/mve-vecreduce-mlapred.ll |
| llvm/lib/Target/ARM/ARMISelLowering.cpp |
| llvm/test/Analysis/CostModel/ARM/mve-abs.ll |
| llvm/test/Analysis/CostModel/ARM/reduce-umax.ll |
| llvm/test/Analysis/CostModel/ARM/reduce-smin.ll |
| llvm/test/Analysis/CostModel/ARM/select.ll |
| llvm/test/Analysis/CostModel/ARM/arith-overflow.ll |
| llvm/test/Transforms/LoopVectorize/ARM/mve-selectandorcost.ll |
| llvm/test/CodeGen/Thumb2/mve-satmul-loops.ll |
| llvm/test/CodeGen/Thumb2/mve-pred-and.ll |
| llvm/test/CodeGen/Thumb2/mve-vcmpz.ll |
| llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp |
| llvm/test/CodeGen/Thumb2/active_lane_mask.ll |
| llvm/test/CodeGen/Thumb2/mve-fptosi-sat-vector.ll |
| llvm/test/CodeGen/Thumb2/mve-vpsel.ll |
| llvm/test/Analysis/CostModel/ARM/arith-usat.ll |
| llvm/test/CodeGen/Thumb2/mve-pred-build-const.ll |
| llvm/test/CodeGen/Thumb2/mve-pred-const.ll |
| llvm/test/CodeGen/Thumb2/mve-pred-not.ll |
| llvm/test/CodeGen/Thumb2/mve-fpclamptosat_vec.ll |
| llvm/test/CodeGen/Thumb2/mve-pred-ext.ll |
| llvm/test/CodeGen/Thumb2/mve-pred-xor.ll |
| llvm/test/CodeGen/Thumb2/mve-vecreduce-addpred.ll |
| llvm/test/CodeGen/Thumb2/mve-pred-bitcast.ll |
| llvm/test/CodeGen/Thumb2/mve-saturating-arith.ll |
| llvm/test/CodeGen/Thumb2/mve-vselect-constants.ll |
| llvm/test/Analysis/CostModel/ARM/reduce-umin.ll |
| llvm/test/CodeGen/Thumb2/mve-masked-ldst.ll |
Commit
e359a1e5486bd1e800ad699ad7957bf324539590
by springerm[mlir][linalg][bufferize][NFC] Map only tensors in BufferizationState
BufferizationState had map/lookup overloads for non-tensor values. This was necessary for IREE. There is now a better way to do this, so these overloads can be removed.
Differential Revision: https://reviews.llvm.org/D114929
|
| mlir/lib/Dialect/Linalg/ComprehensiveBufferize/BufferizableOpInterface.cpp |
| mlir/include/mlir/Dialect/Linalg/ComprehensiveBufferize/BufferizableOpInterface.h |
Commit
54dc03b97bfac40dacd8a0cb5f03381842b20422
by mehrnoosh.heidarpour[InstSimplify] Add test case for logic 'or' fold; NFC
|
| llvm/test/Transforms/InstSimplify/or.ll |
Commit
f6279562dae456f6c58d5f7484ba4bae5c2071fa
by a.bataev[OPENMP]Fix PR52117: Crash caused by target region inside of task construct.
Need to do the analysis of the captured expressions in the clauses.
Previously the compiler ignored them and it may lead to a compiler crash
trying to get the address of the mapped variables.
Differential Revision: https://reviews.llvm.org/D114546
|
| clang/test/OpenMP/task_target_device_codegen.c |
| clang/test/OpenMP/taskloop_codegen.cpp |
| clang/test/Analysis/cfg-openmp.cpp |
| clang/lib/Sema/SemaOpenMP.cpp |
Commit
049530129326f9b0bfa9ce6a762c6cb180974ac5
by weratt[lldb-vscode] Report supportsModulesRequest=true
The adapter does support `Modules` request, implemented in 39239f9.
Reviewed By: wallace
Differential Revision: https://reviews.llvm.org/D115033
|
| lldb/tools/lldb-vscode/lldb-vscode.cpp |
Commit
72750f00121eb10f27ccd62270e5695d9e3322a5
by anna[TrivialDeadness] Introduce API separating two different usages
The earlier usage of wouldInstructionBeTriviallyDead is based on the
assumption that the use_count of that instruction being checked will be
zero. This patch separates the API into two different ones:
1. The strictly conservative one where the instruction is trivially dead iff the uses are dead.
2. The slightly relaxed form, where an instruction is dead along paths where it is not used.
The second form can be used in identifying instructions that are valid
to sink down to uses (D109917).
Reviewed-By: reames
Differential Revision: https://reviews.llvm.org/D114647
|
| llvm/include/llvm/Transforms/Utils/Local.h |
| llvm/lib/Transforms/Utils/Local.cpp |
Commit
d6c0ef78876dc3204b0a6d92119b15aa9cd12af3
by nemanja.i.ibm[PowerPC] Handle base load with reservation mnemonic
The Power ISA defined l[bhwdq]arx as both base and
extended mnemonics. The base mnemonic takes the EH
bit as an operand and the extended mnemonic omits
it, making it implicitly zero. The existing
implementation only handles the base mnemonic when
EH is 1 and internally produces a different
instruction. There are historical reasons for this.
This patch simply removes the limitation introduced
by this implementation that disallows the base
mnemonic with EH = 0 in the ASM parser.
This resolves an issue that prevented some files
in the Linux kernel from being built with
-fintegrated-as.
Also fix a crash if the value is not an integer immediate.
|
| llvm/test/MC/PowerPC/ppc64-errors.s |
| llvm/test/CodeGen/PowerPC/inline-asm-label.ll |
| llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp |
| llvm/test/MC/PowerPC/ppc64-encoding-bookII.s |
Commit
dbed678f4be29107d9848c3716f54bca3ec266bc
by lntue[libc] Fix bugs with negative and mixed normal/denormal inputs in hypot implementation.
Fix a bug with negative and mixed normal/denormal inputs in hypot implementation.
Differential Revision: https://reviews.llvm.org/D114726
|
| libc/test/src/math/HypotTest.h |
| libc/src/__support/FPUtil/Hypot.h |
Commit
ab0c5cea0b1a9a1227fea840184dd7b5983c22a5
by david.green[ARM] Use v2i1 for MVE and CDE intrinsics
This adjusts all the MVE and CDE intrinsics now that v2i1 is a legal
type, to use a <2 x i1> as opposed to emulating the predicate with a
<4 x i1>. The v4i1 workarounds have been removed leaving the natural
v2i1 types, notably in vctp64 which now generates a v2i1 type.
AutoUpgrade code has been added to upgrade old IR, which needs to
convert the old v4i1 to a v2i1 be converting it back and forth to an
integer with arm.mve.v2i and arm.mve.i2v intrinsics. These should be
optimized away in the final assembly.
Differential Revision: https://reviews.llvm.org/D114455
|
| clang/test/CodeGen/arm-mve-intrinsics/vqdmullbq.c |
| llvm/test/CodeGen/Thumb2/cde-vec.ll |
| clang/test/CodeGen/arm-mve-intrinsics/scatter-gather.c |
| llvm/lib/Target/ARM/ARMInstrMVE.td |
| clang/test/CodeGen/arm-mve-intrinsics/vqdmulltq.c |
| llvm/include/llvm/IR/IntrinsicsARM.td |
| llvm/test/CodeGen/Thumb2/mve-intrinsics/vldr.ll |
| clang/test/CodeGen/arm-mve-intrinsics/vld24.c |
| llvm/lib/Target/ARM/MVETailPredication.cpp |
| clang/test/CodeGen/arm-cde-vec.c |
| llvm/test/Transforms/InstCombine/ARM/mve-v2i2v.ll |
| llvm/test/CodeGen/Thumb2/mve-intrinsics/predicates.ll |
| llvm/test/CodeGen/Thumb2/mve-vctp.ll |
| llvm/test/Transforms/LoopStrengthReduce/ARM/vctp-chains-inseltpoison.ll |
| llvm/lib/IR/AutoUpgrade.cpp |
| llvm/test/CodeGen/Thumb2/mve-gatherscatter-mmo.ll |
| clang/utils/TableGen/MveEmitter.cpp |
| llvm/test/CodeGen/Thumb2/active_lane_mask.ll |
| clang/test/CodeGen/arm-mve-intrinsics/vldr.c |
| llvm/test/CodeGen/Thumb2/mve-intrinsics/scatter-gather.ll |
| llvm/test/Transforms/LoopStrengthReduce/ARM/vctp-chains.ll |
| llvm/test/CodeGen/Thumb2/mve-intrinsics/v2i1-upgrade.ll |
| clang/test/CodeGen/arm-mve-intrinsics/vmulltq.c |
| llvm/lib/Analysis/ConstantFolding.cpp |
| llvm/test/CodeGen/Thumb2/mve-intrinsics/vmullbq.ll |
| llvm/test/CodeGen/Thumb2/mve-intrinsics/vqdmull.ll |
| clang/test/CodeGen/arm-mve-intrinsics/predicates.c |
| llvm/test/Transforms/InstSimplify/ConstProp/ARM/mve-vctp.ll |
| llvm/test/CodeGen/Thumb2/mve-intrinsics/vmulltq.ll |
| clang/test/CodeGen/arm-mve-intrinsics/vmullbq.c |
Commit
98a021fcbfe104f98c7b67c35af4bbbccc3c1b8f
by stephen.tozer[DebugInfo] Attempt to preserve more information during tail duplication
Prior to this patch, tail duplication handled debug info poorly -
specifically, debug instructions would be dropped instead of being set
undef, potentially extending the lifetimes of prior debug values that
should be killed. The pass was also very aggressive with dropping debug
info, dropping debug info even when the SSA value it referred to was
still present. This patch attempts to handle debug info more carefully,
checking to see whether each affected debug value can still be live,
setting it undef if not.
Reviewed By: jmorse
Differential Revision: https://reviews.llvm.org/D106875
|
| llvm/test/CodeGen/X86/tail-dup-debugvalue.mir |
| llvm/lib/CodeGen/TailDuplicator.cpp |
| llvm/lib/CodeGen/MachineSSAUpdater.cpp |
| llvm/include/llvm/CodeGen/MachineSSAUpdater.h |
Commit
1cefe91d40aef043ec949c6ddb053b47b4d5b8e6
by 1.int32[clang-tidy][docs][NFC] Improve documentation of bugprone-unhandled-exception-at-new
Reviewed By: aaron.ballman
Differential Revision: https://reviews.llvm.org/D114602
|
| clang-tools-extra/docs/clang-tidy/checks/bugprone-unhandled-exception-at-new.rst |
Commit
71405d90f042792c243d6c134c5cc2bc23853980
by gchatelet[libc] Select FPUtils implementations via code instead of build
We want to simplify the build system and rely on code to do the implementation selection.
This is in preparation of adding a Bazel configuration (D114712).
Differential Revision: https://reviews.llvm.org/D115034
|
| libc/src/__support/FPUtil/x86_64/FEnvImpl.h |
 | libc/src/__support/FPUtil/DummyFEnvImpl.h |
| libc/src/__support/FPUtil/NextAfterLongDoubleX86.h |
| libc/src/__support/FPUtil/x86_64/FMA.h |
| libc/src/__support/FPUtil/LongDoubleBitsX86.h |
| libc/src/__support/FPUtil/x86_64/SqrtLongDouble.h |
| libc/src/__support/FPUtil/FEnvImpl.h |
| libc/src/__support/FPUtil/Sqrt.h |
| libc/src/__support/FPUtil/x86_64/LongDoubleBits.h |
| libc/src/__support/FPUtil/x86_64/NextAfterLongDouble.h |
| libc/src/__support/FPUtil/CMakeLists.txt |
| libc/src/__support/FPUtil/FMA.h |
| libc/src/__support/FPUtil/aarch64/FEnvImpl.h |
| libc/src/__support/FPUtil/aarch64/FMA.h |
| libc/src/__support/FPUtil/ManipulationFunctions.h |
| libc/src/__support/FPUtil/SqrtLongDoubleX86.h |
| libc/src/__support/FPUtil/FPBits.h |
Commit
ead3979a92fc33add4710c4510d6906260dcb4ad
by flo[MemoryLocation] Move DSE intrinsic handling to MemoryLocation. (NFC)
Suggested in D114872.
|
| llvm/lib/Transforms/Scalar/DeadStoreElimination.cpp |
| llvm/lib/Analysis/MemoryLocation.cpp |
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