FailedChanges

Summary

  1. [libcxx] [test] Fix filesystem permission tests for windows (details)
  2. [mlir][ODS]: Add per-op cppNamespace. (details)
  3. [ArgumentPromotion] Fix byval alignment handling. (details)
  4. [RISCV] Prefer to lower MC_GlobalAddress operands to .Lfoo$local (details)
  5. [AArch64][GlobalISel] Support truncstorei8/i16 w/ combine to form truncating G_STOREs. (details)
  6. [GlobalOpt] Remove heap SROA (details)
  7. [X86] X86TTIImpl::getInterleavedMemoryOpCostAVX2(): canonicalize to integer type (details)
  8. [lld][WebAssembly] Convert test to assembly. NFC. (details)
  9. [clang] Support -fpic -fno-semantic-interposition for RISCV (details)
  10. [OpenMP] Use compound operators for reduction combiner if available. (details)
  11. [libc++] Run `substitutes-in-compile-flags.sh.cpp` test on Windows. (details)
  12. Add an "interrupt timeout" to Process, and pipe that through the (details)
  13. [lld][WebAssembly] Remove relocation target verification (details)
  14. [mlir] Move move capture in SparseElementsAttr::getValues (details)
  15. [NFC][LSAN] Limit the number of concurrent threads is the test (details)
  16. [AArch64][GlobaISel] Mark target generic instructions as HasNoSideEffects. (details)
  17. [PowerPC] Improve codegen for int-to-fp conversion of subword vector extract (details)
  18. [OpenMP] Changes to enable MSVC ARM64 build of libomp (details)
  19. [RISCV] Regenerate stepvector.ll. NFC (details)
  20. [hwasan] Stress test for thread creation. (details)
  21. [AMDGPU] Fix extra waitcnt being added with BUFFER_INVL2 (details)
  22. Removed unnecessary introduction of semi-colons. (details)
  23. [mlir] Elide large elements attrs when printing Operations in diagnostics (details)
  24. [mlir][tosa] Tosa elementwise broadcasting had some minor bugs (details)
Commit 68de58cd649cb3a3e94a1c9552ebf2a18bb9d040 by martin
[libcxx] [test] Fix filesystem permission tests for windows

On Windows, the permission bits are mapped down to essentially only
two possible states; readonly or readwrite. Normalize the checked
permission bitmask to match what the implementation will return.

Differential Revision: https://reviews.llvm.org/D101728
The file was modifiedlibcxx/test/support/filesystem_test_helper.h
The file was modifiedlibcxx/test/std/input.output/filesystems/fs.op.funcs/fs.op.copy_file/copy_file.pass.cpp
The file was modifiedlibcxx/test/std/input.output/filesystems/fs.op.funcs/fs.op.permissions/permissions.pass.cpp
Commit 49755871ad0c24ed970c0a4f2c51f90488b0ddd2 by silvasean
[mlir][ODS]: Add per-op cppNamespace.

This is useful for dialects that have logical subparts.

Differential Revision: https://reviews.llvm.org/D102200
The file was modifiedmlir/test/mlir-tblgen/dialect.td
The file was modifiedmlir/lib/TableGen/Operator.cpp
The file was modifiedmlir/include/mlir/TableGen/CodeGenHelpers.h
The file was modifiedmlir/tools/mlir-tblgen/OpDefinitionsGen.cpp
The file was modifiedmlir/include/mlir/IR/OpBase.td
The file was modifiedmlir/include/mlir/TableGen/Operator.h
Commit 61cbbba7a645a1d87db9a80867c84a788ab2ea9c by efriedma
[ArgumentPromotion] Fix byval alignment handling.

Make sure the alignment of the generated operations matches the
alignment of the byval argument.  Previously, we were just ignoring
alignment and getting lucky.

While I'm here, also delete the unnecessary "tail" handling.
Passing a pointer to a byval argument to a "tail" call is UB, so
rewriting to an alloca doesn't require any special handling.

Differential Revision: https://reviews.llvm.org/D89819
The file was modifiedllvm/test/Transforms/ArgumentPromotion/attrs.ll
The file was modifiedllvm/test/Transforms/ArgumentPromotion/byval.ll
The file was removedllvm/test/Transforms/ArgumentPromotion/tail.ll
The file was modifiedllvm/test/Transforms/ArgumentPromotion/byval-2.ll
The file was modifiedllvm/test/Transforms/ArgumentPromotion/dbg.ll
The file was modifiedllvm/lib/Transforms/IPO/ArgumentPromotion.cpp
Commit ec27c5f170441ab54295830aa9f7d376406c6a0f by i
[RISCV] Prefer to lower MC_GlobalAddress operands to .Lfoo$local

Similar to X86 D73230 and AArch64 D101872

With this change, we can set dso_local in clang's -fpic -fno-semantic-interposition mode,
for default visibility external linkage non-ifunc-non-COMDAT definitions.

For such dso_local definitions, variable access/taking the address of a
function/calling a function will go through a local alias to avoid GOT/PLT.

Reviewed By: jrtc27, luismarques

Differential Revision: https://reviews.llvm.org/D101875
The file was addedllvm/test/CodeGen/RISCV/elf-preemption.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVMCInstLower.cpp
Commit ae2b36e8bdfa612649c6f2d8b6b9079679cb2572 by Amara Emerson
[AArch64][GlobalISel] Support truncstorei8/i16 w/ combine to form truncating G_STOREs.

This needs some tablegen changes so that we can actually import the patterns properly.

Differential Revision: https://reviews.llvm.org/D102204
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/select-store.mir
The file was addedllvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-truncstore.mir
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll
The file was modifiedllvm/utils/TableGen/GlobalISelEmitter.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64Combine.td
The file was modifiedllvm/include/llvm/Target/TargetSelectionDAG.td
Commit 129f466e222e13fdf680356831bb935e1229bdf4 by i
[GlobalOpt] Remove heap SROA

GlobalOpt implements a heap SROA (SROA for an malloc allocatated struct or array
of structs) which is largely undertested (heap-sra-[1234].ll are basically the
same test with very little difference) and does not trigger at all when
bootstrapping clang (it only supports the case of one single store).

The heap SROA implementation causes PR50027 (GEP is not properly handled; crash or miscompile).
Just drop the implementation. I have deleted some obviously duplicated tests
but kept `heap-sra-[12]{,-no-nullopt}.ll`.

Reviewed By: aeubanks

Differential Revision: https://reviews.llvm.org/D102257
The file was modifiedllvm/lib/Transforms/IPO/GlobalOpt.cpp
The file was modifiedllvm/test/Transforms/GlobalOpt/heap-sra-phi.ll
The file was modifiedllvm/test/Transforms/GlobalOpt/MallocSROA-section.ll
The file was modifiedllvm/test/Transforms/GlobalOpt/heap-sra-2.ll
The file was removedllvm/test/Transforms/GlobalOpt/heap-sra-4.ll
The file was removedllvm/test/Transforms/GlobalOpt/heap-sra-4-no-null-opt.ll
The file was modifiedllvm/test/Transforms/GlobalOpt/heap-sra-1.ll
The file was removedllvm/test/Transforms/GlobalOpt/heap-sra-3-no-null-opt.ll
The file was removedllvm/test/Transforms/GlobalOpt/heap-sra-3.ll
Commit 97e04d41e646aa13b0cc5ff3812bfb7305fa4756 by lebedev.ri
[X86] X86TTIImpl::getInterleavedMemoryOpCostAVX2(): canonicalize to integer type

This way we don't have to duplicate i32/f32 and i64/f64 entries,
which was already forgotten to be done for a few tuples.
The file was modifiedllvm/lib/Target/X86/X86TargetTransformInfo.cpp
Commit b2f227c6c87c16fa593e643a487efd9326249066 by sbc
[lld][WebAssembly] Convert test to assembly. NFC.

Differential Revision: https://reviews.llvm.org/D102264
The file was removedlld/test/wasm/reloc-addend.ll
The file was addedlld/test/wasm/reloc-addend.s
Commit 2075f2b296b0fa90cb7597f0f318232940d29e95 by i
[clang] Support -fpic -fno-semantic-interposition for RISCV

-fno-semantic-interposition (only effective with -fpic) can optimize default
visibility external linkage (non-ifunc-non-COMDAT) variable access and function
calls to avoid GOT/PLT, by using local aliases, e.g.
```
int var;
__attribute__((optnone)) int fun(int x) { return x * x; }
int test() { return fun(var); }
```

-fpic (var and fun are dso_preemptable)
```
test:
.LBB1_1:
        auipc   a0, %got_pcrel_hi(var)
        ld      a0, %pcrel_lo(.LBB1_1)(a0)
        lw      a0, 0(a0)
// fun is preemptible by default in ld -shared mode. ld will create a PLT.
        tail    fun@plt
```

vs -fpic -fno-semantic-interposition (var and fun are dso_local)
```
test:
.Ltest$local:
.LBB1_1:
        auipc   a0, %pcrel_hi(.Lvar$local)
        addi    a0, a0, %pcrel_lo(.LBB1_1)
        lw      a0, 0(a0)
// The assembler either resolves .Lfun$local at assembly time (-mno-relax
// -fno-function-sections), or produces a relocation referencing a non-preemptible
// local symbol (which can avoid PLT).
        tail    .Lfun$local
```

Note: Clang's default -fpic is more aggressive than GCC -fpic: interprocedural
optimizations (including inlining) are available but local aliases are not used.
-fpic -fsemantic-interposition can disable interprocedural optimizations.

Depends on D101875

Reviewed By: luismarques

Differential Revision: https://reviews.llvm.org/D101876
The file was modifiedclang/test/Driver/fsemantic-interposition.c
The file was modifiedclang/lib/Driver/ToolChains/Clang.cpp
Commit f90abac6caab3b44e6a000de8cb72d204e74eb76 by michael.p.rice
[OpenMP] Use compound operators for reduction combiner if available.

The OpenMP spec seems to require the compound operators be used for
+, *, &, |, and ^ reduction.  So use these if a class has those operators.
If not try the simple operators as we did previously to limit the impact
to existing code.

Fixes: https://bugs.llvm.org/show_bug.cgi?id=48584

Differential Revision: https://reviews.llvm.org/D101941
The file was modifiedclang/test/OpenMP/target_simd_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/target_teams_distribute_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/parallel_for_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/taskloop_in_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/teams_distribute_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/target_teams_distribute_parallel_for_simd_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/teams_distribute_simd_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/simd_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/for_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/teams_distribute_parallel_for_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/parallel_sections_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/target_parallel_for_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/target_teams_distribute_parallel_for_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/target_parallel_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/distribute_parallel_for_simd_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/target_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/parallel_master_taskloop_simd_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/parallel_master_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/parallel_for_simd_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/master_taskloop_in_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/nvptx_target_parallel_reduction_codegen_tbaa_PR46146.cpp
The file was modifiedclang/test/OpenMP/task_in_reduction_message.cpp
The file was modifiedclang/test/OpenMP/taskloop_reduction_messages.cpp
The file was modifiedclang/lib/Sema/SemaOpenMP.cpp
The file was modifiedclang/test/OpenMP/taskloop_simd_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/target_parallel_for_simd_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/master_taskloop_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/master_taskloop_simd_in_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/master_taskloop_simd_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/parallel_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/for_simd_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/parallel_master_taskloop_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/target_teams_distribute_simd_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/taskgroup_task_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/distribute_parallel_for_reduction_messages.cpp
The file was addedclang/test/OpenMP/reduction_compound_op.cpp
The file was modifiedclang/test/OpenMP/distribute_simd_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/target_teams_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/teams_distribute_parallel_for_simd_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/teams_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/sections_reduction_messages.cpp
The file was modifiedclang/test/OpenMP/taskloop_simd_in_reduction_messages.cpp
Commit 384dd9ddaf616a1563ee1c1a8a1347b7658e7a70 by vvereschaka
[libc++] Run `substitutes-in-compile-flags.sh.cpp` test on Windows.

Fix for substitutes-in-compile-flags.sh.cpp to run it properly on Windows platform.

Differential Revision: https://reviews.llvm.org/D102048
The file was modifiedlibcxx/test/libcxx/selftest/additional_compile_flags/substitutes-in-compile-flags.sh.cpp
Commit 9558b602b22cb7d681757c5f56d941e39a9d9d19 by jingham
Add an "interrupt timeout" to Process, and pipe that through the
ProcessGDBRemote plugin layers.

Also fix a bug where if we tried to interrupt, but the ReadPacket
wakeup timer woke us up just after the timeout, we would break out
the switch, but then since we immediately check if the response is
empty & fail if it is, we could end up actually only giving a
small interval to the interrupt.

Differential Revision: https://reviews.llvm.org/D102085
The file was modifiedlldb/source/Plugins/Process/gdb-remote/GDBRemoteClientBase.cpp
The file was modifiedlldb/source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext.cpp
The file was modifiedlldb/unittests/Process/gdb-remote/GDBRemoteClientBaseTest.cpp
The file was modifiedlldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp
The file was modifiedlldb/unittests/Process/gdb-remote/GDBRemoteCommunicationClientTest.cpp
The file was modifiedlldb/include/lldb/Target/Process.h
The file was modifiedlldb/source/Target/Process.cpp
The file was modifiedlldb/source/Target/TargetProperties.td
The file was modifiedlldb/test/API/functionalities/gdb_remote_client/TestHaltFails.py
The file was modifiedlldb/source/Plugins/Process/gdb-remote/GDBRemoteClientBase.h
The file was modifiedlldb/source/Plugins/Platform/gdb-server/PlatformRemoteGDBServer.cpp
The file was modifiedlldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
The file was modifiedlldb/unittests/tools/lldb-server/tests/TestClient.cpp
The file was modifiedlldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.h
Commit b49a798e71f922a68628ad9e31ca12fdb864c2f5 by sbc
[lld][WebAssembly] Remove relocation target verification

We have this extra step in wasm-ld that doesn't exist in other lld
backend which verifies the existing contents of the relocation targets.
This was originally intended as an extra form of double checking and an
aid to compiler developers.   However it has always been somewhat
controversial and there have been suggestions in the past the we simply
remove it.

My motivation for removing it now is that its causing me a headache
when trying to fix an issue with negative addends.  In the case of
negative addends that final result can be wrapped/negative but this
checking code would require significant modification to be able to deal
with that case.  For example with some test cases I'm looking at I'm
seeing error like this:

```
wasm-ld: warning: /usr/local/google/home/sbc/dev/wasm/llvm-build/tools/lld/test/wasm/Output/merge-string.s.tmp.o:(.rodata_relocs): unexpected existing value for R_WASM_MEMORY_ADDR_I32: existing=FFFFFFFA expected=FFFFFFFFFFFFFFFA
```

Rather than try to refactor `calcExpectedValue` to somehow return two
different types of results (32 and 64-bit) depending on the relocation
type, I think we can just remove this code.

Differential Revision: https://reviews.llvm.org/D102265
The file was modifiedlld/wasm/InputFiles.h
The file was modifiedlld/test/wasm/reloc-addend.s
The file was modifiedlld/wasm/InputChunks.cpp
The file was modifiedlld/wasm/InputFiles.cpp
Commit 731206f3684af5979e3a794970db83f9a34b4541 by riddleriver
[mlir] Move move capture in SparseElementsAttr::getValues

This was a TODO for the move to C++14. Now that the move has been completed, we can resolve it.
The file was modifiedmlir/include/mlir/IR/BuiltinAttributes.h
Commit 2a73b7bd8cf7620fc0e478ac838b07ee6649dd8a by Vitaly Buka
[NFC][LSAN] Limit the number of concurrent threads is the test

Test still fails with D88184 reverted.

The test was flaky on https://bugs.chromium.org/p/chromium/issues/detail?id=1206745 and
https://lab.llvm.org/buildbot/#/builders/sanitizer-x86_64-linux

Reviewed By: morehouse

Differential Revision: https://reviews.llvm.org/D102218
The file was modifiedcompiler-rt/test/lsan/TestCases/many_threads_detach.cpp
Commit 69069509b2d3cb0e0bcf6e38e0ab05c432adc763 by Amara Emerson
[AArch64][GlobaISel] Mark target generic instructions as HasNoSideEffects.

One test needed updating because the newly side-effect-free instructions were
now being DCE'd.
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/select-ext.mir
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrGISel.td
Commit ffbffaf6b6b0fc06abb7b43ec8de8bc61d941bc7 by albionapc
[PowerPC] Improve codegen for int-to-fp conversion of subword vector extract

When an integer is converted into floating point in subword vector extract,
it can be done in 2 instructions instead of the 3+ instructions it generates
right now. This patch removes the uncessary generation.

Differential: https://reviews.llvm.org/D100604
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrVSX.td
The file was modifiedllvm/test/CodeGen/PowerPC/uint-to-fp-v4i32.ll
The file was addedllvm/test/CodeGen/PowerPC/vec-extract-itofp.ll
The file was modifiedllvm/test/CodeGen/PowerPC/vec_conv_i16_to_fp32_elts.ll
The file was modifiedllvm/test/CodeGen/PowerPC/vec_conv_i8_to_fp32_elts.ll
Commit 4fb0aaf03381473ec8af727edb4b5d59b64b0d60 by Andrey.Churbanov
[OpenMP] Changes to enable MSVC ARM64 build of libomp

This is the first in a series of changes to the OpenMP runtime
that have been done internally by Microsoft. This patch makes
the necessary changes to enable libomp.dll to build with
the MSVC compiler targeting ARM64.

Differential Revision: https://reviews.llvm.org/D101173
The file was modifiedopenmp/runtime/src/dllexports
The file was modifiedopenmp/runtime/src/CMakeLists.txt
The file was modifiedopenmp/runtime/src/kmp_atomic.cpp
The file was modifiedopenmp/runtime/src/kmp_platform.h
The file was modifiedopenmp/runtime/src/z_Windows_NT-586_util.cpp
The file was modifiedopenmp/runtime/src/kmp.h
The file was modifiedopenmp/runtime/src/kmp_os.h
Commit d092dd56aed8af64425446544ca7c9a0616d86ce by craig.topper
[RISCV] Regenerate stepvector.ll. NFC

It looks like the RV32 and RV64 prefixes were removed from the
RUN lines while another patch was in review that added check
lines that used them.
The file was modifiedllvm/test/CodeGen/RISCV/rvv/stepvector.ll
Commit a7757f6c22e45e84e56da79af67fe29dd1c224f5 by eugenis
[hwasan] Stress test for thread creation.

This test has two modes - testing reused threads with multiple loops of
batch create/join, and testing new threads with a single loop of
create/join per fork.

The non-reuse variant catches the problem that was fixed in D101881 with
a high probability.

Differential Revision: https://reviews.llvm.org/D101936
The file was addedcompiler-rt/test/hwasan/TestCases/Linux/create-thread-stress.cpp
Commit 4433f4601e8a8e36ddd9bb6f6ed394bda353b828 by Austin.Kerbow
[AMDGPU] Fix extra waitcnt being added with BUFFER_INVL2

The waitcnt pass would increment the number of vmem events for some buffer
invalidates that were not handled by the pass.

Reviewed By: rampitec

Differential Revision: https://reviews.llvm.org/D102252
The file was modifiedllvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
The file was modifiedllvm/lib/Target/AMDGPU/BUFInstructions.td
The file was modifiedllvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/waitcnt-preexisting.mir
The file was modifiedllvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
Commit ebdcebfcb4b522a81290f67dcbb7222ff7f9d052 by aorlov
Removed unnecessary introduction of semi-colons.
The file was modifiedllvm/include/llvm/DebugInfo/Symbolize/DIPrinter.h
Commit a9bbbaaa8810b22c9672694d576e3a0a210af54a by riddleriver
[mlir] Elide large elements attrs when printing Operations in diagnostics

Diagnostics are intended to be read by users, and in most cases displayed in a terminal. When not eliding huge element attributes, in some cases we end up dumping hundreds of megabytes(gigabytes) to the terminal (or logs), completely obfuscating the main diagnostic being shown.

Differential Revision: https://reviews.llvm.org/D102272
The file was modifiedmlir/lib/IR/Diagnostics.cpp
Commit 764ad3b3fafbf57ca916715625fffb7df5dbeb92 by rob.suderman
[mlir][tosa] Tosa elementwise broadcasting had some minor bugs

Updated tests to include broadcast of left and right. Includes
bypass if in-type and out-type match shape (no broadcasting).

Differential Revision: https://reviews.llvm.org/D102276
The file was modifiedmlir/test/Conversion/TosaToLinalg/tosa-to-linalg.mlir
The file was modifiedmlir/lib/Conversion/TosaToLinalg/TosaToLinalg.cpp