Progress:
Changes

Changes from Git (git http://labmaster3.local/git/llvm-project.git)

Summary

  1. [fir] Add data flow optimization pass (details)
  2. [X86][Costmodel] Now that `getReplicationShuffleCost()` is good, update `getInterleavedMemoryOpCostAVX512()` (details)
  3. [AArch64][SVE] Mark fixed-type FP extending/truncating loads/stores as custom (details)
  4. Use a deterministic order when updating the DominatorTree (details)
  5. fix typos in comments (details)
  6. [NFC][X86][LV][Costmodel] Add most basic test for masked interleaved load (details)
  7. Don't consider 'LinkageSpec' when calculating DeclContext 'Encloses' (details)
  8. [CodeGen][AArch64] Bail out in performConcatVectorsCombine for scalable vectors (details)
  9. [clang-format] regressed default behavior for operator parentheses (details)
  10. Reapply 'Implement target_clones multiversioning' (details)
  11. [mlir][memref] Fix bug in verification of memref.collapse_shape (details)
  12. [X86] Add vector test coverage for or with no common bits tests (details)
  13. [AMDGPU] Fix "must generated" typo in docs (details)
  14. [AMDGPU] Fix list indentation in docs (details)
  15. [AMDGPU][GlobalISel] Transform (fadd (fmul x, y), z) -> (fma x, y, z) (details)
  16. [AMDGPU][GlobalISel] Transform (fadd (fpext (fmul x, y)), z) -> (fma (fpext x), (fpext y), z) (details)
  17. [AMDGPU][GlobalISel] Transform (fadd (fma x, y, (fmul u, v)), z) -> (fma x, y, (fma u, v, z)) (details)
  18. [AMDGPU][GlobalISel] Transform (fadd (fma x, y, (fpext (fmul u, v))), z) -> (fma x, y, (fma (fpext u), (fpext v), z)) (details)
  19. [AMDGPU][GlobalISel] Transform (fsub (fmul x, y), z) -> (fma x, y, -z) (details)
  20. [AMDGPU][GlobalISel] Transform (fsub (fneg (fmul, x, y)), z) -> (fma (fneg x), y, (fneg z)) (details)
  21. [AMDGPU][GlobalISel] Transform (fsub (fpext (fmul x, y)), z) -> (fma (fpext x), (fpext y), (fneg z)) (details)
  22. [AMDGPU][GlobalISel] Transform (fsub (fpext (fneg (fmul x, y))), z) -> (fneg (fma (fpext x), (fpext y), z)) (details)
  23. [X86][Costmodel] `getInterleavedMemoryOpCostAVX512()`: masked load can not be folded into a shuffle (details)
  24. [fir] Get rid of the global option in FIRBuilder (details)
  25. [HWASan] Disable LTO test on aarch64. (details)
  26. [SCEV] Remove incorrect assert (details)
  27. [InstCombine] Fold (~A | B) ^ A --> ~(A & B) (details)
  28. [llvm] Use range-based for loops (NFC) (details)
  29. [mlir] Handle an edge case when folding reshapes with multiple trailing 1 dimensions (details)
  30. [LLDB][NativePDB] fix find-functions.cpp failure on windows bots (details)
  31. [NFC][AIX]Disable unsupported hip test on AIX (details)
  32. [libc++] Fix incorrect REQUIRES on a locale-dependent test (details)
  33. OpenMP: Start calling setTargetAttributes for generated kernels (details)
  34. [LLDB][NativePDB] fix find-functions.cpp failure on windows bots (2) (details)
  35. [HIP] Add atomic load, atomic store and atomic cmpxchng_weak builtin support in HIP-clang (details)
  36. [NFC][clang]Increase the number of driver diagnostics (details)
  37. [InstCombine] (~(a | b) & c) | ~(c | (a ^ b)) -> ~((a | b) & (c | (b ^ a))) (details)
  38. [InstCombine] add tests for or with mul operand; NFC (details)
  39. [LICM] Regenerate test checks (NFC) (details)
  40. [mlir][sparse] some leftover cleanup from migration to bufferization dialect (details)
  41. Revert "OpenMP: Start calling setTargetAttributes for generated kernels" (details)
Commit 2e7202b0082fd0e22589949aa4d3472d201949b2 by clementval
[fir] Add data flow optimization pass

Add pass to perform store/load forwarding and potentially removing dead
stores.

This patch is part of the upstreaming effort from fir-dev branch.

Reviewed By: kiranchandramohan, schweitz, mehdi_amini, awarzynski

Differential Revision: https://reviews.llvm.org/D111288
The file was addedflang/lib/Optimizer/Transforms/MemRefDataFlowOpt.cpp
The file was modifiedflang/include/flang/Optimizer/Transforms/Passes.h
The file was modifiedflang/include/flang/Optimizer/Transforms/Passes.td
The file was modifiedflang/lib/Optimizer/Transforms/CMakeLists.txt
The file was addedflang/test/Fir/memref-data-flow.fir
Commit cffe3a084f87ad2ed17aeebc1075eb100182114e by lebedev.ri
[X86][Costmodel] Now that `getReplicationShuffleCost()` is good, update `getInterleavedMemoryOpCostAVX512()`

... to actually ask about i1-elt-wide mask, since that is what will probably be used on AVX512.
This unblocks D111460.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D114316
The file was modifiedllvm/test/Analysis/CostModel/X86/interleaved-store-accesses-with-gaps.ll
The file was modifiedllvm/lib/Target/X86/X86TargetTransformInfo.cpp
Commit 61808066325ff0828bab7f016e8798b78d2e6b49 by bradley.smith
[AArch64][SVE] Mark fixed-type FP extending/truncating loads/stores as custom

This allows the generic DAG combine to fold fp_extend/fp_trunc into
loads/stores which we can then lower into a integer extending
load/truncating store plus an FP_EXTEND/FP_ROUND.

The nuance here is that fixed-type FP_EXTEND/FP_ROUND require unpacked
types hence lowering them introduces an unpack/zip. By allowing these
nodes to be combined with loads/store we make it much easier to have
this unpack/zip combined into the load/store by our custom lowering.

Differential Revision: https://reviews.llvm.org/D114580
The file was modifiedllvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp
The file was modifiedllvm/test/CodeGen/AArch64/sve-fixed-length-fp-extend-trunc.ll
Commit 297fb66484c73d3a04e8974921e94cb00c1587c2 by bjorn.a.pettersson
Use a deterministic order when updating the DominatorTree

This solves a problem with non-deterministic output from opt due
to not performing dominator tree updates in a deterministic order.

The problem that was analysed indicated that JumpThreading was using
the DomTreeUpdater via llvm::MergeBasicBlockIntoOnlyPred. When
preparing the list of updates to send to DomTreeUpdater::applyUpdates
we iterated over a SmallPtrSet, which didn't give a well-defined
order of updates to perform.

The added domtree-updates.ll test case is an example that would
result in non-deterministic printouts of the domtree. Semantically
those domtree:s are equivalent, but it show the fact that when we
use the domtree iterator the order in which nodes are visited depend
on the order in which dominator tree updates are performed.

Since some passes (at least EarlyCSE) are iterating over nodes in the
dominator tree in a similar fashion as the domtree printer, then the
order in which transforms are applied by such passes, transitively,
also depend on the order in which dominator tree updates are
performed. And taking EarlyCSE as an example the end result could be
different depending on in which order the transforms are applied.

Reviewed By: nikic, kuhar

Differential Revision: https://reviews.llvm.org/D110292
The file was modifiedllvm/include/llvm/Support/GenericDomTree.h
The file was modifiedllvm/lib/CodeGen/IndirectBrExpandPass.cpp
The file was modifiedllvm/lib/Transforms/Utils/Local.cpp
The file was modifiedllvm/lib/Transforms/Utils/BasicBlockUtils.cpp
The file was addedllvm/test/Transforms/JumpThreading/domtree-updates.ll
The file was modifiedllvm/lib/Transforms/Utils/SimplifyCFG.cpp
Commit d96f92ff16edab72cf78811673f02371f07a5a70 by sylvestre
fix typos in comments
The file was modifiedclang-tools-extra/clang-doc/ClangDoc.h
The file was modifiedllvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp
The file was modifiedllvm/test/tools/llvm-objcopy/ELF/Inputs/ihex-elf-sections.yaml
Commit 5e96553608a1bbf688f11c76890dc543c5f89c61 by lebedev.ri
[NFC][X86][LV][Costmodel] Add most basic test for masked interleaved load
The file was removedllvm/test/Analysis/CostModel/X86/interleaved-store-accesses-with-gaps.ll
The file was addedllvm/test/Analysis/CostModel/X86/masked-interleaved-load-i16.ll
The file was addedllvm/test/Analysis/CostModel/X86/masked-interleaved-store-i16.ll
Commit 90010c2e1d60c6a9a4a0b30a113d4dae2b7214eb by erich.keane
Don't consider 'LinkageSpec' when calculating DeclContext 'Encloses'

We don't properly handle lookup through using directives when there is
a linkage spec in the common chain.  This is because `CppLookupName` and
`CppNamespaceLookup` end up skipping `LinkageSpec`'s (correctly, as they
are not lookup scopes), but the `UnqualUsingDirectiveSet` does not.

I discovered that when we are calculating the `CommonAncestor` for a
using-directive, we were coming up with the `LinkageSpec`, instead of
the `LinkageSpec`'s parent.  Then, when we use
`UnqualUsingDirectiveSet::getNamespacesFor` a scope, we don't end up
finding any that were in the `LinkageSpec` (again, since `CppLookupName`
skips linkage specs), so those don't end up participating in the lookup.

The function `UnqualUsingDirectiveSet::addUsingDirective` calculates
this common ancestor via a loop through the the `DeclSpec::Encloses`
function.

Changing this Encloses function to believe that a `LinkageSpec`
`Encloses` nothing ends up fixing the problem without breaking any other tests,
so I opted to do that.  A less aggressive patch could perhaps change only
the `addUsingDirective`, but my examination of all uses of `Encloses`
showed that it seems to be used exclusively in lookup, which makes me think
this is correct everywhere.

Differential Revision: https://reviews.llvm.org/D113709
The file was modifiedclang/lib/AST/DeclBase.cpp
The file was addedclang/test/SemaCXX/lookup-through-linkage.cpp
Commit 84364bdaabfca35f083c932ffd3a14f3b9ad4f3a by david.sherwood
[CodeGen][AArch64] Bail out in performConcatVectorsCombine for scalable vectors

I tried to exercise the existing combine patterns in performConcatVectorsCombine
for scalable vectors and at the moment it doesn't seem possible. Parts of
the code currently assume we're dealing with fixed-width vectors with calls
to getVectorNumElements(), therefore I've decided to simply bail out early
for scalable vectors.

Added a test here to show that we don't crash when attempting to combine
truncate + concat:

  CodeGen/AArch64/concat_vector-truncate-combine.ll

Differential Revision: https://reviews.llvm.org/D114600
The file was modifiedllvm/test/CodeGen/AArch64/concat_vector-truncate-combine.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp
Commit 814aabae37757d21d96e22608ccb98e91c1f3a06 by mydeveloperday
[clang-format] regressed default behavior for operator parentheses

{D110833} regressed behavior of spaces before parentheses for operators, this revision reverts that so that operators are handled as they were before.

I think in hindsight it was a mistake to try and consume operator behaviour in with the function behaviour, I think Operators can be considered a special style. Its seems the code is getting confused as to if this is a function declaration or definition.

I think latterly we can consider adding an operator parentheses specific custom option but this should have been explicitly called out as it can impact projects.

Reviewed By: HazardyKnusperkeks, curdeius

Differential Revision: https://reviews.llvm.org/D114696
The file was modifiedclang/lib/Format/TokenAnnotator.cpp
The file was modifiedclang/unittests/Format/FormatTest.cpp
Commit fc53eb69c26cdd7efa6b629c187d04326f0448ca by erich.keane
Reapply 'Implement target_clones multiversioning'

See discussion in D51650, this change was a little aggressive in an
error while doing a 'while we were here', so this removes that error
condition, as it is apparently useful.

This reverts commit bb4934601d731465e01e2e22c80ce2dbe687d73f.
The file was modifiedclang/test/Sema/attr-cpuspecific.c
The file was modifiedclang/include/clang/Basic/DiagnosticSemaKinds.td
The file was modifiedclang/lib/Sema/SemaDecl.cpp
The file was modifiedclang/lib/Sema/SemaDeclAttr.cpp
The file was modifiedclang/lib/CodeGen/CodeGenModule.h
The file was addedclang/test/CodeGen/attr-target-clones.c
The file was modifiedclang/include/clang/AST/Decl.h
The file was addedclang/test/CodeGenCXX/attr-target-clones.cpp
The file was modifiedclang/include/clang/Basic/DiagnosticGroups.td
The file was modifiedclang/include/clang/Basic/AttrDocs.td
The file was modifiedclang/lib/CodeGen/CodeGenModule.cpp
The file was modifiedclang/lib/AST/ASTContext.cpp
The file was modifiedclang/test/Misc/pragma-attribute-supported-attributes-list.test
The file was modifiedclang/include/clang/Basic/Attr.td
The file was addedclang/test/SemaCXX/attr-target-clones.cpp
The file was addedclang/test/Sema/attr-target-clones.c
The file was modifiedclang/include/clang/Sema/Sema.h
The file was modifiedclang/lib/AST/Decl.cpp
Commit 95f34e318c469806879a0cd1a6c5290901ed12df by herhut
[mlir][memref] Fix bug in verification of memref.collapse_shape

The verifier computed an illegal type with negative dimension size when collapsing partially static memrefs.

Differential Revision: https://reviews.llvm.org/D114702
The file was modifiedmlir/lib/Dialect/MemRef/IR/MemRefOps.cpp
The file was modifiedmlir/test/Dialect/MemRef/ops.mlir
Commit a7363067e69a60442a1d52e93207ed7a86ce9d6a by spatel
[X86] Add vector test coverage for or with no common bits tests

Ensure D113970 handles vector types patterns as well.

Differential Revision: https://reviews.llvm.org/D114575
The file was addedllvm/test/CodeGen/X86/vec_no-common-bits.ll
Commit 7319d11586c4aa836204316a5be7cd71cfe5e05d by jay.foad
[AMDGPU] Fix "must generated" typo in docs
The file was modifiedllvm/docs/AMDGPUUsage.rst
Commit 65d9dc7f1f4ac5b4d76502d36bd81d9857538148 by jay.foad
[AMDGPU] Fix list indentation in docs
The file was modifiedllvm/docs/AMDGPUUsage.rst
Commit 881840fc268e6523b71b40e717c647ed45682816 by Mirko.Brkusanin
[AMDGPU][GlobalISel] Transform (fadd (fmul x, y), z) -> (fma x, y, z)

Patch by: Mateja Marjanovic

Differential Revision: https://reviews.llvm.org/D93305
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-mul-post-legalize.mir
The file was modifiedllvm/lib/Target/AMDGPU/SIISelLowering.h
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-mul.ll
The file was modifiedllvm/include/llvm/Target/GlobalISel/Combine.td
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-mul-pre-legalize.mir
The file was modifiedllvm/include/llvm/CodeGen/TargetLowering.h
The file was modifiedllvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
The file was modifiedllvm/lib/Target/AMDGPU/SIISelLowering.cpp
Commit 89511362165332695bf0e26767662b47f8e11f98 by Mirko.Brkusanin
[AMDGPU][GlobalISel] Transform (fadd (fpext (fmul x, y)), z) -> (fma (fpext x), (fpext y), z)

Patch by: Mateja Marjanovic

Differential Revision: https://reviews.llvm.org/D97937
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-ext-mul.ll
The file was modifiedllvm/lib/Target/AMDGPU/SIISelLowering.cpp
The file was modifiedllvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
The file was modifiedllvm/lib/Target/AMDGPU/SIISelLowering.h
The file was modifiedllvm/include/llvm/Target/GlobalISel/Combine.td
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
The file was modifiedllvm/include/llvm/CodeGen/TargetLowering.h
Commit f7322925365c165e8e92a699a2a699b6fe04f6d5 by Mirko.Brkusanin
[AMDGPU][GlobalISel] Transform (fadd (fma x, y, (fmul u, v)), z) -> (fma x, y, (fma u, v, z))

Patch by: Mateja Marjanovic

Differential Revision: https://reviews.llvm.org/D97938
The file was modifiedllvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-fma-mul.ll
The file was modifiedllvm/include/llvm/Target/GlobalISel/Combine.td
Commit e5e49a08f11618653aca133f22603c165889505e by Mirko.Brkusanin
[AMDGPU][GlobalISel] Transform (fadd (fma x, y, (fpext (fmul u, v))), z) -> (fma x, y, (fma (fpext u), (fpext v), z))

Patch by: Mateja Marjanovic

Differential Revision: https://reviews.llvm.org/D98047
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-ext-fma.ll
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
The file was modifiedllvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
The file was modifiedllvm/include/llvm/Target/GlobalISel/Combine.td
Commit a7821692708c413d7a2488137dea2fbbfac31ca7 by Mirko.Brkusanin
[AMDGPU][GlobalISel] Transform (fsub (fmul x, y), z) -> (fma x, y, -z)

Patch by: Mateja Marjanovic

Differential Revision: https://reviews.llvm.org/D96614
The file was modifiedllvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
The file was modifiedllvm/include/llvm/Target/GlobalISel/Combine.td
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-mul.ll
Commit 5fe7fcd28e5e7df174a46a78e19316856152eefa by Mirko.Brkusanin
[AMDGPU][GlobalISel] Transform (fsub (fneg (fmul, x, y)), z) -> (fma (fneg x), y, (fneg z))

Patch by: Mateja Marjanovic

Differential Revision: https://reviews.llvm.org/D98048
The file was modifiedllvm/include/llvm/Target/GlobalISel/Combine.td
The file was modifiedllvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-neg-mul.ll
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
Commit 37c2a2201d683383d3683321ff1f33fd8dd22298 by Mirko.Brkusanin
[AMDGPU][GlobalISel] Transform (fsub (fpext (fmul x, y)), z) -> (fma (fpext x), (fpext y), (fneg z))

Patch by: Mateja Marjanovic

Differential Revision: https://reviews.llvm.org/D98049
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-ext-mul.ll
The file was modifiedllvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
The file was modifiedllvm/include/llvm/Target/GlobalISel/Combine.td
Commit 0dd570ff56c53dd6d11305fb0b36edab69eb1484 by Mirko.Brkusanin
[AMDGPU][GlobalISel] Transform (fsub (fpext (fneg (fmul x, y))), z) -> (fneg (fma (fpext x), (fpext y), z))

Patch by: Mateja Marjanovic

Differential Revision: https://reviews.llvm.org/D98050
The file was modifiedllvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-ext-neg-mul.ll
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
The file was modifiedllvm/include/llvm/Target/GlobalISel/Combine.td
Commit 7e73c2a66a8bb73b80aedc94c4e58598ac87e9d5 by lebedev.ri
[X86][Costmodel] `getInterleavedMemoryOpCostAVX512()`: masked load can not be folded into a shuffle

The mask on the shuffle is for the output, not the input.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D114697
The file was modifiedllvm/lib/Target/X86/X86TargetTransformInfo.cpp
The file was modifiedllvm/test/Analysis/CostModel/X86/masked-interleaved-load-i16.ll
Commit 1cc3b135aa61a31a7f7e488dd720e29bd8907bfc by clementval
[fir] Get rid of the global option in FIRBuilder

Replace the global option `nameLengthHashSize` with a constexpr
with the same name. The option was not used in fir-dev so switching
to a constexpr is fine.

Reviewed By: kiranchandramohan

Differential Revision: https://reviews.llvm.org/D114630
The file was modifiedflang/lib/Optimizer/Builder/FIRBuilder.cpp
Commit 2022e2fcd05c68a38c4b5ef865461c9c86a81997 by mascasa
[HWASan] Disable LTO test on aarch64.

It fails for non-Android aarch64 bots as well.
The file was modifiedcompiler-rt/test/hwasan/TestCases/lto.c
Commit 77dd579827f2e7574be4bbf3f94a48930e7b094f by nikita.ppv
[SCEV] Remove incorrect assert

Fix assertion failure reported on D113349 by removing the assert.
While the produced expression should be equivalent, it may not
be strictly the same, e.g. due to lazy nowrap flag updates. Similar
to what the main createSCEV() code does, simply retain the old
value map entry if one already exists.
The file was modifiedllvm/lib/Analysis/ScalarEvolution.cpp
The file was addedllvm/test/Analysis/ScalarEvolution/addrec-computed-during-addrec-calculation.ll
Commit c572eb1ad9d8a528bcaff0160888aff31b1f4b5f by mehrnoosh.heidarpour
[InstCombine] Fold (~A | B) ^ A --> ~(A & B)

https://alive2.llvm.org/ce/z/gLrYPk

Fixes:
https://llvm.org/PR52518

Reviewed by: spatel

Differential revision: https://reviews.llvm.org/D114339
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
The file was modifiedllvm/test/Transforms/InstCombine/xor.ll
Commit f240e528cea25fd2a9ae01b1e1fe77f507ed7a2c by kazu
[llvm] Use range-based for loops (NFC)
The file was modifiedllvm/lib/CodeGen/MachinePipeliner.cpp
The file was modifiedllvm/lib/Object/ELFObjectFile.cpp
The file was modifiedllvm/lib/ProfileData/InstrProf.cpp
The file was modifiedllvm/lib/ObjectYAML/COFFEmitter.cpp
The file was modifiedllvm/lib/CodeGen/SelectionDAG/ResourcePriorityQueue.cpp
The file was modifiedllvm/lib/Target/Hexagon/HexagonCommonGEP.cpp
The file was modifiedllvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
The file was modifiedllvm/lib/Passes/StandardInstrumentations.cpp
Commit 8d474f1d157530577f06ce3ef9187e1aaf31a59e by benny.kra
[mlir] Handle an edge case when folding reshapes with multiple trailing 1 dimensions

We would exit early and miss this case.

Differential Revision: https://reviews.llvm.org/D114711
The file was modifiedmlir/test/Dialect/Linalg/canonicalize.mlir
The file was modifiedmlir/lib/Dialect/Utils/ReshapeOpsUtils.cpp
Commit 34d02fada28753221eda576e2f651f9b23c3f1af by zequanwu
[LLDB][NativePDB] fix find-functions.cpp failure on windows bots
The file was modifiedlldb/test/Shell/SymbolFile/NativePDB/find-functions.cpp
Commit 23dc886226306d961c31987db9aad137a69ad539 by wanyu9511
[NFC][AIX]Disable unsupported hip test on AIX

AIX doesn't support GPU. There is no point testing HIP on it.

Reviewed By: Jake-Egan

Differential Revision: https://reviews.llvm.org/D114484
The file was modifiedclang/test/Driver/hip-version.hip
Commit a8278a747ddf9e56262dafddd7c03e29cd85d074 by Louis Dionne
[libc++] Fix incorrect REQUIRES on a locale-dependent test

The test doesn't depend specifically on the en_US.UTF-8 locale, instead
it depends on whether localization support exists, period.

Differential Revision: https://reviews.llvm.org/D114708
The file was modifiedlibcxx/test/libcxx/iterators/iterator.requirements/iterator.assoc.types/iterator.traits/locale_dependent.compile.pass.cpp
Commit 6c27d389c8a00040aad998fe959f38ba709a8750 by Matthew.Arsenault
OpenMP: Start calling setTargetAttributes for generated kernels

This wasn't setting any of the attributes the target would expect to
emit for kernels.
The file was modifiedclang/lib/CodeGen/CGOpenMPRuntime.cpp
The file was modifiedclang/lib/CodeGen/TargetInfo.cpp
The file was addedclang/test/OpenMP/amdgcn-attributes.cpp
Commit fe270ab061fa1200d1f7e121ac6671f7d24b73d6 by zequanwu
[LLDB][NativePDB] fix find-functions.cpp failure on windows bots (2)
The file was modifiedlldb/test/Shell/SymbolFile/NativePDB/find-functions.cpp
Commit df0560ca00182364e0a786d35adb294c3c98dbd0 by Anshil.Gandhi
[HIP] Add atomic load, atomic store and atomic cmpxchng_weak builtin support in HIP-clang

Introduce `__hip_atomic_load`, `__hip_atomic_store` and `__hip_atomic_compare_exchange_weak`
builtins in HIP.

Reviewed By: yaxunl

Differential Revision: https://reviews.llvm.org/D114553
The file was modifiedclang/include/clang/AST/Expr.h
The file was modifiedclang/lib/Sema/SemaChecking.cpp
The file was modifiedclang/test/CodeGenCUDA/atomic-ops.cu
The file was modifiedclang/lib/AST/StmtPrinter.cpp
The file was modifiedclang/include/clang/Basic/Builtins.def
The file was modifiedclang/lib/CodeGen/CGAtomic.cpp
The file was modifiedclang/lib/AST/Expr.cpp
The file was addedclang/test/SemaCUDA/atomic-ops.cu
Commit 3c32c568844c745e3fe7fa72ce3aa65340e545bc by wanyu9511
[NFC][clang]Increase the number of driver diagnostics

We're close to hitting the limited number of driver diagnostics, increase `DIAG_SIZE_DRIVER` to accommodate more.

Reviewed By: erichkeane

Differential Revision: https://reviews.llvm.org/D114615
The file was modifiedclang/include/clang/Basic/DiagnosticIDs.h
Commit 5c6b9e1622b10a543ea4210996d2732a6e5183da by Stanislav.Mekhanoshin
[InstCombine] (~(a | b) & c) | ~(c | (a ^ b)) -> ~((a | b) & (c | (b ^ a)))

```
----------------------------------------
define i3 @src(i3 %a, i3 %b, i3 %c) {
%0:
  %or1 = or i3 %b, %c
  %not1 = xor i3 %or1, 7
  %and1 = and i3 %a, %not1
  %xor1 = xor i3 %b, %c
  %or2 = or i3 %xor1, %a
  %not2 = xor i3 %or2, 7
  %or3 = or i3 %and1, %not2
  ret i3 %or3
}
=>
define i3 @tgt(i3 %a, i3 %b, i3 %c) {
%0:
  %obc = or i3 %b, %c
  %xbc = xor i3 %b, %c
  %o = or i3 %a, %xbc
  %and = and i3 %obc, %o
  %r = xor i3 %and, 7
  ret i3 %r
}
Transformation seems to be correct!
```

Differential Revision: https://reviews.llvm.org/D112955
The file was modifiedllvm/test/Transforms/InstCombine/and-xor-or.ll
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
Commit 142044a0b52f767c11a74aee827c3cf598a68138 by spatel
[InstCombine] add tests for or with mul operand; NFC
The file was modifiedllvm/test/Transforms/InstCombine/or.ll
Commit eee035235ebd76b0e1b62f6dec989874a3102233 by nikita.ppv
[LICM] Regenerate test checks (NFC)
The file was modifiedllvm/test/Transforms/LICM/scalar-promote.ll
The file was modifiedllvm/test/Transforms/LICM/scalar-promote-memmodel.ll
Commit 52668355f481c25131be7a1b4e3498ddf3b0f6d2 by ajcbik
[mlir][sparse] some leftover cleanup from migration to bufferization dialect

Reviewed By: pifon2a

Differential Revision: https://reviews.llvm.org/D114730
The file was modifiedmlir/include/mlir/Dialect/SparseTensor/IR/SparseTensorOps.td
Commit 25eb7fa01d7ebbe67648ea03841cda55b4239ab2 by Matthew.Arsenault
Revert "OpenMP: Start calling setTargetAttributes for generated kernels"

This reverts commit 6c27d389c8a00040aad998fe959f38ba709a8750.

This is failing on the buildbots
The file was modifiedclang/lib/CodeGen/TargetInfo.cpp
The file was modifiedclang/lib/CodeGen/CGOpenMPRuntime.cpp
The file was removedclang/test/OpenMP/amdgcn-attributes.cpp