Changes

Changes from Git (git http://labmaster3.local/git/llvm-zorg.git)

Summary

  1. jenkins: cmake_builder and clang_builder: Ignore error in the test stage (details)
  2. jenkins: Stop uploading the compiler build artifacts to cloud storage (details)
  3. jenkins: Fix the file path pattern for the test results XML files (details)
Commit 8fe2367ba5b3d4b9a713050f81389464058f30bf by Azharuddin Mohammed
jenkins: cmake_builder and clang_builder: Ignore error in the test stage

This allows us to proceed to generating the test result report.
The file was modifiedzorg/jenkins/monorepo_build.py
Commit 3cdd95df20acbae1ec921a18f675bec033a7ed28 by Azharuddin Mohammed
jenkins: Stop uploading the compiler build artifacts to cloud storage

The storage space has been decommissioned.

https://lists.llvm.org/pipermail/llvm-dev/2021-July/151623.html
The file was modifiedzorg/jenkins/jobs/jobs/clang-stage1-RA
The file was modifiedzorg/jenkins/jobs/jobs/clang-stage2-Rthinlto
Commit 56cd66e2a88d32a74817e8392d70e96a536671e1 by Azharuddin Mohammed
jenkins: Fix the file path pattern for the test results XML files

Include all the available test results files in the build directory.
The file was modifiedzorg/jenkins/jobs/jobs/clang-stage1-cmake-RA-incremental
The file was modifiedzorg/jenkins/jobs/jobs/clang-stage1-RA
The file was modifiedzorg/jenkins/jobs/jobs/clang-stage2-Rthinlto

Changes from Git (git http://labmaster3.local/git/llvm-project.git)

Summary

  1. [llvm][Inline] Add interface to return cost-benefit stuff (details)
  2. [AMDGPU] Regenerate anyext test checks (details)
  3. [AMDGPU] Regenerate half test checks (details)
  4. [AMDGPU] Regenerate ctpop16 test checks (details)
  5. [AMDGPU] Regenerate global-load-saddr-to-vaddr test checks (details)
  6. [X86][AVX] Adjust AllowBWIVPERMV3 tolerance to account for VariableCrossLaneShuffleDepth (details)
  7. [Inline] Fix a warning by removing an explicit copy constructor (details)
  8. [GlobalISel] Remove FlagsOp (NFC) (details)
  9. [x86] improve CMOV codegen by pushing add into operands, part 2 (details)
  10. [AMDGPU] Regenerate mul24 test checks (details)
  11. [AMDGPU] Regenerate wave32.ll test checks (details)
  12. [NFC][Codegen][X86] Improve test coverage for repeated insertions of the same scalar into different elements (details)
  13. [OpenMP][NVPTX] Disable OpenMPOpt when building deviceRTLs (details)
  14. [InstCombine] Fix PR47960 - Incorrect transformation of fabs with nnan flag (details)
  15. [JITLink][RISCV] Run new test from 0ad562b48 only if the RISCV backend is enabled (details)
  16. Revert rG939291041bb35b8088e3b61be2b8b3bc950f64a7 "[AMDGPU] Regenerate wave32.ll test checks" (details)
  17. [Attributes] Remove nonnull from UB-implying attributes (details)
Commit 4bdfea2c515275136eaff8de9666e5c2ee913748 by taolq
[llvm][Inline] Add interface to return cost-benefit stuff

Return cost-benefit stuff which is computed by cost-benefit analysis.

Reviewed By: mtrofin

Differential Revision: https://reviews.llvm.org/D105349
The file was modifiedllvm/lib/Analysis/InlineCost.cpp
The file was modifiedllvm/include/llvm/Analysis/InlineCost.h
Commit 97d2277b3774a2344c5519ab6f10d175b8a5653e by llvm-dev
[AMDGPU] Regenerate anyext test checks

To simplify diff in future patch
The file was modifiedllvm/test/CodeGen/AMDGPU/anyext.ll
Commit 249ef1fa823613291b9ea2707e3055472cb8020c by llvm-dev
[AMDGPU] Regenerate half test checks

To simplify diff in future patch
The file was modifiedllvm/test/CodeGen/AMDGPU/half.ll
Commit 00e37c1cd4b6d25a1237625871bba020a2e3f8b7 by llvm-dev
[AMDGPU] Regenerate ctpop16 test checks

To simplify diff in future patch
The file was modifiedllvm/test/CodeGen/AMDGPU/ctpop16.ll
Commit 9591abd74e4d1230ac403a988a00f2eb319aca11 by llvm-dev
[AMDGPU] Regenerate global-load-saddr-to-vaddr test checks

To simplify diff in future patch
The file was modifiedllvm/test/CodeGen/AMDGPU/global-load-saddr-to-vaddr.ll
Commit 15b883f45771bc06d7f726292e03cadf0ece2a9d by llvm-dev
[X86][AVX] Adjust AllowBWIVPERMV3 tolerance to account for VariableCrossLaneShuffleDepth

As noticed on D105390 - we were hardwiring the depth limit for combining to VPERMI2W/VPERMI2B instructions. Not only had we made the limit too low, we hadn't accounted for slow/fast shuffles via the VariableCrossLaneShuffleDepth control
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was modifiedllvm/test/CodeGen/X86/vector-shuffle-v48.ll
The file was modifiedllvm/test/CodeGen/X86/vector-shuffle-512-v64.ll
The file was modifiedllvm/test/CodeGen/X86/insertelement-ones.ll
The file was modifiedllvm/test/CodeGen/X86/min-legal-vector-width.ll
The file was modifiedllvm/test/CodeGen/X86/vector-shuffle-256-v16.ll
The file was modifiedllvm/test/CodeGen/X86/vector-shuffle-128-v16.ll
The file was modifiedllvm/test/CodeGen/X86/x86-interleaved-access.ll
The file was modifiedllvm/test/CodeGen/X86/vector-shuffle-128-v8.ll
Commit 4e288a85283fe632cbdf004abc2ca7a7711823f3 by kazu
[Inline] Fix a warning by removing an explicit copy constructor

This patches fixes the warning:

  llvm/include/llvm/Analysis/InlineCost.h:62:3: error: definition of
  implicit copy assignment operator for 'CostBenefitPair' is
  deprecated because it has a user-declared copy constructor
  [-Werror,-Wdeprecated-copy]

by removing the explicit copy constructor.
The file was modifiedllvm/include/llvm/Analysis/InlineCost.h
Commit 0fc5534ac74a9c431f7f5a6284a4729d3143d22b by kazu
[GlobalISel] Remove FlagsOp (NFC)

The class was introduced without a use on Dec 11, 2018 in commit
cef44a234219e38e1c28c902ff24586150eef682.
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
Commit 1ce05ad619a5904f15f35a5c96ece27ee1991f1c by spatel
[x86] improve CMOV codegen by pushing add into operands, part 2

This is a minimum extension of D106607 to allow folding for
2 non-zero constantsi that can be materialized as immediates..

In the reduced test examples, we save 1 instruction by rolling
the constants into LEA/ADD. In the motivating test from the bullet
benchmark, we absorb both of the constant moves into add ops via
LEA magic, so we reduce by 2 instructions.

Differential Revision: https://reviews.llvm.org/D106684
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was modifiedllvm/test/CodeGen/X86/add-cmov.ll
Commit 54e5ced7e61e38fe1af0aadfb64ed4b629e06268 by llvm-dev
[AMDGPU] Regenerate mul24 test checks

To simplify diffs in future patch
The file was modifiedllvm/test/CodeGen/AMDGPU/mul_uint24-r600.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/mul_int24.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/mul_uint24-amdgcn.ll
Commit 939291041bb35b8088e3b61be2b8b3bc950f64a7 by llvm-dev
[AMDGPU] Regenerate wave32.ll test checks

To simplify diff in future patch
The file was modifiedllvm/test/CodeGen/AMDGPU/wave32.ll
Commit fa0910e6de5d03fe96dceb2377f6f7710cff270c by lebedev.ri
[NFC][Codegen][X86] Improve test coverage for repeated insertions of the same scalar into different elements
The file was modifiedllvm/test/CodeGen/X86/avx-insertelt.ll
Commit f1b8fa55d03315744a88035aa46fbbf9ec6ae622 by tianshilei1992
[OpenMP][NVPTX] Disable OpenMPOpt when building deviceRTLs

We build `deviceRTLs` with `-O1` by default, which also triggers OpenMPOpt. When
the info cache is created, some attributes are removed. As a result, although we
mark a few functions `noinline`, they are still inlined when the bitcode library
is generated. This can cause an issue in middle end optimization.

Reviewed By: jdoerfert

Differential Revision: https://reviews.llvm.org/D106710
The file was modifiedopenmp/libomptarget/deviceRTLs/nvptx/CMakeLists.txt
Commit 7bd361200a7bd86d633058115412a771aea885ca by spatel
[InstCombine] Fix PR47960 - Incorrect transformation of fabs with nnan flag

Bug Fix for PR: https://llvm.org/PR47960

This patch makes sure that the fast math flag used in the 'select'
instruction is the same as the 'fabs' instruction after the transformation.

Differential Revision: https://reviews.llvm.org/D101727
The file was modifiedllvm/test/Transforms/InstCombine/fabs.ll
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
Commit 75077f46e7e4d5c89a6d7cd9a8ae7d740df2f4cd by thakis
[JITLink][RISCV] Run new test from 0ad562b48 only if the RISCV backend is enabled
The file was addedllvm/test/ExecutionEngine/JITLink/RISCV/lit.local.cfg
Commit 34dc4f24f2d38b18cccbc2dc0aaa7cb44cd54313 by llvm-dev
Revert rG939291041bb35b8088e3b61be2b8b3bc950f64a7 "[AMDGPU] Regenerate wave32.ll test checks"

This still breaks buildbots
The file was modifiedllvm/test/CodeGen/AMDGPU/wave32.ll
Commit 99f869c8f00a36dac3c774178b69d05876a29a31 by nikita.ppv
[Attributes] Remove nonnull from UB-implying attributes

From LangRef:

> if the parameter or return pointer is null, poison value is
> returned or passed instead. The nonnull attribute should be
> combined with the noundef attribute to ensure a pointer is not
> null or otherwise the behavior is undefined.

Dropping noundef is sufficient to prevent UB. Including nonnull
in this method just muddies the semantics.
The file was modifiedllvm/lib/IR/Attributes.cpp
The file was modifiedllvm/test/Transforms/DeadArgElim/NoundefAttrs.ll
The file was modifiedllvm/test/Transforms/InstCombine/unused-nonnull.ll