SuccessChanges

Summary

  1. [zorg] Add buildbot for Synopsys ARC (details)
  2. [zorg] Build and test project depends on project enabled in LibcxxAndAbiBuilder (details)
Commit 41979ca6ea64a4f9a46675af188634d4fb40fa75 by danila
[zorg] Add buildbot for Synopsys ARC

Create AWS worker for LLVM Experimental Target : ARC

Reviewed By: gkistanova

Differential Revision: https://reviews.llvm.org/D101345
The file was modifiedbuildbot/osuosl/master/config/workers.py (diff)
The file was modifiedbuildbot/osuosl/master/config/builders.py (diff)
The file was modifiedbuildbot/osuosl/master/config/status.py (diff)
Commit c5e33710b23442d929d6646c71e1e31d0de2f106 by Xiangling.Liao
[zorg] Build and test project depends on project enabled in LibcxxAndAbiBuilder

Build and test project depends on project enabled in LibcxxAndAbiBuilder;
Let all steps respect env passed in;

Differential Revision: https://reviews.llvm.org/D100497
The file was modifiedzorg/buildbot/builders/LibcxxAndAbiBuilder.py (diff)

Summary

  1. [clang-format] Fix build on gcc < 7 introduced in rG9363aa9. (details)
  2. [MLIR][Shape] Fix `shape.broadcast` to standard lowering (details)
  3. [RISCV] Fix stack slot for argument types (Bug 49500) (details)
  4. [NFC][scudo] Suppress "division by zero" warning (details)
  5. [lldb][AArch64] Don't check for VmFlags in smaps files (details)
  6. [SPE] Support constrained float operations on SPE (details)
  7. Improve error messages for attributes in the wrong context. (details)
  8. [NVPTX] Fix unused var warning with asserts disabled (details)
  9. [mlir] Split out Python bindings entry point into a separate file (details)
  10. [Greedy RA] Replace ll to mir test to make more stable to check an error. (details)
  11. [mlir] Support complex numbers in Linalg promotion (details)
  12. [ARM] Ensure CSINC has one use in CSINV combine (details)
  13. [mlir] Add LinalgTransforms dependency on Complex (details)
  14. [RISCV][NFC] Combine identical RV32 and RV64 test checks (details)
  15. Try to fix bots. We shouldn't be setting the entrybuilder's DL to a null one. (details)
  16. [AMDGPU] Allow buildSpillLoadStore in empty bb (details)
  17. Update libstdc++ hack comment (details)
  18. [mlir] Fix top-level comments (NFC) (details)
  19. [mlir] Affine: parallelize affine loops with reductions (details)
  20. [mlir] support max/min lower/upper bounds in affine.parallel (details)
  21. [AArch64][SVE] Move convert.{from,to}.svbool optimization into InstCombine (details)
  22. [AArch64][SVE] Convert svdup(vec, SV_VL1, elm) to insertelement(vec, elm, 0) (details)
  23. [AArch64][SVE] Use SIMD variant of INSR when scalar is the result of a vector extract (details)
Commit 40c2d6188b08f7a1bdd23a8cfdfea8fa998bdff6 by marek.kurdej+llvm.org
[clang-format] Fix build on gcc < 7 introduced in rG9363aa9.

This fixes another bogus build error on gcc, e.g. https://lab.llvm.org/buildbot/#/builders/110/builds/2974.

/home/ssglocal/clang-cmake-x86_64-avx2-linux/clang-cmake-x86_64-avx2-linux/llvm/clang/lib/Format/TokenAnnotator.cpp:3412:34: error: binding ‘const clang::format::FormatStyle’ to reference of type ‘clang::format::FormatStyle&’ discards qualifiers
   auto ShouldAddSpacesInAngles = [&Style = this->Style,
                                  ^
The file was modifiedclang/lib/Format/TokenAnnotator.cpp
Commit eb56fa97de96856bb63e31340598a356056470c5 by frgossen
[MLIR][Shape] Fix `shape.broadcast` to standard lowering

Differential Revision: https://reviews.llvm.org/D101456
The file was modifiedmlir/lib/Conversion/ShapeToStandard/ShapeToStandard.cpp
The file was modifiedmlir/test/Conversion/ShapeToStandard/shape-to-standard.mlir
Commit 43ad058a01881962604a941ae95209fad095aa18 by fraser
[RISCV] Fix stack slot for argument types (Bug 49500)

This is an complementary/alternative fix for D99068. It takes a slightly
different approach by explicitly summing up all of the required split
part type sizes and ensuring we allocate enough space for them. It also
takes the maximum alignment of each part.

Compared with D99068 there are fewer changes to the stack objects in
existing tests. However, @luismarques has shown in that patch that there
are opportunities to reduce our stack usage in the future.

Reviewed By: luismarques

Differential Revision: https://reviews.llvm.org/D99087
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.cpp
The file was modifiedllvm/test/CodeGen/RISCV/vector-abi.ll
The file was modifiedllvm/test/CodeGen/RISCV/stack-slot-size.ll
Commit c50796475d9452a3f62a0c103a78d72649557c0b by Vitaly Buka
[NFC][scudo] Suppress "division by zero" warning
The file was modifiedcompiler-rt/lib/scudo/standalone/secondary.h
Commit f31e390453d255bc6a486bbd5cb990e684b29510 by david.spickett
[lldb][AArch64] Don't check for VmFlags in smaps files

AArch64 kernel builds default to having /smaps and
the "VmFlags" line was added in 3.8. Long before MTE
was supported.

So we can assume that if you're AArch64 with MTE,
you can run this test.

The previous method of checking had a race condition
where the process we read smaps for, could finish before
we get to read the file.

I explored some alternatives but in the end I think
it's fine to just assume we have what we need.

Reviewed By: omjavaid

Differential Revision: https://reviews.llvm.org/D100493
The file was modifiedlldb/packages/Python/lldbsuite/test/lldbtest.py
The file was modifiedlldb/test/API/linux/aarch64/mte_memory_region/TestAArch64LinuxMTEMemoryRegion.py
Commit 56d923efdb692bf2d459203692b164d54f4ffe48 by qiucofan
[SPE] Support constrained float operations on SPE

This patch enables support on SPE for constrained arithmetic and
comparison operations. This fixes bugzilla 50070.

One thing not covered is fcmp vs. fcmps on SPE. Some condition code
generates singaling comparison while some not. In this patch, all are
considered as singaling. So there might be still some issue when
compiling from C code.

Reviewed By: jhibbits

Differential Revision: https://reviews.llvm.org/D101282
The file was modifiedllvm/lib/Target/PowerPC/PPCISelLowering.cpp
The file was addedllvm/test/CodeGen/PowerPC/fp-strict-fcmp-spe.ll
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrSPE.td
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrInfo.td
The file was modifiedllvm/test/CodeGen/PowerPC/fp-strict.ll
Commit 30bbfda01fb6c6c56c55c6729348d9df7f68ac31 by nicholas
Improve error messages for attributes in the wrong context.

verifyFunctionAttrs has a comment that the value V is printed in error messages. The recently added errors for attributes didn't print V. Make them print V.

Change the stringification of AttributeList. Firstly they started with 'PAL[' which stood for ParamAttrsList. Change that to 'AttributeList[' matching its current name AttributeList. Print out semantic meaning of the index instead of the raw index value (i.e. 'return', 'function' or 'arg(n)').

Differential revision: https://reviews.llvm.org/D101484
The file was modifiedllvm/lib/IR/Attributes.cpp
The file was modifiedllvm/unittests/IR/AttributesTest.cpp
The file was modifiedllvm/lib/IR/Verifier.cpp
Commit 54ee962e4795cd00a379e560727dff7ea0743765 by david.spickett
[NVPTX] Fix unused var warning with asserts disabled

<...>/llvm-project/llvm/lib/Target/NVPTX/NVPTXLowerArgs.cpp:191:15:
warning: unused variable ‘ASC’ [-Wunused-variable]
  191 |     if (auto *ASC =
dyn_cast<AddrSpaceCastInst>(I.OldInstruction)) {
      |               ^~~
The file was modifiedllvm/lib/Target/NVPTX/NVPTXLowerArgs.cpp
Commit ac0a70f3737ecb2c0586c00240d14e46ff00644e by zinenko
[mlir] Split out Python bindings entry point into a separate file

This will allow the bindings to be built as a library and reused in out-of-tree
projects that want to provide bindings on top of MLIR bindings.

Reviewed By: stellaraccident, mikeurbach

Differential Revision: https://reviews.llvm.org/D101075
The file was modifiedmlir/lib/Bindings/Python/CMakeLists.txt
The file was addedmlir/lib/Bindings/Python/IRModule.cpp
The file was modifiedmlir/lib/Bindings/Python/MainModule.cpp
Commit 2e1150d8aad60a8a127c10d9cd48c31334493ebf by serguei.katkov
[Greedy RA] Replace ll to mir test to make more stable to check an error.
The file was removedllvm/test/CodeGen/X86/statepoint-invoke-ra1.ll
The file was addedllvm/test/CodeGen/X86/statepoint-invoke-ra.mir
Commit 42e5f42215c098face7f835f1a5a223409b85f69 by tpopp
[mlir] Support complex numbers in Linalg promotion

FillOp allows complex ops, and filling a properly sized buffer with
a default zero complex number is implemented.

Differential Revision: https://reviews.llvm.org/D99939
The file was modifiedmlir/test/Dialect/Linalg/transform-patterns.mlir
The file was modifiedmlir/test/lib/Transforms/TestLinalgTransforms.cpp
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/Promotion.cpp
The file was modifiedmlir/include/mlir/Dialect/Linalg/IR/LinalgStructuredOps.td
The file was modifiedmlir/include/mlir/Dialect/Linalg/Transforms/Transforms.h
Commit e11420ca2371cb8e53fec90cfc619ddf8249c965 by david.green
[ARM] Ensure CSINC has one use in CSINV combine

Otherwise the CMP glue may be used in multiple nodes, needing to be
emitted multiple times. Currently this either increases instruction
count or fails as it attempt to insert the same node multiple times.
The file was modifiedllvm/test/CodeGen/Thumb2/csel.ll
The file was modifiedllvm/lib/Target/ARM/ARMISelLowering.cpp
Commit b863af5a5e03ec89effa48402bd02a2d16e2be08 by tpopp
[mlir] Add LinalgTransforms dependency on Complex
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/CMakeLists.txt
Commit f6c54a61da0d952cefc4be26f4e78709dae77450 by fraser
[RISCV][NFC] Combine identical RV32 and RV64 test checks
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vreductions-fp-sdnode.ll
Commit 2fa14d47005115341c14f37cb2ab00062a60fe0d by Amara Emerson
Try to fix bots. We shouldn't be setting the entrybuilder's DL to a null one.

This was causing a DILocation verifier error, the old code path didn't try to do
this when building constants via the finishPendingPhis() method.
The file was modifiedllvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
Commit 9569d5ba02697f64dda86591cb202f8a4390f710 by sebastian.neubauer
[AMDGPU] Allow buildSpillLoadStore in empty bb

This allows calling buildSpillLoadStore for an empty basic block, where
MI points at the end of the block instead of to an instruction.

This only happens with downstream CFI changes, so I was not able to
create a testcase that works with upstream LLVM.

Differential Revision: https://reviews.llvm.org/D101356
The file was modifiedllvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
The file was modifiedllvm/lib/Target/AMDGPU/SIFrameLowering.cpp
The file was modifiedllvm/lib/Target/AMDGPU/SIRegisterInfo.h
Commit 0ff41c2ebc9904f881c958f9006bbf2b6bdc5d1e by nathan
Update libstdc++ hack comment

This libstc++ hack isn't ready for removal. Updating the comment to
note what I found. While I have not proven Ville's
__is_throw_swappable patch made this go away, that patch did remove
the use of noexcept(noexcept(swap(....))). I'm not sure when gcc grew
deferred noexcept parsing.

Differential Revision: https://reviews.llvm.org/D101441
The file was modifiedclang/lib/Sema/SemaExceptionSpec.cpp
Commit de94b1855c63f8357bc7ae6668996c4a42d2b5be by l.chelini
[mlir] Fix top-level comments (NFC)
The file was modifiedmlir/lib/Dialect/SCF/SCF.cpp
Commit 545fa37834ef6b5731444728c00e7a18d4f1aeed by zinenko
[mlir] Affine: parallelize affine loops with reductions

Introduce a basic support for parallelizing affine loops with reductions
expressed using iteration arguments. Affine parallelism detector now has a flag
to assume such reductions are parallel. The transformation handles a subset of
parallel reductions that are can be expressed using affine.parallel:
integer/float addition and multiplication. This requires to detect the
reduction operation since affine.parallel only supports a fixed set of
reduction operators.

Reviewed By: chelini, kumasento, bondhugula

Differential Revision: https://reviews.llvm.org/D101171
The file was modifiedmlir/include/mlir/Analysis/Utils.h
The file was modifiedmlir/lib/Dialect/Affine/Utils/Utils.cpp
The file was modifiedmlir/include/mlir/Dialect/Affine/Utils.h
The file was modifiedmlir/test/Dialect/Affine/parallelize.mlir
The file was modifiedmlir/include/mlir/Analysis/AffineAnalysis.h
The file was modifiedmlir/lib/Analysis/AffineAnalysis.cpp
The file was modifiedmlir/include/mlir/Dialect/Affine/Passes.td
The file was modifiedmlir/lib/Dialect/Affine/Transforms/SuperVectorize.cpp
The file was modifiedmlir/lib/Analysis/Utils.cpp
The file was modifiedmlir/lib/Dialect/Affine/Transforms/AffineParallelize.cpp
The file was modifiedmlir/lib/Dialect/Affine/Utils/CMakeLists.txt
Commit 6841e6afba00e78972061d2d9bb631c4ac38ad25 by zinenko
[mlir] support max/min lower/upper bounds in affine.parallel

This enables to express more complex parallel loops in the affine framework,
for example, in cases of tiling by sizes not dividing loop trip counts perfectly
or inner wavefront parallelism, among others. One can't use affine.max/min
and supply values to the nested loop bounds since the results of such
affine.max/min operations aren't valid symbols. Making them valid symbols
isn't an option since they would introduce selection trees into memref
subscript arithmetic as an unintended and undesired consequence. Also
add support for converting such loops to SCF. Drop some API that isn't used in
the core repo from AffineParallelOp since its semantics becomes ambiguous in
presence of max/min bounds. Loop normalization is currently unavailable for
such loops.

Depends On D101171

Reviewed By: bondhugula

Differential Revision: https://reviews.llvm.org/D101172
The file was modifiedmlir/lib/IR/AffineMap.cpp
The file was modifiedmlir/lib/Parser/Parser.cpp
The file was modifiedmlir/lib/Dialect/Affine/Transforms/AffineLoopNormalize.cpp
The file was modifiedmlir/lib/IR/AsmPrinter.cpp
The file was modifiedmlir/lib/Dialect/Affine/IR/AffineOps.cpp
The file was modifiedmlir/include/mlir/IR/OpImplementation.h
The file was modifiedmlir/lib/Conversion/AffineToStandard/AffineToStandard.cpp
The file was modifiedmlir/lib/Dialect/Affine/Utils/Utils.cpp
The file was modifiedmlir/test/Dialect/Affine/parallelize.mlir
The file was modifiedmlir/test/Conversion/AffineToStandard/lower-affine.mlir
The file was modifiedmlir/include/mlir/Dialect/Affine/IR/AffineOps.td
The file was modifiedmlir/lib/Parser/Parser.h
The file was modifiedmlir/include/mlir/IR/AffineMap.h
The file was modifiedmlir/test/Dialect/Affine/invalid.mlir
The file was modifiedmlir/lib/Parser/AffineParser.cpp
The file was modifiedmlir/test/Dialect/Affine/ops.mlir
Commit c8f20ed44888f3a09c077690480d1d978c881b0d by bradley.smith
[AArch64][SVE] Move convert.{from,to}.svbool optimization into InstCombine

As part of this the ptrue coalescing done in SVEIntrinsicOpts has been
modified to not introduce redundant converts, since the convert removal
will no longer run after that optimisation to clean up.

Differential Revision: https://reviews.llvm.org/D101302
The file was modifiedllvm/lib/Target/AArch64/SVEIntrinsicOpts.cpp
The file was addedllvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-opts-reinterpret.ll
The file was removedllvm/test/CodeGen/AArch64/sve-intrinsic-opts-reinterpret.ll
The file was modifiedllvm/test/CodeGen/AArch64/sve-coalesce-ptrue-intrinsics.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
Commit 89085bcc86d4dad5cac1601f3c54b776e53eeaa4 by bradley.smith
[AArch64][SVE] Convert svdup(vec, SV_VL1, elm) to insertelement(vec, elm, 0)

By converting the SVE intrinsic to a normal LLVM insertelement we give
the code generator a better chance to remove transitions between GPRs
and VPRs

Co-authored-by: Paul Walker <paul.walker@arm.com>

Depends on D101302

Differential Revision: https://reviews.llvm.org/D101167
The file was addedllvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-opts-dup.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
Commit 354604a2a7149b5efd52134efa4765cf8c32e386 by bradley.smith
[AArch64][SVE] Use SIMD variant of INSR when scalar is the result of a vector extract

At the intrinsic layer the sve.insr operation takes a scalar. When this
scalar is an integer we are forcing a data transition between GPRs and
ZPRs that is potentially costly.

Often the integer scalar is the result of a vector extract, when
performing a reduction for example. In such cases we should keep all
data within the ZPRs.

Co-authored-by: Paul Walker <paul.walker@arm.com>

Differential Revision: https://reviews.llvm.org/D101169
The file was modifiedllvm/lib/Target/AArch64/SVEInstrFormats.td
The file was addedllvm/test/CodeGen/AArch64/sve-insr.ll