Changes

Summary

  1. [AMDGPU] Invert the handling of skip insertion. (details)
  2. [MachO] Add a test for detecting reserved unit length. (details)
  3. [gn build] Port 0dc6c249bff (details)
  4. [DWARF] Fix DWARFDebugAranges to support 64-bit CU offsets. (details)
  5. [RISCV] Support ABI checking with per function target-features (details)
  6. [llvm-locstats][NFC] Support OOP concept (details)
  7. Revert "[RISCV] Add Clang frontend support for Bitmanip extension" (details)
  8. [yaml2obj/obj2yaml] - Add support for SHT_RELR sections. (details)
  9. [llvm-locstats] Add the --draw-plot option (details)
  10. [AArch64][SVE] Add ptest intrinsics (details)
  11. [Support] Replace Windows __declspec(thread) with thread_local for (details)
  12. Revert "[yaml2obj/obj2yaml] - Add support for SHT_RELR sections." (details)
  13. [Lexer] Allow UCN for dollar symbol '\u0024' in identifiers when using (details)
  14. [llvm-locstats] Fix the docs (details)
  15. [NFC] Adjust test cases numbering, test commit. (details)
  16. [AArch64][SVE] Fold variable into assert to silence unused variable (details)
  17. [lldb] Add expect_expr function for testing expression evaluation in (details)
  18. [yaml2obj/obj2yaml] - Add support for SHT_RELR sections. (details)
  19. Fix "pointer is null" static analyzer warning. NFCI. (details)
  20. RegisterClassInfo::computePSetLimit - assert that we actually find a (details)
  21. Fix Wdocumentation warning. NFC. (details)
  22. Revert "[RISCV] Support ABI checking with per function target-features" (details)
  23. [RISCV] Support ABI checking with per function target-features (details)
  24. Revert rG6078f2fedcac5797ac39ee5ef3fd7a35ef1202d5 - (details)
  25. Bump the trunk major version to 11 (details)
  26. [PowerPC] Legalize saturating vector add/sub (details)
  27. [llvm-locstats] Add the --compare option (details)
  28. Further implement CWG 2292 (details)
  29. [RISCV] Fix test for inline asm z constraint modifier (details)
  30. TableGen/GlobalISel: Don't reconstruct CodeGenRegBank (details)
  31. TableGen/GlobalISel: Don't take reference to temporary values (details)
  32. TableGen: Delete some copy constuctors (details)
  33. GlobalISel: Fix narrowScalar for G_ANYEXT results (details)
  34. AMDGPU: Partially directly select llvm.amdgcn.interp.p1.f16 (details)
  35. GlobalISel: Implement lower for G_BITCAST (details)
Commit 0dc6c249bffac9f23a605ce4e42a84341da3ddbd by cdevadas
[AMDGPU] Invert the handling of skip insertion.
The current implementation of skip insertion (SIInsertSkip) makes it a
mandatory pass required for correctness. Initially, the idea was to have
an optional pass. This patch inserts the s_cbranch_execz upfront during
SILowerControlFlow to skip over the sections of code when no lanes are
active. Later, SIRemoveShortExecBranches removes the skips for short
branches, unless there is a sideeffect and the skip branch is really
necessary.
This new pass will replace the handling of skip insertion in the
existing SIInsertSkip Pass.
Differential revision: https://reviews.llvm.org/D68092
The file was modifiedllvm/test/CodeGen/AMDGPU/subreg-coalescer-undef-use.ll
The file was modifiedllvm/lib/Target/AMDGPU/SIInsertSkips.cpp
The file was addedllvm/lib/Target/AMDGPU/SIRemoveShortExecBranches.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/else.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/uniform-loop-inside-nonuniform.ll
The file was modifiedllvm/lib/Target/AMDGPU/SILowerControlFlow.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/si-lower-control-flow-unreachable-block.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/wave32.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/hoist-cond.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/insert-skips-kill-uncond.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/convergent-inlineasm.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/smrd_vmem_war.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/mul24-pass-ordering.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/skip-branch-taildup-ret.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/divergent-branch-uniform-condition.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/cse-phi-incoming-val.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/control-flow-fastregalloc.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/call-skip.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/skip-branch-trap.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/si-annotate-cf-noloop.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/insert-skips-flat-vmem.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/skip-if-dead.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/stack-pointer-offset-relative-frameindex.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/collapse-endcf.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/valu-i1.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/branch-condition-and.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/uniform-cfg.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPU.h
The file was modifiedllvm/test/CodeGen/AMDGPU/branch-relaxation.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/insert-skips-gws.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/si-lower-control-flow.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/atomic_optimizations_pixelshader.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/wqm.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/ret_jump.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/insert-skips-ignored-insts.mir
The file was modifiedllvm/lib/Target/AMDGPU/CMakeLists.txt
Commit fcc08aa835de1e0c1f3e7e479917575e55433b68 by ikudrin
[MachO] Add a test for detecting reserved unit length.
This is a follow-up for D71546 to add a corresponding unit test.
Differential Revision: https://reviews.llvm.org/D72695
The file was modifiedlld/unittests/MachOTests/MachONormalizedFileToAtomsTests.cpp
Commit 4b1d471fa61f2d390d4dd5f2e95862a3cb5a6ec0 by llvmgnsyncbot
[gn build] Port 0dc6c249bff
The file was modifiedllvm/utils/gn/secondary/llvm/lib/Target/AMDGPU/BUILD.gn
Commit 2142e20f50954b9b5085e9b9461efc318a3348c0 by ikudrin
[DWARF] Fix DWARFDebugAranges to support 64-bit CU offsets.
DWARFContext, the only user of this class, can already handle such
offsets.
Differential Revision: https://reviews.llvm.org/D71834
The file was modifiedllvm/lib/DebugInfo/DWARF/DWARFDebugAranges.cpp
The file was modifiedllvm/include/llvm/DebugInfo/DWARF/DWARFDebugAranges.h
Commit 109e4d12edda07bdec139de36d9fdb6f73399f92 by zakk.chen
[RISCV] Support ABI checking with per function target-features
if users don't specific -mattr, the default target-feature come from IR
attribute.
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.cpp
The file was modifiedllvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
The file was modifiedllvm/lib/Target/RISCV/Utils/RISCVBaseInfo.cpp
The file was modifiedllvm/test/CodeGen/RISCV/subtarget-features-std-ext.ll
Commit a3ebc40644d7e93841d1f8c8994f1f22023960ad by djordje.todorovic
[llvm-locstats][NFC] Support OOP concept
Making these changes, the code becomes more robust and easier for adding
the new features.
  -Introduce the LocationStats class representing the statistics
-Add the pretty_print() method in the LocationStats class
-Add additional '-' for the program options
-Add the verify_program_inputs() function
-Add the parse_locstats() function
-Rename 'results' => 'opts'
-Add more comments
Differential Revision: https://reviews.llvm.org/D71868
The file was modifiedllvm/docs/CommandGuide/llvm-locstats.rst
The file was modifiedllvm/utils/llvm-locstats/llvm-locstats.py
Commit cbe681bd8339d3a018d25441a5f4ef9da2bd017d by scott.egerton
Revert "[RISCV] Add Clang frontend support for Bitmanip extension"
This reverts commit 57cf6ee9c84434161088c39a6f8dd2aae14eb12d.
The file was modifiedclang/test/Preprocessor/riscv-target-features.c
The file was modifiedclang/lib/Basic/Targets/RISCV.h
The file was modifiedclang/lib/Driver/ToolChains/Arch/RISCV.cpp
The file was modifiedclang/lib/Basic/Targets/RISCV.cpp
Commit 46d11e30ee807accefd14e0b7f306647963a39b5 by grimar
[yaml2obj/obj2yaml] - Add support for SHT_RELR sections.
The encoded sequence of Elf*_Relr entries in a SHT_RELR section looks
like [ AAAAAAAA BBBBBBB1 BBBBBBB1 ... AAAAAAAA BBBBBB1 ... ] i.e. start
with an address, followed by any number of bitmaps. The address entry
encodes 1 relocation. The subsequent bitmap entries encode up to 63(31)
relocations each, at subsequent offsets following the last address
entry.
More information is here:
https://github.com/llvm-mirror/llvm/blob/master/lib/Object/ELF.cpp#L272
This patch adds a support for these sections.
Differential revision: https://reviews.llvm.org/D71872
The file was modifiedllvm/include/llvm/ObjectYAML/ELFYAML.h
The file was modifiedllvm/lib/ObjectYAML/ELFYAML.cpp
The file was addedllvm/test/tools/yaml2obj/ELF/relr-section.yaml
The file was modifiedllvm/lib/ObjectYAML/ELFEmitter.cpp
The file was addedllvm/test/tools/obj2yaml/relr-section.yaml
The file was modifiedllvm/tools/obj2yaml/elf2yaml.cpp
Commit ada964661e2b4d86b0753c99265c812029a3d1d2 by djordje.todorovic
[llvm-locstats] Add the --draw-plot option
When using the option, draw the histogram representing the debug
location buckets. The resulting histogram will be saved in a png file.
Differential Revision: https://reviews.llvm.org/D71869
The file was modifiedllvm/utils/llvm-locstats/llvm-locstats.py
The file was modifiedllvm/docs/CommandGuide/llvm-locstats.rst
Commit 93a4dede3a5ecb110dd7cdfd7faa48e3448844d8 by cullen.rhodes
[AArch64][SVE] Add ptest intrinsics
Summary: Implements the following intrinsics:
    * @llvm.aarch64.sve.ptest.any
   * @llvm.aarch64.sve.ptest.first
   * @llvm.aarch64.sve.ptest.last
Reviewers: sdesmalen, efriedma, dancgr, mgudim, cameron.mcinally,
rengolin
Reviewed By: efriedma
Subscribers: tschuett, kristof.beyls, hiraditya, rkruppe, psnobl,
llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D72398
The file was modifiedllvm/include/llvm/IR/IntrinsicsAArch64.td
The file was addedllvm/test/CodeGen/AArch64/sve-setcc.ll
The file was addedllvm/test/CodeGen/AArch64/sve-intrinsics-pred-testing.ll
The file was modifiedllvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.h
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
Commit 884a65af5ceebce76519749ed6eb9a86d0596771 by russell.gallop
[Support] Replace Windows __declspec(thread) with thread_local for
LLVM_THREAD_LOCAL
Windows minimum host tools version is now VS2017, which supports C++11
thread_local so use this for LLVM_THREAD_LOCAL instead of
declspec(thread). According to [1], thread_local is implemented with
declspec(thread) so this should be NFC.
[1] https://docs.microsoft.com/en-us/cpp/cpp/thread?view=vs-2017
Differential Revision: https://reviews.llvm.org/D72399
The file was modifiedllvm/include/llvm/Support/Compiler.h
Commit ca6f616532780b236556fc129cda3243d31cb01a by grimar
Revert "[yaml2obj/obj2yaml] - Add support for SHT_RELR sections."
This reverts commit 46d11e30ee807accefd14e0b7f306647963a39b5.
It broke bots. E.g.
http://lab.llvm.org:8011/builders/llvm-clang-lld-x86_64-scei-ps4-ubuntu-fast/builds/60744
The file was modifiedllvm/lib/ObjectYAML/ELFYAML.cpp
The file was removedllvm/test/tools/obj2yaml/relr-section.yaml
The file was removedllvm/test/tools/yaml2obj/ELF/relr-section.yaml
The file was modifiedllvm/lib/ObjectYAML/ELFEmitter.cpp
The file was modifiedllvm/tools/obj2yaml/elf2yaml.cpp
The file was modifiedllvm/include/llvm/ObjectYAML/ELFYAML.h
Commit a90ea386981f4fa3c7cb7f62c6900069764b05a8 by scott.egerton
[Lexer] Allow UCN for dollar symbol '\u0024' in identifiers when using
-fdollars-in-identifiers flag.
Summary: Previously, the -fdollars-in-identifiers flag allows the '$'
symbol to be used in an identifier but the universal character name
equivalent '\u0024' is not allowed. This patch changes this, so that
\u0024 is valid in identifiers.
Reviewers: rsmith, jordan_rose
Reviewed By: rsmith
Subscribers: dexonsmith, simoncook, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D71758
The file was modifiedclang/test/Preprocessor/ucn-pp-identifier.c
The file was modifiedclang/lib/Lex/Lexer.cpp
Commit ce8795eb6c054328173876fe3fb126fd0b0b8aba by djordje.todorovic
[llvm-locstats] Fix the docs
Add the missing picture for the documentation.
The file was addedllvm/docs/CommandGuide/locstats-draw-plot.png
Commit 019c8d9d1511a07d2004667d2240f3e47cb991ec by arkady.shlykov
[NFC] Adjust test cases numbering, test commit.
Summary: Test case test14 is missing, adjust the numbering to have a
consecutive range. Also a test commit to verify commit access.
The file was modifiedllvm/test/Transforms/LoopUnroll/peel-loop-conditions.ll
Commit 06cfcdcca7de9c88a1e885eff0d0c4c07090ad48 by benny.kra
[AArch64][SVE] Fold variable into assert to silence unused variable
warnings in Release builds
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp
Commit 13f22f5d5958a46db1212a083a426e339204c783 by Raphael Isemann
[lldb] Add expect_expr function for testing expression evaluation in
dotests.
Summary: This patch adds a new function to lldbtest: `expect_expr`. This
function is supposed to replace the current approach of calling
`expect`/`runCmd` with `expr`, `p` etc.
`expect_expr` allows evaluating expressions and matching their
value/summary/type/error message without having to do any string
matching that might allow unintended passes (e.g., `self.expect("expr
3+4", substrs=["7"])` can unexpectedly pass for results like `(Class7)
$0 = 7`, `(int) $7 = 22`, `(int) $0 = 77` and so on).
This only uses the function in a few places to test and demonstrate it.
I'll migrate the tests in follow up commits.
Reviewers: JDevlieghere, shafik, labath
Reviewed By: labath
Subscribers: christof, abidh, lldb-commits
Tags: #lldb
Differential Revision: https://reviews.llvm.org/D70314
The file was modifiedlldb/packages/Python/lldbsuite/test/functionalities/data-formatter/data-formatter-stl/libcxx/string/TestDataFormatterLibcxxString.py
The file was modifiedlldb/packages/Python/lldbsuite/test/lldbtest.py
The file was modifiedlldb/packages/Python/lldbsuite/test/commands/expression/call-function/TestCallBuiltinFunction.py
Commit 7570d387c21935b58afa67cb9ee17250e38721fa by grimar
[yaml2obj/obj2yaml] - Add support for SHT_RELR sections.
Note: this is a reland with a trivial 2 lines fix in
ELFState<ELFT>::writeSectionContent.
     It adds a check similar to ones we already have for other sections
to fix the case revealed
     by bots, like
http://lab.llvm.org:8011/builders/llvm-clang-lld-x86_64-scei-ps4-ubuntu-fast/builds/60744.
The encoded sequence of Elf*_Relr entries in a SHT_RELR section looks
like [ AAAAAAAA BBBBBBB1 BBBBBBB1 ... AAAAAAAA BBBBBB1 ... ] i.e. start
with an address, followed by any number of bitmaps. The address entry
encodes 1 relocation. The subsequent bitmap entries encode up to 63(31)
relocations each, at subsequent offsets following the last address
entry.
More information is here:
https://github.com/llvm-mirror/llvm/blob/master/lib/Object/ELF.cpp#L272
This patch adds a support for these sections.
Differential revision: https://reviews.llvm.org/D71872
The file was modifiedllvm/include/llvm/ObjectYAML/ELFYAML.h
The file was modifiedllvm/lib/ObjectYAML/ELFEmitter.cpp
The file was modifiedllvm/tools/obj2yaml/elf2yaml.cpp
The file was modifiedllvm/lib/ObjectYAML/ELFYAML.cpp
Commit 7b15865225103389150153d12904041fcc57fd0e by llvm-dev
Fix "pointer is null" static analyzer warning. NFCI.
Use cast<> instead of dyn_cast<> since the pointer is always
dereferenced and cast<> will perform the null assertion for us.
The file was modifiedllvm/lib/Target/NVPTX/NVPTXLowerAlloca.cpp
Commit 0b64400e0b3de18c99f77380e98da8e5e1a49832 by llvm-dev
RegisterClassInfo::computePSetLimit - assert that we actually find a
register.
Fixes "pointer is null" clang static analyzer warning.
The file was modifiedllvm/lib/CodeGen/RegisterClassInfo.cpp
Commit eb82226f33525c7332f8008c048b821f08d725fa by llvm-dev
Fix Wdocumentation warning. NFC.
The file was modifiedclang/include/clang/Sema/Sema.h
Commit 3bc2860e926b7e35c381ea41dd90caeb7ae400d2 by zakk.chen
Revert "[RISCV] Support ABI checking with per function target-features"
This reverts commit 109e4d12edda07bdec139de36d9fdb6f73399f92.
The file was modifiedllvm/test/CodeGen/RISCV/subtarget-features-std-ext.ll
The file was modifiedllvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
The file was modifiedllvm/lib/Target/RISCV/Utils/RISCVBaseInfo.cpp
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.cpp
Commit 7bc58a779aaa1de56fad8b1bc8e46932d2f2f1e4 by zakk.chen
[RISCV] Support ABI checking with per function target-features
if users don't specific -mattr, the default target-feature come from IR
attribute.
Reviewers: lenary, asb
Reviewed By: lenary, asb
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D70837
The file was modifiedllvm/lib/Target/RISCV/Utils/RISCVBaseInfo.cpp
The file was modifiedllvm/test/CodeGen/RISCV/subtarget-features-std-ext.ll
The file was modifiedllvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.cpp
Commit e26a78e70857273c83aaacd4aa0edb36effe70e3 by llvm-dev
Revert rG6078f2fedcac5797ac39ee5ef3fd7a35ef1202d5 -
"[AArch64][GlobalISel]: Support @llvm.{return,frame}address selection."
These intrinsics expand to a variable number of instructions so just
like in ISelLowering.cpp we use custom code to deal with them.
Committing Tim's original patch.
Differential Revision: https://reviews.llvm.org/D65656
---- Breaks EXPENSIVE_CHECKS builds.
The file was modifiedllvm/lib/Target/AArch64/AArch64InstructionSelector.cpp
The file was removedllvm/test/CodeGen/AArch64/GlobalISel/select-returnaddr.ll
The file was removedllvm/test/CodeGen/AArch64/GlobalISel/select-frameaddr.ll
Commit 5852475e2c049ce29dcb1f0da3ac33035f8c9156 by hans
Bump the trunk major version to 11
and clear the release notes.
The file was modifiedllvm/utils/lit/lit/__init__.py
The file was modifiedpstl/test/pstl/version.pass.cpp
The file was modifiedlibcxx/include/__config
The file was modifiedlibcxx/include/__libcpp_version
The file was modifiedclang/docs/conf.py
The file was modifiedpolly/docs/ReleaseNotes.rst
The file was modifiedlibcxx/docs/ReleaseNotes.rst
The file was modifiedllvm/utils/gn/secondary/llvm/version.gni
The file was modifiedllvm/docs/ReleaseNotes.rst
The file was modifiedpstl/docs/ReleaseNotes.rst
The file was modifiedllvm/utils/release/build_llvm_package.bat
The file was modifiedclang/docs/ReleaseNotes.rst
The file was modifiedclang-tools-extra/docs/ReleaseNotes.rst
The file was modifiedclang/docs/analyzer/conf.py
The file was modifiedlld/docs/conf.py
The file was modifiedlibunwind/CMakeLists.txt
The file was modifiedlibcxx/docs/conf.py
The file was modifiedclang-tools-extra/docs/conf.py
The file was modifiedlibunwind/docs/conf.py
The file was modifiedpolly/docs/conf.py
The file was modifiedpstl/include/pstl/internal/pstl_config.h
The file was modifiedlibcxx/CMakeLists.txt
The file was modifiedlld/docs/ReleaseNotes.rst
The file was modifiedllvm/CMakeLists.txt
Commit 9c64f04df8ecbcad2c527c33f5ef8a7993842001 by nemanja.i.ibm
[PowerPC] Legalize saturating vector add/sub
These intrinsics and the corresponding ISD nodes were recently added.
PPC has instructions that do this for vectors. Legalize them and add
patterns to emit the satuarting instructions.
Differential revision: https://reviews.llvm.org/D71940
The file was addedllvm/test/CodeGen/PowerPC/saturating-intrinsics.ll
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrAltivec.td
The file was modifiedllvm/lib/Target/PowerPC/PPCISelLowering.cpp
Commit 3b8ef7876ec797a03569184264e7ba4e5e046b68 by djordje.todorovic
[llvm-locstats] Add the --compare option
Draw a plot showing the difference in debug loc coverage on two files
provided.
Differential Revision: https://reviews.llvm.org/D71870
The file was modifiedllvm/utils/llvm-locstats/llvm-locstats.py
The file was addedllvm/docs/CommandGuide/locstats-compare.png
The file was modifiedllvm/docs/CommandGuide/llvm-locstats.rst
Commit ee0f1f1edc3ec0d4e698d50cc3180217448802b7 by aaron
Further implement CWG 2292
The core issue is that simple-template-id is ambiguous between
class-name and type-name. This fixes PR43966.
The file was addedclang/test/SemaCXX/pseudo-destructor-name.cpp
The file was modifiedclang/lib/Sema/SemaExprCXX.cpp
Commit 46e3edcc2c89e34b3ec198387b758a6998f5980b by luismarques
[RISCV] Fix test for inline asm z constraint modifier
Summary: Use an `i` constraint in the test, to correctly trigger the
code for handling the `z` constraint modifier.
Reviewers: asb, lenary, jrtc27 Reviewed By: lenary, jrtc27 Tags: #llvm
Differential Revision: https://reviews.llvm.org/D72134
The file was modifiedllvm/test/CodeGen/RISCV/inline-asm.ll
Commit 3ab7b7f53552a0969bd89db3317eb5a3ddf31d8f by arsenm2
TableGen/GlobalISel: Don't reconstruct CodeGenRegBank
The maps for dealing with the relationships between different register
classes and subregister indexes rely on unique pointers for every
class/index. By constructing a second copy of CodeGenRegBank, two
different pointer values existed for a given subregister depending on
where you were querying.
Use the existing CodeGenRegBank owned by the CodeGenTarget instead of
constructing a second copy. This avoids incorrectly failing map lookups
in a future change.
The file was modifiedllvm/utils/TableGen/GlobalISelEmitter.cpp
Commit eafa8dbefe30c85e58efc5309793f2d7c2109e35 by arsenm2
TableGen/GlobalISel: Don't take reference to temporary values
These return temporary Optional<> values which are immediately
destroyed. I'm not sure why no sanitizers seem to have caught this, but
I encountered crashes on these in a future patch.
The file was modifiedllvm/utils/TableGen/GlobalISelEmitter.cpp
Commit 8931fde869c2787886a5f84c03f70cd32e2e8b1f by arsenm2
TableGen: Delete some copy constuctors
Some register related machinery relies on uniqued, static pointers for
register classes and subregisters, so try to make sure these are never
copied.
The file was modifiedllvm/utils/TableGen/CodeGenRegisters.h
The file was modifiedllvm/utils/TableGen/RISCVCompressInstEmitter.cpp
Commit 91715617ad601c6bd953e1c47ecaaf3610de233f by arsenm2
GlobalISel: Fix narrowScalar for G_ANYEXT results
This is nearly the same as G_ZEXT.
The file was modifiedllvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-anyext.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-unmerge-values.mir
Commit bd7658a212ebc27a8f7d69666820df33bc8d61f5 by arsenm2
AMDGPU: Partially directly select llvm.amdgcn.interp.p1.f16
The 16 bank LDS case is complicated due to using multiple instructions.
If I attempt to write a pattern for it, the generated selector
incorrectly places the copy to m0 after the first instruction, so that
needs to be separately addressed.
Also fix not gluing the copy to m0 to the second operation in the second
half of the 16 bank lowering.
The file was modifiedllvm/lib/Target/AMDGPU/VOP3Instructions.td
The file was modifiedllvm/test/MC/AMDGPU/vop3.s
The file was modifiedllvm/lib/Target/AMDGPU/SIISelLowering.cpp
Commit 936483fb7dd2c8c6b014516ff3b3cd13740e0518 by arsenm2
GlobalISel: Implement lower for G_BITCAST
Bitcast only really applies between scalars and vectors. Implement as an
unmerge and remerge. The test needs to tolerate failure since one of the
unmerges currently fails to legalize.
The file was modifiedllvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bitcast.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp