SuccessChanges

Summary

  1. [libcxx][ranges] Add ranges::empty CPO. (details)
  2. [ORC-RT] Add unit test infrastructure, extensible_rtti implementation, unit test (details)
  3. [gn build] Port e5d483f28a3a (details)
  4. [NFC][LSAN] Fix flaky multithreaded test (details)
  5. Enable export of FIR includes into the install tree (details)
  6. [RISCV] Fix the calculation of the offset of Zvlsseg spilling. (details)
Commit e5d483f28a3af0972fc9b0df6073e4c14bb39359 by zoecarver
[libcxx][ranges] Add ranges::empty CPO.

Depends on D101079. Refs D101189.

Differential Revision: https://reviews.llvm.org/D101193
The file was addedlibcxx/include/__ranges/empty.h
The file was modifiedlibcxx/include/ranges
The file was addedlibcxx/test/std/ranges/range.access/range.prim/empty.pass.cpp
The file was addedlibcxx/test/std/ranges/range.access/range.prim/empty.incomplete.verify.cpp
The file was modifiedlibcxx/include/CMakeLists.txt
Commit 6d263b6f1c97fe6c45c75443e7daf6cd0c1c4222 by Lang Hames
[ORC-RT] Add unit test infrastructure, extensible_rtti implementation, unit test

Add unit test infrastructure for the ORC runtime, plus a cut-down
extensible_rtti system and extensible_rtti unit test.

Removes the placeholder.cpp source file.

Differential Revision: https://reviews.llvm.org/D102080
The file was modifiedcompiler-rt/cmake/config-ix.cmake
The file was modifiedcompiler-rt/lib/orc/CMakeLists.txt
The file was addedcompiler-rt/lib/orc/extensible_rtti.h
The file was addedcompiler-rt/lib/orc/unittests/extensible_rtti_test.cpp
The file was addedcompiler-rt/lib/orc/extensible_rtti.cpp
The file was addedcompiler-rt/lib/orc/unittests/orc_unit_test_main.cpp
The file was addedcompiler-rt/lib/orc/unittests/CMakeLists.txt
The file was removedcompiler-rt/lib/orc/placeholder.cpp
Commit 842b1624460b2904ec5439d8b0d8b50ae5d35a7a by llvmgnsyncbot
[gn build] Port e5d483f28a3a
The file was modifiedllvm/utils/gn/secondary/libcxx/include/BUILD.gn
Commit c057779d389c5c1740a8051aa2929f7bc0f8ee00 by Vitaly Buka
[NFC][LSAN] Fix flaky multithreaded test
The file was modifiedcompiler-rt/test/lsan/TestCases/many_threads_detach.cpp
Commit 1e11616a071d07d0f3cdae1140b5c8685eb564a2 by rkauffmann
Enable export of FIR includes into the install tree
https://reviews.llvm.org/D102040
The file was modifiedflang/CMakeLists.txt
Commit d8ec2b183e9243366e3a0cd1116dbe879856b333 by kai.wang
[RISCV] Fix the calculation of the offset of Zvlsseg spilling.

For Zvlsseg spilling, we need to convert the pseudo instructions
into multiple vector load/store instructions with appropriate offsets.
For example, for PseudoVSPILL3_M2, we need to convert it to

VS2R %v2, %base
ADDI %base, %base, (vlenb x 2)
VS2R %v4, %base
ADDI %base, %base, (vlenb x 2)
VS2R %v6, %base

We need to keep the size of the offset in the pseudo spilling instructions.
In this case, it is (vlenb x 2).

In the original implementation, we use the size of frame objects divide the
number of vectors in zvlsseg types. The size of frame objects is not
necessary exactly the same as the spilling data. It may be larger than
it. So, we change it to (VLENB x LMUL) in this patch. The calculation is
more direct and easy to understand.

Differential Revision: https://reviews.llvm.org/D101869
The file was addedllvm/test/CodeGen/RISCV/rvv/zvlsseg-spill.mir
The file was modifiedllvm/lib/Target/RISCV/RISCVRegisterInfo.cpp