Started 1 mo 0 days ago
Took 8 hr 8 min

Build #4458 (Sep 21, 2021 5:57:34 AM)

Changes
  1. [DebugInfo] Add test for dumping DW_AT_defaulted (details / githubweb)
  2. [RISCV] Add test cases for missed opportunities to use vand/vor/vxor.vx. NFC (details / githubweb)
  3. [NFC] [hwasan] Separate outline and inline instrumentation. (details / githubweb)
  4. [Polly] Partially fix scoped alias metadata (details / githubweb)
  5. [OpenMP][NVPTX] Fix a warning that data argument not used by format string (details / githubweb)
  6. Sema: relax va_start checking further for Windows AArch64 (details / githubweb)
  7. [GlobalISel] Implement support for the "trap-func-name" attribute. (details / githubweb)
  8. [AMDGPU][NFC] Correct typos in lib/Target/AMDGPU/AMDGPU*.cpp files. Test commit for new contributor. (details / githubweb)
  9. [mlir][tosa] Remove the documentation requirement for elements of several binary elementwise ops to be of the same rank. (details / githubweb)
  10. [clang] Fix a few comment typos to cycle bots (details / githubweb)
  11. [mlir][tosa] Add several binary elementwise to the list of broadcastable ops. (details / githubweb)
  12. [X86] Rename the X86WinAllocaExpander pass and related symbols to "DynAlloca". NFC. (details / githubweb)
  13. Update MLIR generate-test-checks.py to add the notice from the source into the generated file (details / githubweb)
  14. [mlir-tblgen] Add DagNode StaticMatcher. (details / githubweb)
  15. [clang] Fix a few comment more typos to cycle bots (details / githubweb)
  16. [clang] Fix a few more comment typos to cycle bots (details / githubweb)
  17. [InstCombine] Eliminate vector reverse if all inputs/outputs to an instruction are reverses (details / githubweb)
  18. [mlir][python] Forward _OperationBase _CAPIPtr to the Operation. (details / githubweb)
  19. [mlir] Tighten verification of SparseElementsAttr (details / githubweb)
  20. [mlir] Add value_begin/value_end methods to DenseElementsAttr (details / githubweb)
  21. [mlir] Refactor ElementsAttr into an AttrInterface (details / githubweb)
  22. [llvm] Use make_early_inc_range (NFC) (details / githubweb)
  23. [NFC] Rename Context->CtxI in SCEV for uniformity reasons (details / githubweb)
  24. [Polly] Don't generate inter-iteration noalias metadata. (details / githubweb)
  25. [SimplifyCFG] Redirect switch cases that lead to UB into an unreachable block (details / githubweb)
  26. [OpAsmParser] Add a parseCommaSeparatedList helper and beef up Delimeter. (details / githubweb)
  27. BPF: make 32bit register spill with 64bit alignment (details / githubweb)

Started by upstream project clang-stage2-Rthinlto_relay build number 6300
originally caused by:

This run spent:

  • 7 hr 59 min waiting;
  • 8 hr 8 min build duration;
  • 16 hr total from scheduled to completion.
Revision: 6e86f181714783f160991f7b8bea89a1c57c7a52
Repository: https://github.com/llvm/llvm-zorg.git
  • refs/remotes/origin/main
Revision: ea72b0319d7b0f0c2fcf41d121afa5d031b319d5
Repository: https://github.com/llvm/llvm-project.git
  • detached
Test Result (no failures)