Changes

Summary

  1. [DebugInfo] Add test for dumping DW_AT_defaulted (details)
  2. [RISCV] Add test cases for missed opportunities to use vand/vor/vxor.vx. NFC (details)
  3. [NFC] [hwasan] Separate outline and inline instrumentation. (details)
  4. [Polly] Partially fix scoped alias metadata (details)
  5. [OpenMP][NVPTX] Fix a warning that data argument not used by format string (details)
  6. Sema: relax va_start checking further for Windows AArch64 (details)
  7. [GlobalISel] Implement support for the "trap-func-name" attribute. (details)
  8. [AMDGPU][NFC] Correct typos in lib/Target/AMDGPU/AMDGPU*.cpp files. Test commit for new contributor. (details)
  9. [mlir][tosa] Remove the documentation requirement for elements of several binary elementwise ops to be of the same rank. (details)
  10. [clang] Fix a few comment typos to cycle bots (details)
  11. [mlir][tosa] Add several binary elementwise to the list of broadcastable ops. (details)
  12. [X86] Rename the X86WinAllocaExpander pass and related symbols to "DynAlloca". NFC. (details)
  13. Update MLIR generate-test-checks.py to add the notice from the source into the generated file (details)
  14. [mlir-tblgen] Add DagNode StaticMatcher. (details)
  15. [clang] Fix a few comment more typos to cycle bots (details)
  16. [clang] Fix a few more comment typos to cycle bots (details)
  17. [InstCombine] Eliminate vector reverse if all inputs/outputs to an instruction are reverses (details)
  18. [mlir][python] Forward _OperationBase _CAPIPtr to the Operation. (details)
  19. [mlir] Tighten verification of SparseElementsAttr (details)
  20. [mlir] Add value_begin/value_end methods to DenseElementsAttr (details)
  21. [mlir] Refactor ElementsAttr into an AttrInterface (details)
  22. [llvm] Use make_early_inc_range (NFC) (details)
  23. [NFC] Rename Context->CtxI in SCEV for uniformity reasons (details)
  24. [Polly] Don't generate inter-iteration noalias metadata. (details)
  25. [SimplifyCFG] Redirect switch cases that lead to UB into an unreachable block (details)
  26. [OpAsmParser] Add a parseCommaSeparatedList helper and beef up Delimeter. (details)
  27. BPF: make 32bit register spill with 64bit alignment (details)
Commit fa822a2ee52f8243d29eb035d7002a9ab40788a0 by paul.robinson
[DebugInfo] Add test for dumping DW_AT_defaulted
The file was addedllvm/test/tools/llvm-dwarfdump/X86/DW_AT_defaulted.s
Commit c6e52b1e85c6d633bda0e268fed16487fea084d1 by craig.topper
[RISCV] Add test cases for missed opportunities to use vand/vor/vxor.vx. NFC

These are cases were the splat is in another basic block. CGP
needs to sink it to expose the opportunity to SelectionDAG.
The file was modifiedllvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll (diff)
Commit 16b5f4502c5b58c7f70afa8e1e1e33d170ba6089 by fmayer
[NFC] [hwasan] Separate outline and inline instrumentation.

Reviewed By: eugenis

Differential Revision: https://reviews.llvm.org/D110067
The file was modifiedllvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp (diff)
Commit 53720f74e4e32fe11a1688282f7d09dc1828b83a by nikita.ppv
[Polly] Partially fix scoped alias metadata

This partially addresses the verifier failures caused by D110026.
In particular, it does not fix the "second level" alias metadata.
The file was modifiedpolly/test/Isl/CodeGen/invariant_load_alias_metadata.ll (diff)
The file was modifiedpolly/test/Isl/CodeGen/MemAccess/codegen_address_space.ll (diff)
The file was modifiedpolly/test/Isl/CodeGen/simple_vec_assign_scalar.ll (diff)
The file was modifiedpolly/test/ScopInfo/int2ptr_ptr2int.ll (diff)
The file was modifiedpolly/test/Isl/CodeGen/non-affine-phi-node-expansion-2.ll (diff)
The file was modifiedpolly/test/ScopInfo/int2ptr_ptr2int_2.ll (diff)
The file was modifiedpolly/test/Isl/CodeGen/MemAccess/create_arrays.ll (diff)
The file was modifiedpolly/test/Isl/CodeGen/MemAccess/different_types.ll (diff)
The file was modifiedpolly/lib/CodeGen/IRBuilder.cpp (diff)
The file was modifiedpolly/test/Isl/CodeGen/phi_loop_carried_float_escape.ll (diff)
The file was modifiedpolly/test/Isl/CodeGen/scev-backedgetaken.ll (diff)
The file was modifiedpolly/test/Isl/CodeGen/getNumberOfIterations.ll (diff)
The file was modifiedpolly/test/Isl/CodeGen/MemAccess/generate-all.ll (diff)
The file was modifiedpolly/test/Isl/CodeGen/OpenMP/alias-metadata.ll (diff)
The file was modifiedpolly/test/Isl/CodeGen/invariant_loads_ignore_parameter_bounds.ll (diff)
The file was modifiedpolly/test/Isl/CodeGen/stmt_split_no_dependence.ll (diff)
The file was modifiedpolly/test/ScheduleOptimizer/pattern-matching-based-opts_10.ll (diff)
The file was modifiedpolly/test/Isl/CodeGen/partial_write_impossible_restriction.ll (diff)
The file was modifiedpolly/test/Isl/CodeGen/phi_loop_carried_float.ll (diff)
The file was modifiedpolly/test/Isl/CodeGen/non_affine_float_compare.ll (diff)
The file was modifiedpolly/test/Isl/CodeGen/partial_write_array.ll (diff)
The file was modifiedpolly/test/CodeGen/stride_detection.ll (diff)
The file was modifiedpolly/test/Isl/CodeGen/annotated_alias_scopes.ll (diff)
The file was modifiedpolly/test/Isl/CodeGen/OpenMP/new_multidim_access.ll (diff)
The file was modifiedpolly/test/Isl/CodeGen/partial_write_full_write_that_appears_partial.ll (diff)
Commit 49e976c9343253956a7de93f1d982537f9c240ab by tianshilei1992
[OpenMP][NVPTX] Fix a warning that data argument not used by format string

Reviewed By: jhuber6, grokos

Differential Revision: https://reviews.llvm.org/D110104
The file was modifiedopenmp/libomptarget/plugins/cuda/src/rtl.cpp (diff)
Commit 96d3319d6f024b17ac725d9595548acc4787003c by Saleem Abdulrasool
Sema: relax va_start checking further for Windows AArch64

When building in C mode, the VC runtime assumes that it can use pointer
aliasing through `char *` for the parameter to `__va_start`.  Relax the
checks further.  In theory we could keep the tests strict for non-system
header code, but this takes the less strict approach as the additional
check doesn't particularly end up being too much more helpful for
correctness.  The C++ type system is a bit stricter and requires the
explicit cast which we continue to verify.
The file was addedclang/test/Sema/microsoft-varargs.c
The file was modifiedclang/lib/Sema/SemaChecking.cpp (diff)
Commit f9d69a0ab02567933302602238264a38468f9900 by Amara Emerson
[GlobalISel] Implement support for the "trap-func-name" attribute.

This attribute calls a function instead of emitting a trap instruction.

Differential Revision: https://reviews.llvm.org/D110098
The file was modifiedllvm/lib/CodeGen/GlobalISel/IRTranslator.cpp (diff)
The file was modifiedllvm/test/CodeGen/AArch64/debugtrap.ll (diff)
The file was modifiedllvm/test/CodeGen/AArch64/ubsantrap.ll (diff)
The file was modifiedllvm/test/CodeGen/AArch64/arm64-trap.ll (diff)
Commit dc6e8dfdfe7efecfda318d43a06fae18b40eb498 by jacob.lambert
[AMDGPU][NFC] Correct typos in lib/Target/AMDGPU/AMDGPU*.cpp files. Test commit for new contributor.
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp (diff)
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULibCalls.cpp (diff)
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULibFunc.cpp (diff)
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp (diff)
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp (diff)
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUAtomicOptimizer.cpp (diff)
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUPrintfRuntimeBinding.cpp (diff)
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp (diff)
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUAnnotateKernelFeatures.cpp (diff)
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp (diff)
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUReplaceLDSUseWithPointer.cpp (diff)
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUAliasAnalysis.cpp (diff)
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUAlwaysInlinePass.cpp (diff)
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp (diff)
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULowerModuleLDSPass.cpp (diff)
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUPropagateAttributes.cpp (diff)
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp (diff)
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp (diff)
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp (diff)
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp (diff)
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPURewriteOutArguments.cpp (diff)
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp (diff)
Commit 4edf46f72a8f3bd9d60628d0c852e8ff91921673 by rob.suderman
[mlir][tosa] Remove the documentation requirement for elements of several binary elementwise ops to be of the same rank.

Reviewed By: rsuderman

Differential Revision: https://reviews.llvm.org/D110095
The file was modifiedmlir/include/mlir/Dialect/Tosa/IR/TosaOps.td (diff)
Commit f11917057923bce7f9c04282b4a3b15ef0aad0d6 by thakis
[clang] Fix a few comment typos to cycle bots
The file was modifiedclang/lib/Format/TokenAnnotator.cpp (diff)
The file was modifiedclang/lib/Format/Format.cpp (diff)
The file was modifiedclang/lib/Format/WhitespaceManager.h (diff)
The file was modifiedclang/lib/Format/ContinuationIndenter.cpp (diff)
The file was modifiedclang/lib/Format/UnwrappedLineFormatter.cpp (diff)
The file was modifiedclang/lib/Format/MacroExpander.cpp (diff)
Commit 38ff7e11c04e760570e3cb517f8b78d554c65386 by rob.suderman
[mlir][tosa] Add several binary elementwise to the list of broadcastable ops.

Reviewed By: rsuderman

Differential Revision: https://reviews.llvm.org/D110096
The file was modifiedmlir/lib/Dialect/Tosa/Transforms/TosaMakeBroadcastable.cpp (diff)
Commit 4ceea7740990f5b755a7bb911e92254dd5680921 by Amara Emerson
[X86] Rename the X86WinAllocaExpander pass and related symbols to "DynAlloca". NFC.

For x86 Darwin, we have a stack checking feature which re-uses some of this
machinery around stack probing on Windows. Renaming this to be more appropriate
for a generic feature.

Differential Revision: https://reviews.llvm.org/D109993
The file was modifiedllvm/lib/Target/X86/X86InstrInfo.td (diff)
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp (diff)
The file was removedllvm/lib/Target/X86/X86WinAllocaExpander.cpp
The file was addedllvm/lib/Target/X86/X86DynAllocaExpander.cpp
The file was modifiedllvm/lib/Target/X86/X86InstrCompiler.td (diff)
The file was modifiedllvm/utils/gn/secondary/llvm/lib/Target/X86/BUILD.gn (diff)
The file was modifiedllvm/test/CodeGen/X86/O0-pipeline.ll (diff)
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.h (diff)
The file was modifiedllvm/lib/Target/X86/X86TargetMachine.cpp (diff)
The file was modifiedllvm/test/CodeGen/X86/opt-pipeline.ll (diff)
The file was modifiedllvm/lib/Target/X86/X86MachineFunctionInfo.h (diff)
The file was modifiedllvm/lib/Target/X86/CMakeLists.txt (diff)
The file was modifiedllvm/lib/Target/X86/X86.h (diff)
Commit 4e7c0a37c9c92baa655d244f5bfde91d52b138d0 by joker.eph
Update MLIR generate-test-checks.py to add the notice from the source into the generated file

Folks may not read the source of the tool and miss these instructions.

Differential Revision: https://reviews.llvm.org/D110082
The file was modifiedmlir/utils/generate-test-checks.py (diff)
Commit bb2506061b06e9786b5eb9c458f52f9ba7e52a73 by chiahungduan
[mlir-tblgen] Add DagNode StaticMatcher.

Some patterns may share the common DAG structures. Generate a static
function to do the match logic to reduce the binary size.

Reviewed By: jpienaar

Differential Revision: https://reviews.llvm.org/D105797
The file was modifiedmlir/tools/mlir-tblgen/RewriterGen.cpp (diff)
The file was modifiedmlir/lib/TableGen/Pattern.cpp (diff)
The file was addedmlir/test/mlir-tblgen/rewriter-static-matcher.td
The file was modifiedmlir/include/mlir/TableGen/Pattern.h (diff)
Commit bde305baf631004b8d00081f11e62b33e1665e45 by thakis
[clang] Fix a few comment more typos to cycle bots
The file was modifiedclang/lib/Sema/SemaLookup.cpp (diff)
The file was modifiedclang/lib/Sema/SemaTemplateInstantiateDecl.cpp (diff)
The file was modifiedclang/lib/Sema/SemaDeclCXX.cpp (diff)
The file was modifiedclang/lib/Sema/SemaConcept.cpp (diff)
The file was modifiedclang/lib/Sema/SemaOpenMP.cpp (diff)
The file was modifiedclang/lib/Sema/TreeTransform.h (diff)
The file was modifiedclang/lib/Sema/SemaCodeComplete.cpp (diff)
The file was modifiedclang/lib/Sema/SemaCXXScopeSpec.cpp (diff)
The file was modifiedclang/lib/Sema/SemaDeclAttr.cpp (diff)
The file was modifiedclang/lib/Sema/SemaTemplate.cpp (diff)
The file was modifiedclang/lib/Sema/SemaType.cpp (diff)
The file was modifiedclang/lib/Sema/SemaDeclObjC.cpp (diff)
The file was modifiedclang/lib/Sema/SemaChecking.cpp (diff)
The file was modifiedclang/lib/Sema/SemaTemplateDeduction.cpp (diff)
The file was modifiedclang/lib/Sema/SemaStmt.cpp (diff)
The file was modifiedclang/lib/Sema/SemaInit.cpp (diff)
Commit 60ab6861ed13e4f1e2729f8add6366a7be223d80 by thakis
[clang] Fix a few more comment typos to cycle bots
The file was modifiedclang/lib/AST/CommentBriefParser.cpp (diff)
The file was modifiedclang/lib/AST/Interp/Program.cpp (diff)
The file was modifiedclang/lib/AST/ASTContext.cpp (diff)
The file was modifiedclang/lib/AST/ComparisonCategories.cpp (diff)
The file was modifiedclang/lib/AST/RecordLayoutBuilder.cpp (diff)
The file was modifiedclang/lib/AST/Interp/InterpStack.h (diff)
The file was modifiedclang/lib/AST/Interp/Opcodes.td (diff)
The file was modifiedclang/lib/AST/ExprConstant.cpp (diff)
The file was modifiedclang/lib/AST/DeclCXX.cpp (diff)
The file was modifiedclang/lib/AST/DeclTemplate.cpp (diff)
The file was modifiedclang/lib/AST/Interp/Descriptor.h (diff)
The file was modifiedclang/lib/AST/MicrosoftMangle.cpp (diff)
The file was modifiedclang/lib/AST/ASTImporter.cpp (diff)
The file was modifiedclang/lib/AST/Interp/Function.h (diff)
The file was modifiedclang/lib/AST/Interp/InterpState.h (diff)
Commit f417d9d821118ef330b263c4c7ad9d3cda30f406 by mnadeem
[InstCombine] Eliminate vector reverse if all inputs/outputs to an instruction are reverses

Differential Revision: https://reviews.llvm.org/D109808

Change-Id: I1a10d2bc33acbe0ea353c6cb3d077851391fe73e
The file was modifiedllvm/test/Transforms/LoopVectorize/AArch64/sve-vector-reverse-mask4.ll (diff)
The file was addedllvm/test/Transforms/InstCombine/vector-reverse.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/AArch64/sve-vector-reverse.ll (diff)
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineCalls.cpp (diff)
Commit 1fb2e842a93ac862849f5081eb6fdf6f1447ef2a by stellaraccident
[mlir][python] Forward _OperationBase _CAPIPtr to the Operation.

* ODS generated operations extend _OperationBase and without this, cannot be marshalled to CAPI functions.
* No test case updates: this kind of interop is quite hard to verify with in-tree tests.

Differential Revision: https://reviews.llvm.org/D110030
The file was modifiedmlir/lib/Bindings/Python/IRCore.cpp (diff)
Commit 4f21152af12b21ea8f04b322a29dc6ad9e79ef16 by riddleriver
[mlir] Tighten verification of SparseElementsAttr

SparseElementsAttr currently does not perform any verfication on construction, with the only verification existing within the parser. This revision moves the parser verification to SparseElementsAttr, and also adds additional verification for when a sparse index is not valid.

Differential Revision: https://reviews.llvm.org/D109189
The file was modifiedmlir/test/IR/parser.mlir (diff)
The file was modifiedmlir/test/CAPI/ir.c (diff)
The file was modifiedmlir/test/Dialect/Quant/convert-const.mlir (diff)
The file was modifiedmlir/test/Target/LLVMIR/llvmir.mlir (diff)
The file was modifiedmlir/lib/Parser/AttributeParser.cpp (diff)
The file was modifiedmlir/test/IR/invalid.mlir (diff)
The file was modifiedmlir/lib/Parser/TypeParser.cpp (diff)
The file was modifiedmlir/include/mlir/IR/BuiltinAttributes.td (diff)
The file was modifiedmlir/test/IR/pretty-attributes.mlir (diff)
The file was modifiedmlir/lib/IR/BuiltinAttributes.cpp (diff)
The file was modifiedmlir/test/Dialect/Tensor/canonicalize.mlir (diff)
The file was modifiedmlir/include/mlir/IR/BuiltinAttributes.h (diff)
The file was modifiedmlir/lib/Parser/Parser.h (diff)
Commit 0cb5d7fc7fd3eeb40b6ecf9b34a497d46bcba6c6 by riddleriver
[mlir] Add value_begin/value_end methods to DenseElementsAttr

Currently DenseElementsAttr only exposes the ability to get the full range of values for a given type T, but there are many situations where we just want the beginning/end iterator. This revision adds proper value_begin/value_end methods for all of the supported T types, and also cleans up a bit of the interface.

Differential Revision: https://reviews.llvm.org/D104173
The file was modifiedmlir/tools/mlir-tblgen/OpDefinitionsGen.cpp (diff)
The file was modifiedmlir/include/mlir/IR/BuiltinAttributes.h (diff)
The file was modifiedmlir/examples/toy/Ch5/mlir/LowerToAffineLoops.cpp (diff)
The file was modifiedmlir/unittests/TableGen/StructsGenTest.cpp (diff)
The file was modifiedmlir/lib/IR/BuiltinAttributes.cpp (diff)
The file was modifiedmlir/lib/IR/AsmPrinter.cpp (diff)
The file was modifiedmlir/examples/toy/Ch6/mlir/LowerToAffineLoops.cpp (diff)
The file was modifiedmlir/lib/CAPI/IR/BuiltinAttributes.cpp (diff)
The file was modifiedmlir/lib/Dialect/GPU/IR/GPUDialect.cpp (diff)
The file was modifiedmlir/include/mlir/Dialect/CommonFolders.h (diff)
The file was modifiedmlir/include/mlir/IR/BuiltinAttributes.td (diff)
The file was modifiedmlir/lib/Conversion/StandardToSPIRV/StandardToSPIRV.cpp (diff)
The file was modifiedmlir/lib/IR/Operation.cpp (diff)
The file was modifiedmlir/lib/Interfaces/InferTypeOpInterface.cpp (diff)
The file was modifiedmlir/lib/Target/LLVMIR/ConvertFromLLVMIR.cpp (diff)
The file was modifiedmlir/examples/toy/Ch7/mlir/LowerToAffineLoops.cpp (diff)
The file was modifiedmlir/lib/Conversion/LinalgToSPIRV/LinalgToSPIRV.cpp (diff)
The file was modifiedmlir/lib/Conversion/TosaToLinalg/TosaToLinalg.cpp (diff)
Commit d80d3a358fffce430c94c7e9c716a5641010e4d0 by riddleriver
[mlir] Refactor ElementsAttr into an AttrInterface

This revision refactors ElementsAttr into an Attribute Interface.
This enables a common interface with which to interact with
element attributes, without needing to modify the builtin
dialect. It also removes a majority (if not all?) of the need for
the current OpaqueElementsAttr, which was originally intended as
a way to opaquely represent data that was not representable by
the other builtin constructs.

The new ElementsAttr interface not only allows for users to
natively represent their data in the way that best suits them,
it also allows for efficient opaque access and iteration of the
underlying data. Attributes using the ElementsAttr interface
can directly expose support for interacting with the held
elements using any C++ data type they claim to support. For
example, DenseIntOrFpElementsAttr supports iteration using
various native C++ integer/float data types, as well as
APInt/APFloat, and more. ElementsAttr instances that refer to
DenseIntOrFpElementsAttr can use all of these data types for
iteration:

```c++
DenseIntOrFpElementsAttr intElementsAttr = ...;

ElementsAttr attr = intElementsAttr;
for (uint64_t value : attr.getValues<uint64_t>())
  ...;
for (APInt value : attr.getValues<APInt>())
  ...;
for (IntegerAttr value : attr.getValues<IntegerAttr>())
  ...;
```

ElementsAttr also supports failable range/iterator access,
allowing for selective code paths depending on data type
support:

```c++
ElementsAttr attr = ...;
if (auto range = attr.tryGetValues<uint64_t>()) {
  for (uint64_t value : *range)
    ...;
}
```

Differential Revision: https://reviews.llvm.org/D109190
The file was modifiedmlir/include/mlir/Support/InterfaceSupport.h (diff)
The file was modifiedutils/bazel/llvm-project-overlay/mlir/BUILD.bazel (diff)
The file was modifiedmlir/include/mlir/IR/BuiltinAttributes.h (diff)
The file was modifiedmlir/test/lib/Dialect/Test/TestAttributes.cpp (diff)
The file was modifiedmlir/test/lib/IR/CMakeLists.txt (diff)
The file was modifiedmlir/include/mlir/IR/CMakeLists.txt (diff)
The file was addedmlir/test/IR/elements-attr-interface.mlir
The file was addedmlir/lib/IR/BuiltinAttributeInterfaces.cpp
The file was modifiedmlir/include/mlir/IR/BuiltinAttributes.td (diff)
The file was modifiedmlir/test/lib/Dialect/Test/TestAttrDefs.td (diff)
The file was modifiedmlir/tools/mlir-opt/mlir-opt.cpp (diff)
The file was modifiedmlir/lib/IR/BuiltinAttributes.cpp (diff)
The file was modifiedmlir/lib/IR/CMakeLists.txt (diff)
The file was modifiedutils/bazel/llvm-project-overlay/mlir/test/BUILD.bazel (diff)
The file was modifiedllvm/include/llvm/ADT/STLExtras.h (diff)
The file was addedmlir/test/lib/IR/TestBuiltinAttributeInterfaces.cpp
The file was addedmlir/include/mlir/IR/BuiltinAttributeInterfaces.td
The file was addedmlir/include/mlir/IR/BuiltinAttributeInterfaces.h
Commit 85b4b21c8bbad346d58a30154d2767c39cf3285a by kazu
[llvm] Use make_early_inc_range (NFC)
The file was modifiedllvm/lib/Target/NVPTX/NVPTXGenericToNVVM.cpp (diff)
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyLowerBrUnless.cpp (diff)
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyMemIntrinsicResults.cpp (diff)
The file was modifiedllvm/lib/AsmParser/LLParser.cpp (diff)
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyExplicitLocals.cpp (diff)
The file was modifiedllvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp (diff)
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyOptimizeLiveIntervals.cpp (diff)
The file was modifiedllvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp (diff)
The file was modifiedllvm/lib/Target/X86/X86AvoidStoreForwardingBlocks.cpp (diff)
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyPrepareForLiveIntervals.cpp (diff)
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyReplacePhysRegs.cpp (diff)
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp (diff)
The file was modifiedllvm/lib/Target/ARM/ARMISelDAGToDAG.cpp (diff)
The file was modifiedllvm/lib/Target/X86/X86OptimizeLEAs.cpp (diff)
Commit a06db78fd99014993b62b99c305c7b374c1579fc by mkazantsev
[NFC] Rename Context->CtxI in SCEV for uniformity reasons
The file was modifiedllvm/include/llvm/Analysis/ScalarEvolution.h (diff)
The file was modifiedllvm/lib/Analysis/ScalarEvolution.cpp (diff)
Commit cad9f98a2ad98fecf663e9ce39502b8e43676fc9 by llvm-project
[Polly] Don't generate inter-iteration noalias metadata.

This metadata was intended to mark all accesses within an iteration to be pairwise non-aliasing, in this case because every memory of a base pointer is touched (read or write) at most once. This is typical for 'sweeps' over all data. The stated motivation from D30606 is to ensure that unrolled iterations are considered non-aliasing.

Rhe implemention had multiple issues:

* The structure of the noalias metadata was malformed. D110026 added check in the verifier for this metadata, and the tests were failing since then.

* This is not true for the outer loops of the BLIS matrix multiplication, where it was being inserted. Each element of A, B, C is accessed multiple times, as often as the loop not used as an index is iterating.

* Scopes were added to SecondLevelOtherAliasScopeList (used for the !noalias scop list) on-the-fly when another SCEV was seen. This meant that previously visited instructions would not be updated with alias scopes that are only seen later, missing out those SCEVs they should not be aliasing with.

* Since the !noalias scope list would ideally consists of all other SCEV for this base pointer, we might run quickly into scalability issues. Especially after unrolling there would probably at least once SCEV per instruction and unroll instance.

* The inter-iteration noalias base pointer was not removed after leaving the loop marked with it, effectively marking everything after it to noalias as well.

A solution I considered was to mark each instruction as non-aliasing with its own scope. The instruction itself would obviously alias itself, but such construction might also be considered invalid. Duplicating the instruction (e.g. due to speculation) would mark the instruction non-aliasing with its clone. I don't want to go into this territory, especially since the original motivation of determining unrolled instances as noalias based on SCEV is the what scev-aa does as well.

This effectively reverts D30606 and D35761.
The file was modifiedpolly/test/ScheduleOptimizer/pattern-matching-based-opts_13.ll (diff)
The file was modifiedpolly/test/ScheduleOptimizer/pattern-matching-based-opts_5.ll (diff)
The file was modifiedpolly/lib/CodeGen/IslNodeBuilder.cpp (diff)
The file was modifiedpolly/test/ScheduleOptimizer/ensure-correct-tile-sizes.ll (diff)
The file was modifiedpolly/lib/CodeGen/IRBuilder.cpp (diff)
The file was modifiedpolly/test/ScheduleOptimizer/pattern-matching-based-opts_3.ll (diff)
The file was modifiedpolly/lib/Transform/MatmulOptimizer.cpp (diff)
The file was removedpolly/test/ScheduleOptimizer/pattern-matching-based-opts_10.ll
The file was modifiedpolly/test/ScheduleOptimizer/pattern-matching-based-opts_14.ll (diff)
The file was modifiedpolly/include/polly/CodeGen/IRBuilder.h (diff)
The file was modifiedpolly/test/ScheduleOptimizer/mat_mul_pattern_data_layout_2.ll (diff)
Commit 073b254cffeffdef36ffbee0c9afdc0da9cd6ac3 by mkazantsev
[SimplifyCFG] Redirect switch cases that lead to UB into an unreachable block

When following a case of a switch instruction is guaranteed to lead to
UB, we can safely break these edges and redirect those cases into a newly
created unreachable block. As result, CFG will become simpler and we can
remove some of Phi inputs to make further analyzes easier.

Patch by Dmitry Bakunevich!

Differential Revision: https://reviews.llvm.org/D109428
Reviewed By: lebedev.ri
The file was modifiedllvm/test/CodeGen/AArch64/arm64-ccmp.ll (diff)
The file was modifiedllvm/test/Transforms/SimplifyCFG/switch_ub.ll (diff)
The file was modifiedllvm/lib/Transforms/Utils/SimplifyCFG.cpp (diff)
Commit 58abc8c34bde7021bbfa0a7bdfd2af9524cba263 by clattner
[OpAsmParser] Add a parseCommaSeparatedList helper and beef up Delimeter.

Lots of custom ops have hand-rolled comma-delimited parsing loops, as does
the MLIR parser itself.  Provides a standard interface for doing this that
is less error prone and less boilerplate.

While here, extend Delimiter to support <> and {} delimited sequences as
well (I have a use for <> in CIRCT specifically).

Differential Revision: https://reviews.llvm.org/D110122
The file was modifiedmlir/lib/Dialect/SPIRV/IR/SPIRVOps.cpp (diff)
The file was modifiedmlir/include/mlir/IR/OpImplementation.h (diff)
The file was modifiedmlir/lib/Parser/AffineParser.cpp (diff)
The file was modifiedmlir/lib/Dialect/Async/IR/Async.cpp (diff)
The file was modifiedmlir/lib/Parser/LocationParser.cpp (diff)
The file was modifiedmlir/lib/Parser/Parser.h (diff)
The file was modifiedmlir/lib/Parser/Parser.cpp (diff)
The file was modifiedmlir/lib/Dialect/StandardOps/IR/Ops.cpp (diff)
The file was modifiedmlir/test/IR/invalid-affinemap.mlir (diff)
The file was modifiedmlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp (diff)
The file was modifiedmlir/lib/Parser/AttributeParser.cpp (diff)
The file was modifiedmlir/test/IR/invalid.mlir (diff)
The file was modifiedmlir/lib/Parser/TypeParser.cpp (diff)
Commit ea72b0319d7b0f0c2fcf41d121afa5d031b319d5 by yhs
BPF: make 32bit register spill with 64bit alignment

In llvm, for non-alu32 mode, the stack alignment is 64bit so only one
64bit spill per 64bit slot. For alu32 mode, the stack alignment
is 32bit, so it is possible to have two 32bit spills per
64bit slot.

Currently, bpf kernel verifier does not preserve register states
for 32bit spills. That is, one 32bit register may hold a constant
value or a bounded range before spill. After reload from the
stack, the information is lost and sometimes this may cause
verifier failure. For 64bit register spill, the verifier
indeed tries to preserve the register state for reloading.

The current verifier can be modestly changed to handle one
32bit spill per 64bit stack slot with state-preserving reload.
Handling two 32bit spills per 64bit stack slot will require
substantial changes.

This patch changes stack alignment for alu32 to be 64bit.
This way, for any 64bit slot in alu32 mode, only one
32bit or 64bit register values can be saved. Together
with previous-mentioned verifier enhancement, 32bit
spill can be handled with state preserving.

Note that llvm stack slot coallescing
seems only doing adjacent packing which may leave some holes
in the stack. For example,
   stack slot 8   <== 8 bytes
   stack slot 4   <== 8 bytes with 4 byte hole
   stack slot 8   <== 8 bytes
   stack slot 4   <== 4 bytes

Differential Revision: https://reviews.llvm.org/D109073
The file was modifiedllvm/lib/Target/BPF/BPFRegisterInfo.td (diff)
The file was addedllvm/test/CodeGen/BPF/spill-alu32.ll