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Started 28 days ago
Took 8 hr 1 min

Build #4462 (Sep 22, 2021 4:17:32 PM)

Changes
  1. Avoid building the entire tree and testing LLVM itself on MLIR builders (details / githubweb)
Changes
  1. [mlir][sparse] cleanup ABI issues in C interface with memrefs (details / githubweb)
  2. [PowerPC] add testcase for chain commoning; nfc (details / githubweb)
  3. tsan: don't call dlsym during exit (details / githubweb)
  4. tsan: move errno spoiling reporting into a separate function (NFC) (details / githubweb)
  5. tsan: enable sse4.2 in tests (details / githubweb)
  6. [Polly] Add -polly-reschedule and -polly-postopts options. (details / githubweb)
  7. tsan: reset destination range in Java heap move (details / githubweb)
  8. tsan: uninline Enable/DisableIgnores (details / githubweb)
  9. tsan: prepare for trace mapping removal (details / githubweb)
  10. [lldb] Add --stack option to `target symbols add` command (details / githubweb)
  11. [flang] Change complex type define in runtime for clang-cl (details / githubweb)
  12. [InstCombine] Move InstCombineWorklist to Utils to allow reuse (NFC). (details / githubweb)
  13. [clang][ASTImporter] Generic attribute import handling (first step). (details / githubweb)
  14. [Utils] Replace llc with cat for tests (details / githubweb)
  15. tsan: account for mid app range in mem profile (details / githubweb)
  16. tsan: include MBlock/SyncObj stats into mem profile (details / githubweb)
  17. tsan: make mem profile data more consistent (details / githubweb)
  18. tsan: include internal allocator info in mem profile (details / githubweb)
  19. tsan: move mem profile initialization into separate function (details / githubweb)
  20. tsan: remove stale comment (details / githubweb)
  21. tsan: write uptime in mem profile (details / githubweb)
  22. [ARM] Add additional tests for VMOVL in tail predicated loops. (details / githubweb)
  23. [AMDGPU] Divergence-driven instruction selection for mul i32 (details / githubweb)
  24. [AMDGPU] Convert mac/fmac to mad/fma when folding output modifiers (details / githubweb)
  25. [AArch64][SVE] Add missing load/store patterns for unpacked bfloat vectors. (details / githubweb)
  26. [VectorCombine] Switch to using a worklist. (details / githubweb)
  27. [LoopVectorize][X86] Add operands to make it more obvious what line the CHECK concerns (details / githubweb)
  28. [SelectionDAG] Make WidenVecRes_Convert work for scalable vectors. (details / githubweb)
  29. [hwasan] also omit safe mem[cpy|mov|set]. (details / githubweb)
  30. Don't fold (select C, (gep Ptr, Idx), Ptr) if C is vector but Idx is scalar (details / githubweb)
  31. Unbreak module builds by making InstructionWorklist.h non-modular (details / githubweb)
  32. [ARM] Allow smaller VMOVL in tail predicated loops (details / githubweb)
  33. [lldb] [Windows] Fix continuing from breakpoints and singlestepping on ARM/AArch64 (details / githubweb)
  34. [Matrix] Emit assumption that matrix indices are valid. (details / githubweb)
  35. Revert "[CodeGen] regenerate test checks; NFC" (details / githubweb)
  36. Revert "[InstCombine] fold cast of right-shift if high bits are not demanded" (details / githubweb)
  37. [Passes] Run vector-combine early with -fenable-matrix. (details / githubweb)
  38. [gn build] (manually) port f8b1cc365786 (details / githubweb)
  39. [gn build] Port 7a320b279d07 (details / githubweb)
  40. [SelectionDAG] Add PromoteIntOp_INSERT_SUBVECTOR. (details / githubweb)
  41. [lldb] JITLoaderGDB tests can use lli in ORC greedy mode (details / githubweb)

Started by upstream project clang-stage2-Rthinlto_relay build number 6304
originally caused by:

This run spent:

  • 10 hr waiting;
  • 8 hr 1 min build duration;
  • 18 hr total from scheduled to completion.
Revision: fbdda46df1702d87909e66856796ffaefb5c0b41
Repository: https://github.com/llvm/llvm-zorg.git
  • refs/remotes/origin/main
Revision: 9689c1b7bb77d65e8acc9a13e5e416803d38b02f
Repository: https://github.com/llvm/llvm-project.git
  • detached
Test Result (no failures)