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Started 1 yr 4 mo ago
Took 15 hr

Build #4471 (Sep 25, 2021 11:17:26 PM)

Changes
  1. [RISCV] Fix incorrect operand type of inst alias for InstR4 (details / githubweb)
  2. [TTI] getUserCost - Ensure a vector insert/extract index is in unsigned 32-bit range (details / githubweb)
  3. tsan: uninline RacyStacks::operator== (details / githubweb)
  4. [ARM] Fix Arm block placement creating branches after jump tables. (details / githubweb)
  5. [MLIR] Add functionality to remove redundant local variables (details / githubweb)
  6. [DAG] combineShiftToMULH - move getValueType() inside assert. NFCI. (details / githubweb)
  7. [IR] DIBuilder::createEnumerator - pass APSInt by const reference (details / githubweb)
  8. [CMake] Consistently use the LibXml2::LibXml2 target instead of LIBXML2_LIBRARIES (details / githubweb)
  9. [InstCombine] Ensure shifts are in range for (X << C1) / C2 -> X fold. (details / githubweb)
  10. [fir] Add desc to fir.array_load op and update operand name (details / githubweb)
  11. [lldb] Convert misc. StringConvert uses (details / githubweb)
  12. [X86] combineShiftToPMULH - relax from ISA from SSE41 to SSE2 (details / githubweb)
  13. [X86] X86FastISel::fastMaterializeConstant - break if-else chain to fix llvm-else-after-return warning. NFCI (details / githubweb)
  14. [X86][SSE] combineMulToPMADDWD - enable sext(v8i16) -> zext(v8i16) fold on pre-SSE41 targets (details / githubweb)
  15. [Mips] Remove redundant declarations (NFC) (details / githubweb)
  16. [X86][SSE] combineMulToPMADDWD - enable sext(v8i16) -> zext(v8i16) fold on sub-128 bit vectors (details / githubweb)
  17. [X86][SSE] combineMulToPMADDWD - mask off upper bits of sign-extended vXi32 constants (details / githubweb)
  18. [CostModel][X86] Adjust vXi32 multiply costs if it can be performed using PMADDWD (details / githubweb)
  19. [clang-format] Left/Right alignment fixer can cause false positive replacements when they don't actually change anything (details / githubweb)
  20. [DAG] ReduceLoadOpStoreWidth - replace getABITypeAlign with allowsMemoryAccess (PR45116) (details / githubweb)
  21. [ORC] Introduce EPCGenericRTDyldMemoryManager. (details / githubweb)
  22. [lli] Add ChildTarget dependence on OrcTargetProcess library. (details / githubweb)
  23. Revert "[ORC] Introduce EPCGenericRTDyldMemoryManager." (details / githubweb)
  24. [ELF][test] Improve test coverage (details / githubweb)
  25. [ORC-RT] ExecutorAddrDiff ergonomic improvements; contains and overlaps methods (details / githubweb)
  26. [BasicAA] Don't consider Argument as escape source (NFCI) (details / githubweb)
  27. [DSE] Make capture check more precise (details / githubweb)
  28. [AA] Move earliest escape tracking from DSE to AA (details / githubweb)
  29. [ELF] Default gotBaseSymInGotPlt to false (NFC for most architectures) (details / githubweb)

Started by upstream project clang-stage2-Rthinlto_relay build number 6313
originally caused by:

This run spent:

  • 7 hr 3 min waiting;
  • 15 hr build duration;
  • 22 hr total from scheduled to completion.
Revision: eb9c9a7dce812e06645e9ae1fdeabad4736a2ae6
Repository: https://github.com/llvm/llvm-zorg.git
  • refs/remotes/origin/main
Revision: 40cd4db442994e2bac6704e34580246c1d0bd91d
Repository: https://github.com/llvm/llvm-project.git
  • detached
Test Result (1 failure / +1)

Identified problems

Ninja target failed

Below is a link to the first failed ninja target.
Indication 1

Regression test failed

This build failed because a regression test in the test suite FAILed. See the test report for details.
Indication 2

Compile Error

This build failed because of a compile error. Below is a list of all errors in the build log:
Indication 3