Changes

Summary

  1. [NFC][AArch64] Un-autogenerate swifterror.ll tests (details)
  2. [SimplifyCFG] Tail-merging all blocks with `ret` terminator (details)
  3. [GlobalISel] NFC: Change LLT::vector to take ElementCount. (details)
  4. [X86] Fold nested select_cc to select (cmp*ge/le Cond0, Cond1), LHS, Y) (details)
  5. [Clang] XFAIL sanitize-coverage-old-pm.c on 32bit Armv8l (details)
  6. [mlir][Linalg] Add basic lowering test to library calls (details)
  7. [CostModel][AArch64] Improve cost model for vector reduction intrinsics (details)
  8. [SCEV] Generalize MatchBinaryAddToConst to support non-add expressions. (details)
  9. [X86] Exclude invalid element types for bitcast/broadcast folding. (details)
  10. [MCA] Allow unlimited cycles in the timeline view (details)
  11. [NFC][SimplifyCFG] Add basic test for tail-merging `resume` function terminators (details)
  12. [ARM] Extend narrow values to allow using truncating scatters (details)
  13. [DebugInfo] Enable variadic debug value salvaging (details)
  14. [mlir][linalg][python] Add attribute support to the YAML codegen. (details)
  15. [LV] Support sinking recipe in replicate region after another region. (details)
Commit cba4b104a9c14a472521776015571873dc347506 by lebedev.ri
[NFC][AArch64] Un-autogenerate swifterror.ll tests

It appears the change needed in D104597 is minimal and obvious,
so let's not make them so verbose.
The file was modifiedllvm/test/CodeGen/AArch64/swifterror.ll
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/swifterror.ll
Commit 9c4c2f24725e9f98b96fb360894276d342c3ba50 by lebedev.ri
[SimplifyCFG] Tail-merging all blocks with `ret` terminator

Based ontop of D104598, which is a NFCI-ish refactoring.
Here, a restriction, that only empty blocks can be merged, is lifted.

Reviewed By: rnk

Differential Revision: https://reviews.llvm.org/D104597
The file was modifiedllvm/test/Transforms/SimplifyCFG/indirectbr.ll
The file was modifiedllvm/test/CodeGen/AArch64/branch-relax-alignment.ll
The file was modifiedllvm/test/CodeGen/AArch64/cgp-usubo.ll
The file was modifiedllvm/test/Transforms/SimplifyCFG/branch-phi-thread.ll
The file was modifiedllvm/test/CodeGen/ARM/ifcvt5.ll
The file was modifiedllvm/test/CodeGen/AArch64/statepoint-call-lowering.ll
The file was modifiedllvm/test/CodeGen/AArch64/implicit-null-check.ll
The file was modifiedllvm/test/CodeGen/AArch64/ldst-paired-aliasing.ll
The file was modifiedllvm/test/CodeGen/ARM/speculation-hardening-sls.ll
The file was modifiedllvm/test/CodeGen/AArch64/sve-breakdown-scalable-vectortype.ll
The file was modifiedllvm/test/CodeGen/AArch64/swifterror.ll
The file was modifiedllvm/test/CodeGen/ARM/fp16-promote.ll
The file was modifiedllvm/test/CodeGen/AArch64/branch-relax-bcc.ll
The file was modifiedllvm/test/CodeGen/ARM/ifcvt-iter-indbr.ll
The file was modifiedllvm/test/CodeGen/AArch64/combine-comparisons-by-cse.ll
The file was modifiedllvm/test/Transforms/SimplifyCFG/fold-branch-to-common-dest-two-preds-cost.ll
The file was modifiedllvm/test/Transforms/SimplifyCFG/pr39807.ll
The file was modifiedllvm/test/CodeGen/ARM/cfguard-checks.ll
The file was modifiedllvm/test/Transforms/PruneEH/ipo-nounwind.ll
The file was modifiedllvm/test/CodeGen/ARM/ifcvt-callback.ll
The file was modifiedllvm/test/Transforms/SimplifyCFG/branch-fold.ll
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/irtranslator-condbr-lower-tree.ll
The file was modifiedllvm/test/CodeGen/ARM/switch-minsize.ll
The file was modifiedllvm/test/Transforms/PhaseOrdering/X86/vector-reductions.ll
The file was modifiedllvm/test/CodeGen/AArch64/arm64-instruction-mix-remarks.ll
The file was modifiedllvm/test/Transforms/PhaseOrdering/X86/simplifycfg-late.ll
The file was modifiedllvm/test/CodeGen/Thumb2/v8_IT_4.ll
The file was modifiedllvm/test/CodeGen/AArch64/addsub.ll
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/swifterror.ll
The file was modifiedllvm/test/CodeGen/ARM/ifcvt3.ll
The file was modifiedllvm/test/Transforms/SimplifyCFG/basictest.ll
The file was modifiedllvm/test/CodeGen/AArch64/fast-isel-branch-cond-split.ll
The file was modifiedllvm/test/Transforms/SimplifyCFG/guards.ll
The file was modifiedllvm/test/Transforms/SimplifyCFG/pr46638.ll
The file was modifiedllvm/test/CodeGen/ARM/load-global2.ll
The file was modifiedllvm/test/CodeGen/ARM/smml.ll
The file was modifiedllvm/test/CodeGen/Hexagon/noFalignAfterCallAtO2.ll
The file was modifiedllvm/test/CodeGen/Thumb2/tpsoft.ll
The file was modifiedllvm/test/Transforms/SimplifyCFG/HoistCode.ll
The file was modifiedllvm/test/Transforms/SimplifyCFG/duplicate-landingpad.ll
The file was modifiedllvm/test/Transforms/SimplifyCFG/switch-dead-default.ll
The file was modifiedllvm/test/Transforms/PhaseOrdering/inlining-alignment-assumptions.ll
The file was modifiedllvm/test/CodeGen/AArch64/check-sign-bit-before-extension.ll
The file was modifiedllvm/test/CodeGen/Hexagon/dont_rotate_pregs_at_O2.ll
The file was modifiedllvm/test/Transforms/SimplifyCFG/switch_switch_fold.ll
The file was modifiedllvm/test/Transforms/SimplifyCFG/invoke.ll
The file was modifiedllvm/test/Transforms/PGOProfile/chr.ll
The file was modifiedllvm/test/CodeGen/AArch64/ldst-opt-after-block-placement.ll
The file was modifiedllvm/test/Transforms/SimplifyCFG/fold-branch-to-common-dest.ll
The file was modifiedllvm/test/CodeGen/ARM/ifcvt6.ll
The file was modifiedllvm/test/Transforms/SimplifyCFG/switch-range-to-icmp.ll
The file was modifiedllvm/test/CodeGen/ARM/ifcvt1.ll
The file was modifiedllvm/test/CodeGen/AArch64/vec-extract-branch.ll
The file was modifiedllvm/lib/Transforms/Scalar/SimplifyCFGPass.cpp
The file was modifiedllvm/test/CodeGen/AArch64/optimize-cond-branch.ll
The file was modifiedllvm/test/Transforms/SimplifyCFG/unprofitable-pr.ll
The file was modifiedllvm/test/CodeGen/AArch64/cfguard-checks.ll
The file was modifiedllvm/test/CodeGen/AArch64/use-cr-result-of-dom-icmp-st.ll
The file was modifiedllvm/test/Transforms/SimplifyCFG/switch_create.ll
The file was modifiedllvm/test/CodeGen/AArch64/branch-relax-asm.ll
The file was modifiedllvm/test/Transforms/SimplifyCFG/DeadSetCC.ll
The file was modifiedllvm/test/Transforms/SimplifyCFG/Hexagon/switch-to-lookup-table.ll
The file was modifiedllvm/test/Transforms/LoopUnroll/ARM/upperbound.ll
The file was modifiedllvm/test/CodeGen/Thumb2/thumb2-ifcvt1.ll
The file was modifiedllvm/test/CodeGen/AArch64/cond-br-tuning.ll
The file was modifiedllvm/test/Transforms/SimplifyCFG/switch-on-const-select.ll
The file was modifiedllvm/test/Transforms/SimplifyCFG/switch_create-custom-dl.ll
The file was modifiedllvm/test/Transforms/SimplifyCFG/FoldValueComparisonIntoPredecessors-domtree-preservation-edgecase-2.ll
The file was modifiedllvm/test/Transforms/SimplifyCFG/switch_thread.ll
The file was modifiedllvm/test/CodeGen/ARM/thumb2-size-opt.ll
The file was modifiedllvm/test/Transforms/SimplifyCFG/hoist-common-code.ll
The file was modifiedllvm/test/CodeGen/AArch64/f16-instructions.ll
The file was modifiedllvm/test/CodeGen/AArch64/branch-relax-cbz.ll
The file was modifiedllvm/test/Transforms/SimplifyCFG/preserve-branchweights.ll
The file was modifiedllvm/test/CodeGen/AArch64/logical_shifted_reg.ll
Commit d5e14ba88cbf353236faa45caf626c2a30a1cb0c by sander.desmalen
[GlobalISel] NFC: Change LLT::vector to take ElementCount.

This also adds new interfaces for the fixed- and scalable case:
* LLT::fixed_vector
* LLT::scalable_vector

The strategy for migrating to the new interfaces was as follows:
* If the new LLT is a (modified) clone of another LLT, taking the
  same number of elements, then use LLT::vector(OtherTy.getElementCount())
  or if the number of elements is halfed/doubled, it uses .divideCoefficientBy(2)
  or operator*. That is because there is no reason to specifically restrict
  the types to 'fixed_vector'.
* If the algorithm works on the number of elements (as unsigned), then
  just use fixed_vector. This will need to be fixed up in the future when
  modifying the algorithm to also work for scalable vectors, and will need
  then need additional tests to confirm the behaviour works the same for
  scalable vectors.
* If the test used the '/*Scalable=*/true` flag of LLT::vector, then
  this is replaced by LLT::scalable_vector.

Reviewed By: aemerson

Differential Revision: https://reviews.llvm.org/D104451
The file was modifiedllvm/unittests/CodeGen/GlobalISel/GISelUtilsTest.cpp
The file was modifiedllvm/unittests/CodeGen/GlobalISel/KnownBitsVectorTest.cpp
The file was modifiedllvm/lib/Target/X86/X86LegalizerInfo.cpp
The file was modifiedllvm/lib/CodeGen/GlobalISel/LegalizeMutations.cpp
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
The file was modifiedllvm/lib/Target/Mips/MipsLegalizerInfo.cpp
The file was modifiedllvm/lib/CodeGen/LowLevelType.cpp
The file was modifiedllvm/unittests/CodeGen/LowLevelTypeTest.cpp
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
The file was modifiedllvm/unittests/CodeGen/GlobalISel/CSETest.cpp
The file was modifiedllvm/lib/CodeGen/GlobalISel/LegacyLegalizerInfo.cpp
The file was modifiedllvm/lib/CodeGen/GlobalISel/CallLowering.cpp
The file was modifiedllvm/include/llvm/Support/LowLevelTypeImpl.h
The file was modifiedllvm/lib/CodeGen/GlobalISel/Utils.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUArgumentUsageInfo.cpp
The file was modifiedllvm/unittests/CodeGen/GlobalISel/LegalizerTest.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
The file was modifiedllvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
The file was modifiedllvm/unittests/CodeGen/GlobalISel/LegalizerInfoTest.cpp
The file was modifiedllvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
The file was modifiedllvm/unittests/CodeGen/GlobalISel/LegalizerHelperTest.cpp
The file was modifiedllvm/unittests/CodeGen/GlobalISel/MachineIRBuilderTest.cpp
The file was modifiedllvm/unittests/CodeGen/GlobalISel/PatternMatchTest.cpp
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUPreLegalizerCombiner.cpp
The file was modifiedllvm/lib/CodeGen/MIRParser/MIParser.cpp
The file was modifiedllvm/utils/TableGen/GlobalISelEmitter.cpp
Commit c4d3eedc7f1a954ba3a21af5fc9d4f8ecb37a6ac by llvm-dev
[X86] Fold nested select_cc to select (cmp*ge/le Cond0, Cond1), LHS, Y)

select (cmpeq Cond0, Cond1), LHS, (select (cmpugt Cond0, Cond1), LHS, Y) --> (select (cmpuge Cond0, Cond1), LHS, Y)
etc,

We already perform this fold in DAGCombiner for MVT::i1 comparison results, but these can still appear after legalization (in x86 case with MVT::i8 results), where we need to be more careful about generating new comparison codes.

Pulled out of D101074 to help address the remaining regressions.

Differential Revision: https://reviews.llvm.org/D104707
The file was modifiedllvm/test/CodeGen/X86/sdiv_fix_sat.ll
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was modifiedllvm/test/CodeGen/X86/udiv_fix_sat.ll
Commit c5028f3473ed50a7433fe278984cd1a755b338b9 by omair.javaid
[Clang] XFAIL sanitize-coverage-old-pm.c on 32bit Armv8l

sanitize-coverage-old-pm.c started failing on arm 32 bit where
underlying architecture reported is armv8l fore 32bit arm.
This patch XFAILS sanitize-coverage-old-pm.c on armv8l similar
to armv7 and thumbv7.
The file was modifiedclang/test/CodeGen/sanitize-coverage-old-pm.c
Commit e3ea2d706198c37b1564533676a5f85e4576504a by nicolas.vasilache
[mlir][Linalg] Add basic lowering test to library calls

This test shows how convert-linalg-to-std rewrites named linalg ops as library calls.
This can be coupled with a C++ shim to connect to existing libraries such as https://gist.github.com/nicolasvasilache/691ef992404c49dc9b5d543c4aa6db38.
Everything can then be linked together with mlir-cpu-runner and MLIR can call C++ (which can itself call MLIR if needed).

This should evolve into specific rewrite patterns that can be applied on op instances independently rather than having to use a full conversion.

Differential Revision: https://reviews.llvm.org/D104842
The file was addedmlir/test/Dialect/Linalg/library-calls.mlir
Commit 0c4651f0a883443259684aa6de69d26a5bd49e46 by rosie.sumpter
[CostModel][AArch64] Improve cost model for vector reduction intrinsics

OR, XOR and AND entries are added to the cost table. An extra cost
is added when vector splitting occurs.

This is done to address the issue of a missed SLP vectorization
opportunity due to unreasonably high costs being attributed to the vector
Or reduction (see: https://bugs.llvm.org/show_bug.cgi?id=44593).

Differential Revision: https://reviews.llvm.org/D104538
The file was modifiedllvm/test/Analysis/CostModel/AArch64/reduce-and.ll
The file was modifiedllvm/test/Analysis/CostModel/AArch64/reduce-or.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/AArch64/slp-xor-reduction.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
The file was addedllvm/test/Analysis/CostModel/AArch64/reduce-xor.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/AArch64/slp-and-reduction.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/AArch64/slp-or-reduction.ll
Commit 121ecb05e73427ab3bc6ceeca04fbab161417e6e by flo
[SCEV] Generalize MatchBinaryAddToConst to support non-add expressions.

This patch generalizes MatchBinaryAddToConst to support matching
(A + C1), (A + C2), instead of just matching (A + C1), A.

The existing cases can be handled by treating non-add expressions A as
A + 0.

Reviewed By: mkazantsev

Differential Revision: https://reviews.llvm.org/D104634
The file was modifiedllvm/lib/Analysis/ScalarEvolution.cpp
Commit a54c6fc083c45595466c2d3d73ccf80c07ef1247 by flo
[X86] Exclude invalid element types for bitcast/broadcast folding.

It looks like the fold introduced in 63f3383ece25efa can cause crashes
if the type of the bitcasted value is not a valid vector element type,
like x86_mmx.

To resolve the crash, reject invalid vector element types. The way it is
done in the patch is a bit clunky. Perhaps there's a better way to
check?

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D104792
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was modifiedllvm/test/CodeGen/X86/avx-vbroadcast.ll
The file was modifiedllvm/test/CodeGen/X86/avx2-vbroadcast.ll
Commit beebe5a056b8d4d224b07c5039f8e6028a7afb4c by jay.foad
[MCA] Allow unlimited cycles in the timeline view

Change --max-timeline-cycles=0 to mean no limit on the number of cycles.
Use this in AMDGPU tests to show all instructions in the timeline view
instead of having it arbitrarily truncated.

Differential Revision: https://reviews.llvm.org/D104846
The file was modifiedllvm/test/tools/llvm-mca/AMDGPU/gfx10-double.s
The file was modifiedllvm/tools/llvm-mca/Views/TimelineView.cpp
The file was modifiedllvm/test/tools/llvm-mca/AMDGPU/gfx10-add-sequence.s
The file was modifiedllvm/test/tools/llvm-mca/AMDGPU/gfx10-trans.s
The file was modifiedllvm/tools/llvm-mca/llvm-mca.cpp
The file was modifiedllvm/docs/CommandGuide/llvm-mca.rst
Commit 9f5f91778710a891b2b5ccafeb783c3609192ae8 by lebedev.ri
[NFC][SimplifyCFG] Add basic test for tail-merging `resume` function terminators
The file was addedllvm/test/Transforms/SimplifyCFG/tail-merge-resume.ll
Commit 1113e06821e6baffc84b8caf96a28bf62e6d28dc by david.green
[ARM] Extend narrow values to allow using truncating scatters

As a minor adjustment to the existing lowering of offset scatters, this
extends any smaller-than-legal vectors into full vectors using a zext,
so that the truncating scatters can be used. Due to the way MVE
legalizes the vectors this should be cheap in most situations, and will
prevent the vector from being scalarized.

Differential Revision: https://reviews.llvm.org/D103704
The file was modifiedllvm/test/CodeGen/Thumb2/mve-scatter-ind32-unscaled.ll
The file was modifiedllvm/test/CodeGen/Thumb2/mve-scatter-ind8-unscaled.ll
The file was modifiedllvm/lib/Target/ARM/MVEGatherScatterLowering.cpp
The file was modifiedllvm/test/CodeGen/Thumb2/mve-scatter-ptrs.ll
Commit adace79652174d126be290cab42b3122569fe15d by stephen.tozer
[DebugInfo] Enable variadic debug value salvaging

This patch enables the salvaging of debug values that may be calculated
from more than one SSA value, such as with binary operators that do not
use a constant argument. The actual functionality for this behaviour is
added in a previous commit (c7270567), but with the ability to actually
emit the resulting debug values switched off.

The reason for this is that the prior patch has been reverted several
times due to issues discovered downstream, some time after the actual
landing of the patch. The patch in question is rather large and touches
several widely used header files, and all issues discovered are more
related to the handling of variadic debug values as a whole rather than
the details of the patch itself. Therefore, to minimize the build time
impact and risk of conflicts involved in any potential future
revert/reapply of that patch, this significantly smaller patch (that
touches no header files) will instead be used as the capstone to enable
variadic debug value salvaging.

The review linked to this patch is mostly implemented by the previous
commit, c7270567, but also contains the changes in this patch.

Differential Revision: https://reviews.llvm.org/D91722
The file was modifiedllvm/test/DebugInfo/salvage-nonconst-binop.ll
The file was modifiedllvm/test/DebugInfo/NVPTX/debug-info.ll
The file was modifiedllvm/lib/Transforms/Utils/Local.cpp
The file was modifiedllvm/test/DebugInfo/salvage-gep.ll
Commit 25bb61649085c0a6e66630bbffe7faa54cd67829 by gysit
[mlir][linalg][python] Add attribute support to the YAML codegen.

Extend the yaml code generation to support the index attributes that https://reviews.llvm.org/D104711 added to the OpDSL.

Differential Revision: https://reviews.llvm.org/D104712
The file was modifiedmlir/test/python/dialects/linalg/opdsl/arguments.py
The file was modifiedmlir/include/mlir/Dialect/Linalg/IR/LinalgNamedStructuredOps.yaml
The file was modifiedmlir/tools/mlir-linalg-ods-gen/mlir-linalg-ods-yaml-gen.cpp
The file was modifiedmlir/test/mlir-linalg-ods-gen/test-linalg-ods-yaml-gen.yaml
The file was modifiedmlir/test/python/dialects/linalg/opsrun.py
The file was modifiedmlir/test/Dialect/Linalg/generalize-named-polymorphic-ops.mlir
Commit 833bdbe93cd6b114ec09904fed5dc5288343a549 by flo
[LV] Support sinking recipe in replicate region after another region.

This patch handles sinking a replicate region after another replicate
region. In that case, we can connect the sink region after the target
region. This properly handles the case for which an assertion has been
added in 337d7652823f.

Fixes https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=34842.

Reviewed By: Ayal

Differential Revision: https://reviews.llvm.org/D103514
The file was modifiedllvm/lib/Transforms/Vectorize/LoopVectorize.cpp
The file was modifiedllvm/test/Transforms/LoopVectorize/first-order-recurrence-sink-replicate-region.ll