FailedChanges

Summary

  1. [AsmParser][ARM] Make .thumb_func imply .thumb (details)
  2. [llvm][NFC] Remove deprecated TargetFrameLowering and InstrTypes alignment functions (details)
  3. [llvm][NFC] Remove remaining deprecated alignment functions from CodeGen (details)
  4. [llvm-dwarfdump] Help option output should be consistent with the command guide (details)
  5. [DebugInfo] Fix updateDbgUsersToReg to support DBG_VALUE_LIST (details)
  6. [NFC][X86][MCA] AMD Zen 3: add tests with eliminatible GPR moves (details)
  7. [X86] AMD Zen 3: 32/64 -bit GPR register moves are zero-cycle (details)
  8. [NFC][X86][MCA] AMD Zen 3: add tests with non-eliminatible MMX moves (details)
  9. AMDGPU: Correct const_index_stride for wave 32 for PAL ABI (details)
  10. [NFC] (test commit) Changed example invocation of C++ for OpenCL (details)
  11. [X86] Ensure we pass DebugLoc by const reference where possible. NFCI. (details)
  12. [SLP] Regenerate tests to reduce diff in D98714. NFCI. (details)
  13. Revert "AMDGPU: Correct const_index_stride for wave 32 for PAL ABI" (details)
  14. [DAG] Add a generic expansion for SHIFT_PARTS opcodes using funnel shifts (details)
  15. [DebugInfo] Fix crash when emitting an invalidated SDDbgValue (details)
Commit f87638338464e7ff9396e92e04e3f5702d479d39 by thatlemon
[AsmParser][ARM] Make .thumb_func imply .thumb

GNU as documentation states that a `.thumb_func` directive implies `.thumb`, teach the asm parser to switch mode whenever it's encountered. On the other hand the labeled form, exclusive to Apple's toolchain, doesn't switch mode at all.

Reviewed By: nickdesaulniers, peter.smith

Differential Revision: https://reviews.llvm.org/D101975
The file was modifiedllvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
The file was addedllvm/test/MC/ARM/thumb_func-implies-thumb.s
The file was modifiedlld/test/ELF/arm-ldrlit-err.s
Commit eb1b26ec1d1ac60b2207354fcd003cad40e12b76 by gchatelet
[llvm][NFC] Remove deprecated TargetFrameLowering and InstrTypes alignment functions

Differential Revision: https://reviews.llvm.org/D102056
The file was modifiedllvm/include/llvm/CodeGen/TargetFrameLowering.h
The file was modifiedllvm/include/llvm/IR/InstrTypes.h
Commit e805b7c2d63c1f8b74f228718a55536f54ddd1c0 by gchatelet
[llvm][NFC] Remove remaining deprecated alignment functions from CodeGen

Differential Revision: https://reviews.llvm.org/D102058
The file was modifiedllvm/include/llvm/CodeGen/MachineMemOperand.h
The file was modifiedllvm/include/llvm/CodeGen/MachineFrameInfo.h
The file was modifiedllvm/include/llvm/CodeGen/SelectionDAGNodes.h
The file was modifiedllvm/lib/CodeGen/MachineOperand.cpp
Commit f0762fc42f0f4ecf849bef42eed2bb4c0785ea67 by gbreynoo
[llvm-dwarfdump] Help option output should be consistent with the command guide

The dwarfdump command guide shows the short options used as aliases but
these are not found in the help text unless --show-hidden is used.
Investigating other tools some follow this pattern, others like
llvm-objdump show aliases with --help. This change fixes the help output
to be consistent with the command guide. This includes updating alias
descriptions in the help output to use "--".

As part of this change I updated cmdline.test, including some options
that were missing testing.

Differential Revision: https://reviews.llvm.org/D101646
The file was modifiedllvm/test/tools/llvm-dwarfdump/cmdline.test
The file was modifiedllvm/tools/llvm-dwarfdump/llvm-dwarfdump.cpp
Commit 0791f968fee259e5c34523167bd58179b8b081c2 by stephen.tozer
[DebugInfo] Fix updateDbgUsersToReg to support DBG_VALUE_LIST

This patch modifies updateDbgUsersToReg to properly handle
DBG_VALUE_LIST instructions, by replacing the hard-coded operand indices
(i.e. getOperand(0)) with the more general getDebugOperandsForReg(), and
updating the register for all matching operands.

Differential Revision: https://reviews.llvm.org/D101523
The file was modifiedllvm/lib/CodeGen/MachineCopyPropagation.cpp
The file was modifiedllvm/include/llvm/CodeGen/MachineRegisterInfo.h
The file was addedllvm/test/DebugInfo/ARM/machine-cp-updates-dbg-reg.mir
Commit 227678089cf6d8b15d51e58abfefd4f346e9c7f0 by lebedev.ri
[NFC][X86][MCA] AMD Zen 3: add tests with eliminatible GPR moves
The file was addedllvm/test/tools/llvm-mca/X86/Znver3/reg-move-elimination-gpr.s
Commit 7059b28d5d276cab89815b762d10431329a7da2a by lebedev.ri
[X86] AMD Zen 3: 32/64 -bit GPR register moves are zero-cycle

I've verified this with llvm-exegesis.
This is not limited to zero registers.

Refs:
AMD SOG 19h, 2.9.4 Zero Cycle Move
The processor is able to execute certain register to register
mov operations with zero cycle delay.

Agner,
22.13 Instructions with no latency
Register-to-register move instructions are resolved at
the register rename stage without using any execution units.
These instructions have zero latency. It is possible to do six such
register renamings per clock cycle, and it is even possible to
rename the same register multiple times in one clock cycle.
The file was modifiedllvm/lib/Target/X86/X86ScheduleZnver3.td
The file was modifiedllvm/test/tools/llvm-mca/X86/Znver3/reg-move-elimination-gpr.s
Commit bda9ca3e44c1b67d1c4ed145bb7071c340fe8961 by lebedev.ri
[NFC][X86][MCA] AMD Zen 3: add tests with non-eliminatible MMX moves

In Zen3, MMX moves are *not* eliminated,
i've verified this with llvm-exegesis.
The file was addedllvm/test/tools/llvm-mca/X86/Znver3/reg-move-elimination-mmx.s
Commit 442de0c1adf36bfddb5fb66b442bba8999fa733b by david.stuttard
AMDGPU: Correct const_index_stride for wave 32 for PAL ABI

Since there is a single scratch resource descriptor for all shaders, if there is
a wave32 and a wave64 shader (for instance for VsFs pairs)
then the const_index_stride will be incorrect for wave32 shaders.

Differential Revision: https://reviews.llvm.org/D101830

Change-Id: Id8de5566b0d1a07a814e2e7db016df9d20bf6d2c
The file was modifiedllvm/test/CodeGen/AMDGPU/pal-simple-indirect-call.ll
The file was modifiedllvm/lib/Target/AMDGPU/SIFrameLowering.cpp
Commit f372ff17f74f99f5e1c021a9c919b33c4caf38d9 by olemarius.strohm
[NFC] (test commit) Changed example invocation of C++ for OpenCL
The file was modifiedclang/docs/OpenCLSupport.rst
Commit 8e42024f79997827cefe00d31cd3bc55d1551fec by llvm-dev
[X86] Ensure we pass DebugLoc by const reference where possible. NFCI.

Avoids a lot of unnecessary tracking increments/decrements of the underlying TrackingMDNodeRef
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
Commit 2a3f60b5f5304f61cab3654a6afb67b79ca7df86 by llvm-dev
[SLP] Regenerate tests to reduce diff in D98714. NFCI.
The file was modifiedllvm/test/Transforms/SLPVectorizer/vectorizable-functions.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/vectorizable-functions-inseltpoison.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/pr44067.ll
Commit 793b4b26039e461dc3142a3f667ba7c97b0ed920 by david.stuttard
Revert "AMDGPU: Correct const_index_stride for wave 32 for PAL ABI"

This reverts commit 442de0c1adf36bfddb5fb66b442bba8999fa733b.
The file was modifiedllvm/test/CodeGen/AMDGPU/pal-simple-indirect-call.ll
The file was modifiedllvm/lib/Target/AMDGPU/SIFrameLowering.cpp
Commit 280aa3415e408cacc520274fdb948ec9fc63865a by llvm-dev
[DAG] Add a generic expansion for SHIFT_PARTS opcodes using funnel shifts

Based off a discussion on D89281 - where the AARCH64 implementations were being replaced to use funnel shifts.

Any target that has efficient funnel shift lowering can handle the shift parts expansion using the same expansion, avoiding a lot of duplication.

I've generalized the X86 implementation and moved it to TargetLowering - so far I've found that AARCH64 and AMDGPU benefit, but many other targets (ARM, PowerPC + RISCV in particular) could easily use this with a few minor improvements to their funnel shift lowering (or the folding of their target ops that funnel shifts lower to).

NOTE: I'm trying to avoid adding full SHIFT_PARTS legalizer handling as I think it might actually be possible to remove these opcodes in the medium-term and use funnel shift / libcall expansion directly.

Differential Revision: https://reviews.llvm.org/D101987
The file was modifiedllvm/test/CodeGen/AMDGPU/sra.ll
The file was modifiedllvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/fp_to_uint.ll
The file was modifiedllvm/include/llvm/CodeGen/TargetLowering.h
The file was modifiedllvm/test/CodeGen/AMDGPU/srl.ll
The file was modifiedllvm/test/CodeGen/AArch64/arm64-long-shift.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/fp_to_sint.ll
The file was modifiedllvm/lib/Target/AMDGPU/R600ISelLowering.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/shl.ll
The file was modifiedllvm/lib/Target/AMDGPU/R600ISelLowering.h
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.h
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
Commit ce0c1f3ced9bccb29c34b87de82c5cdffcbcd457 by stephen.tozer
[DebugInfo] Fix crash when emitting an invalidated SDDbgValue

This patch fixes a crash in the compiler that occurs when certain
invalidated SDDbgValues are emitted. The cause of this was that we would
attempt to check the liveness of the debug value's operands, which
triggers an assert if any of those operands are invalid. This patch
changes this check such that it only occurs if the SDDbgValue is valid;
if not, the check is irrelevant anyway, so can be safely ignored.

Differential Revision: https://reviews.llvm.org/D101540
The file was modifiedllvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
The file was addedllvm/test/DebugInfo/Generic/invalidated-dbg-value-is-undef.ll