FailedChanges

Summary

  1. [APInt][NFC] Fix typo vlalue->value (details)
  2. [RISCV][NFC] Correct alignment in scatter/gather tests (details)
  3. [AMDGPU] Tweak VOP3_INTERP16 profile (details)
  4. [clang] In DependencyCollector on Windows, ignore case and separators when discarding duplicate dependency file paths. (details)
  5. [X86] Don't dereference a dyn_cast<> - use a cast<> instead. NFCI. (details)
  6. [x86] update fma test with deprecated intrinsics; NFC (details)
  7. [mlir][openacc] Translate ExitDataop to LLVM IR (details)
  8. [AIX] Implement AIX special bitfield related alignment rules (details)
  9. [AMDGPU] Set unused dst_sel to '?' in the encoding (details)
  10. [LoopUnroll] Add multi-exit test which does not exit through latch. (details)
  11. [OpenMP] Fixed Bug 49356 (details)
  12. [HWASan] Build separate LAM runtime on x86_64. (details)
  13. [llvm][doc] fix header for read/write_register intrinsics in LangRef (details)
  14. [Clang][NVPTX] Add NVPTX intrinsics and builtins for CUDA PTX cp.async instructions (details)
  15. [Clang][NVPTX] Add NVPTX intrinsics and builtins for CUDA PTX redux.sync instructions (details)
  16. [mlir][tosa] Fix tosa.avg_pool2d lowering to normalize correctly (details)
Commit b6e4bfd18571b65bf3c537f52225d8ee6c2953c4 by weratt
[APInt][NFC] Fix typo vlalue->value

Reviewed By: fhahn

Differential Revision: https://reviews.llvm.org/D102618
The file was modifiedllvm/include/llvm/ADT/APInt.h
Commit cd73ce4b5e622bb4d71b41f9dab157200501d352 by fraser
[RISCV][NFC] Correct alignment in scatter/gather tests

This lays the groundwork for changes to alignment in D102493 to be more
apparent.
The file was modifiedllvm/test/Analysis/CostModel/RISCV/fixed-vector-scatter.ll
The file was modifiedllvm/test/Analysis/CostModel/RISCV/fixed-vector-gather.ll
Commit 472f856714fb1687b0727b3013f5d071d8fa86ae by jay.foad
[AMDGPU] Tweak VOP3_INTERP16 profile

Set the output register class based on the output type, instead of
hard-coding VGPR_32. I think this is more correct. It doesn't make any
difference at the moment because we use the same class for 16- and
32-bit results, but it might in future if we make more use of true
16-bit register classes.

Differential Revision: https://reviews.llvm.org/D102622
The file was modifiedllvm/lib/Target/AMDGPU/VOP3Instructions.td
Commit 6052a8a53559d667321637f7159353ab724a1141 by sylvain.audi
[clang] In DependencyCollector on Windows, ignore case and separators when discarding duplicate dependency file paths.

This patch removes duplicates also encountered in the output of clang-scan-deps when one same header file is encountered with different casing and/or different separators ('/' vs '\').

The case of separators can appear when the same file is included externally by
`#include <folder/file.h>`

whereas a file from the same folder does
`#include "file.h"`

Under Windows, clang computes the paths using '/' from the include directive, the `\` from the -I options, and the concatenations use the native `\`, leading to internal paths containing a mix of both separators.

Differential Revision: https://reviews.llvm.org/D102339
The file was modifiedclang/lib/Frontend/DependencyFile.cpp
The file was addedclang/test/Frontend/dependency-gen-windows-duplicates.c
Commit 41587466aaf239d061ad084114ec749cecbb2966 by llvm-dev
[X86] Don't dereference a dyn_cast<> - use a cast<> instead. NFCI.

dyn_cast<> can return null if the cast fails, by using cast<> we assert that the cast is correct helping to avoid a potential null dereference.
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
Commit 8854b27b198c1c499ca174369fcc649060afb075 by spatel
[x86] update fma test with deprecated intrinsics; NFC

All of the CHECK lines should be identical to before,
but without any of the x86-specific calls that were
replaced with generic FMA long ago.

The file still has value because it shows a miscompile
as demonstrated in D90901, but we probably need to
add tests with FMF to make that explicit without
losing coverage.
The file was modifiedllvm/test/CodeGen/X86/avx2-fma-fneg-combine.ll
Commit ab5ff154abe59d04f77035587c6a169c15168b2f by clementval
[mlir][openacc] Translate ExitDataop to LLVM IR

Translate ExitDataOp with delete and copyout operands to runtime call.
This is done in a similar way as D101504.

Reviewed By: kiranchandramohan

Differential Revision: https://reviews.llvm.org/D102381
The file was modifiedmlir/lib/Target/LLVMIR/Dialect/OpenACC/OpenACCToLLVMIRTranslation.cpp
The file was modifiedmlir/test/Target/LLVMIR/openacc-llvm.mlir
Commit e0921655b1ff8d4ba7c14be59252fe05b705920e by Xiangling.Liao
[AIX] Implement AIX special bitfield related alignment rules

1.[bool, char, short] bitfields have the same alignment as unsigned int
2.Adjust alignment on typedef field decls/honor align attribute
3.Fix alignment for scoped enum class
4.Long long bitfield has 4bytes alignment and StorageUnitSize under 32 bit
  compile mode

Differential Revision: https://reviews.llvm.org/D87029
The file was addedclang/test/Layout/aix-bitfield-alignment.c
The file was addedclang/test/Layout/aix-bitfield-alignment.cpp
The file was modifiedclang/lib/AST/RecordLayoutBuilder.cpp
Commit f4c0fdc6c9db616e2a50e3b39c615f972b4b3158 by Stanislav.Mekhanoshin
[AMDGPU] Set unused dst_sel to '?' in the encoding

This is to allow disasm with any bits in the unused fields.

Differential Revision: https://reviews.llvm.org/D102526
The file was modifiedllvm/test/MC/Disassembler/AMDGPU/sdwa_vi.txt
The file was modifiedllvm/lib/Target/AMDGPU/VOPInstructions.td
The file was modifiedllvm/test/MC/Disassembler/AMDGPU/sdwa_gfx9.txt
Commit fded6f77c357447b06b952f56c83d2a5487c5adf by flo
[LoopUnroll] Add multi-exit test which does not exit through latch.

This patch adds a new test for loop-unrolling with multiple exiting
blocks, where the latch does not exit, but the header does. This can
happen when the loop has not been rotated, e.g. due to minsize.

Inspired by the following end-to-end test, using -Oz
https://godbolt.org/z/fP6sna8qK

    bool foo(int *ptr, int limit) {
        #pragma clang loop unroll(full)
        for (unsigned int i = 0; i < 4; i++) {
            if (ptr[i] > limit)
            return false;
            ptr[i]++;
        }
        return true;
    }
The file was addedllvm/test/Transforms/LoopUnroll/unroll-header-exiting-with-phis-multiple-exiting-blocks.ll
Commit af6511d730f18beb9053c0120c45abef031344e9 by tianshilei1992
[OpenMP] Fixed Bug 49356

Bug 49356 (https://bugs.llvm.org/show_bug.cgi?id=49356) reports crash in
the test case `tasking/bug_taskwait_detach.cpp`, which is caused by the wrong
function declaration. `gtid` in `__kmpc_omp_task` should be `kmp_int32`.

Reviewed By: AndreyChurbanov

Differential Revision: https://reviews.llvm.org/D102584
The file was modifiedopenmp/runtime/test/tasking/bug_taskwait_detach.cpp
Commit 5f58322368b070b63fe2b2559a54f646cb97e2c4 by mascasa
[HWASan] Build separate LAM runtime on x86_64.

Since we have both aliasing mode and Intel LAM on x86_64, we need to
choose the mode at either run time or compile time.  This patch
implements the plumbing to build both and choose between them at
compile time.

Reviewed By: vitalybuka, eugenis

Differential Revision: https://reviews.llvm.org/D102286
The file was modifiedclang/lib/Driver/ToolChains/CommonArgs.cpp
The file was modifiedcompiler-rt/lib/hwasan/hwasan.h
The file was modifiedcompiler-rt/lib/hwasan/hwasan_dynamic_shadow.cpp
The file was modifiedcompiler-rt/lib/hwasan/hwasan_allocator.h
The file was modifiedcompiler-rt/lib/hwasan/CMakeLists.txt
The file was modifiedcompiler-rt/lib/hwasan/hwasan_linux.cpp
Commit 1417ddafdb68755300c115694ef8861302506062 by zinenko
[llvm][doc] fix header for read/write_register intrinsics in LangRef

Mutli-line headers are not allowed in RST, reformat the header to be a
single wide line.
The file was modifiedllvm/docs/LangRef.rst
Commit 02c2468864bbb37f7b279aff84961815c1500b6c by tra
[Clang][NVPTX] Add NVPTX intrinsics and builtins for CUDA PTX cp.async instructions

Adds NVPTX builtins and intrinsics for the CUDA PTX `cp.async` instructions for
`sm_80` architecture or newer.

PTX ISA description of `cp.async`:
https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-asynchronous-copy
https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-cp-async-mbarrier-arrive

Authored-by: Stuart Adams <stuart.adams@codeplay.com>
Co-Authored-by: Alexander Johnston <alexander@codeplay.com>

Differential Revision: https://reviews.llvm.org/D100394
The file was addedllvm/test/CodeGen/NVPTX/async-copy.ll
The file was modifiedllvm/lib/Target/NVPTX/NVPTXInstrInfo.td
The file was addedllvm/test/CodeGen/NVPTX/mbarrier.ll
The file was modifiedclang/include/clang/Basic/BuiltinsNVPTX.def
The file was modifiedclang/test/CodeGen/builtins-nvptx.c
The file was modifiedllvm/include/llvm/IR/IntrinsicsNVVM.td
The file was modifiedllvm/lib/Target/NVPTX/NVPTXIntrinsics.td
Commit f226e28a880f8e40b1bfd4c77b9768a667372d22 by tra
[Clang][NVPTX] Add NVPTX intrinsics and builtins for CUDA PTX redux.sync instructions

Adds NVPTX builtins and intrinsics for the CUDA PTX `redux.sync` instructions
for `sm_80` architecture or newer.

PTX ISA description of `redux.sync`:
https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-redux-sync

Authored-by: Steffen Larsen <steffen.larsen@codeplay.com>

Differential Revision: https://reviews.llvm.org/D100124
The file was addedclang/test/CodeGenCUDA/redux-builtins.cu
The file was addedllvm/test/CodeGen/NVPTX/redux-sync.ll
The file was modifiedclang/include/clang/Basic/BuiltinsNVPTX.def
The file was modifiedllvm/lib/Target/NVPTX/NVPTXIntrinsics.td
The file was modifiedllvm/include/llvm/IR/IntrinsicsNVVM.td
Commit 08068ddba7f52255fa39968207309f3d1ad98223 by rob.suderman
[mlir][tosa] Fix tosa.avg_pool2d lowering to normalize correctly

Initial version of pooling assumed normalization was accross all elements
equally. TOSA actually requires the noramalization is perform by how
many elements were summed (edges are not artifically dimmer). Updated
the lowering to reflect this change with corresponding tests.

Reviewed By: NatashaKnk

Differential Revision: https://reviews.llvm.org/D102540
The file was modifiedmlir/lib/Conversion/TosaToLinalg/TosaToLinalg.cpp
The file was modifiedmlir/test/Conversion/TosaToLinalg/tosa-to-linalg.mlir