SuccessChanges

Summary

  1. Reapply "[X86] Limit X86InterleavedAccessGroup to handle the same type case only" (details)
  2. [clang][patch] Add support for option -fextend-arguments={32,64}: widen integer arguments to int64 in unprototyped function calls (details)
  3. [lldb] Enable TestCppBitfields on Windows (details)
  4. [AsmParser][SystemZ][z/OS] Introducing HLASM Parser support to AsmParser - Part 1 (details)
  5. [VP] make getFunctionalOpcode return an Optional (details)
  6. Fix lld macho standalone build by including llvm/Config/llvm-config.h instead of llvm/Config/config.h (details)
  7. [mlir][SCF] NFC - Drop SCF EDSC usage (details)
  8. Revert "Do actual DCE in LoopUnroll (try 3)" (details)
  9. [CSSPGO] Overwrite branch weight annotated in previous pass. (details)
  10. Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" (details)
  11. [profile] Skip mmap() if there are no counters (details)
  12. [ScalarEvolution] Remove unused ExitLimit::hasOperand() method (NFC) (details)
  13. [x86] add test check lines to demonstrate FMF propagation failure; NFC (details)
  14. [x86] propagate FMF from x86-specific intrinsic nodes to others during lowering (details)
  15. Revert "Reapply "[clang][deps] Support inferred modules"" (details)
  16. Do actual DCE in LoopUnroll (try 4) (details)
  17. [MCA] llvm-mca MCTargetStreamer segfault fix (details)
  18. [NFCI][Local] removeUnreachableBlocks(): use DeleteDeadBlocks() (details)
  19. [NFCI][Local] MergeBlockIntoPredecessor(): use DeleteDeadBlocks() (details)
  20. [NFCI][Local] TryToSimplifyUncondBranchFromEmptyBlock(): use DeleteDeadBlocks() (details)
  21. [CoverageMapping] Handle gaps in counter IDs for source-based coverage (details)
  22. [MLIR] Update Vector To LLVM conversion to be aware of assume_alignment (details)
Commit 9d09d20448e48c78035c40982646b7b26fee88c3 by pengfei.wang
Reapply "[X86] Limit X86InterleavedAccessGroup to handle the same type case only"

The current implementation assumes the destination type of shuffle is the same as the decomposed ones. Add the check to avoid crush when the condition is not satisfied.

This fixes PR37616.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D102751
The file was modifiedllvm/test/CodeGen/X86/x86-interleaved-access.ll
The file was modifiedllvm/lib/Target/X86/X86InterleavedAccess.cpp
Commit d30dfa86760ced9ac57f676340b34f2247898102 by melanie.blower
[clang][patch] Add support for option -fextend-arguments={32,64}: widen integer arguments to int64 in unprototyped function calls

Reviewed By: Aaron Ballman

Differential Revision: https://reviews.llvm.org/D101640
The file was modifiedclang/include/clang/Basic/LangOptions.def
The file was addedclang/test/CodeGen/extend-arg-64.c
The file was modifiedclang/include/clang/Driver/Options.td
The file was modifiedclang/lib/Basic/Targets/X86.h
The file was modifiedclang/include/clang/Basic/TargetInfo.h
The file was modifiedclang/include/clang/Basic/LangOptions.h
The file was modifiedclang/lib/Driver/ToolChains/Clang.cpp
The file was modifiedclang/lib/Sema/SemaExpr.cpp
The file was addedclang/test/Driver/fextend-args.c
Commit 6c83d4a60b7d243f0674f4381ec72b7c8ec4f2be by weratt
[lldb] Enable TestCppBitfields on Windows

The test works correctly on Windows, the linked bug has been resolved.

Reviewed By: teemperor

Differential Revision: https://reviews.llvm.org/D102769
The file was modifiedlldb/test/API/lang/cpp/bitfields/TestCppBitfields.py
Commit f076da66b9d3c721611de36e43ac1da1607d1abf by anirudh_prasad
[AsmParser][SystemZ][z/OS] Introducing HLASM Parser support to AsmParser - Part 1

- This patch (is one in a series of patches) which introduces HLASM Parser support (for the first parameter of inline asm statements) to LLVM ([[ https://lists.llvm.org/pipermail/llvm-dev/2021-January/147686.html | main RFC here ]])
- This patch in particular introduces HLASM Parser support for Z machine instructions.
- The approach taken here was to subclass `AsmParser`, and make various functions and variables as "protected" wherever appropriate.
- The `HLASMAsmParser` class overrides the `parseStatement` function. Two new private functions `parseAsHLASMLabel` and `parseAsMachineInstruction` are introduced as well.

The general syntax is laid out as follows (more information available in [[ https://www.ibm.com/support/knowledgecenter/SSENW6_1.6.0/com.ibm.hlasm.v1r6.asm/asmr1023.pdf | HLASM V1R6 Language Reference Manual ]] - Chapter 2 - Instruction Statement Format):

```
<TokA><spaces.*><TokB><spaces.*><TokC><spaces.*><TokD>
```

1. TokA is referred to as the Name Entry. This token is optional
2. TokB is referred to as the Operation Entry. This token is mandatory.
3. TokC is referred to as the Operand Entry. This token is mandatory
4. TokD is referred to as the Remarks Entry. This token is optional

- If TokA is provided, then we either parse TokA as a possible comment or as a label (Name Entry), Tok B as the Operation Entry and so on.
- If TokA is not provided (i.e. we have one or more spaces and then the first token), then we will parse the first token (i.e TokB) as a possible Z machine instruction, TokC as the operands to the Z machine instruction and TokD as a possible Remark field
- TokC (Operand Entry), no spaces are allowed between OperandEntries. If a space occurs it is classified as an error.
- TokD if provided is taken as is, and emitted as a comment.

The following additional approach was examined, but not taken:

- Adding custom private only functions to base AsmParser class, and only invoking them for z/OS. While this would eliminate the need for another child class, these private functions would be of non-use to every other target. Similarly, adding any pure virtual functions to the base MCAsmParser class and overriding them in AsmParser would also have the same disadvantage.

Testing:

- This patch doesn't have tests added with it, for the sole reason that MCStreamer Support and Object File support hasn't been added for the z/OS target (yet). Hence, it's not possible generate code outright for the z/OS target. They are in the process of being committed / process of being worked on.

- Any comments / feedback on how to combat this "lack of testing" due to other missing required features is appreciated.

Reviewed By: Kai, uweigand

Differential Revision: https://reviews.llvm.org/D98276
The file was modifiedllvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmInfo.cpp
The file was modifiedllvm/include/llvm/MC/MCAsmInfo.h
The file was modifiedllvm/lib/MC/MCParser/AsmParser.cpp
The file was modifiedllvm/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp
The file was modifiedllvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp
Commit 66963bf3819df4f47bd874a946af058f0c1c4ec0 by simon.moll
[VP] make getFunctionalOpcode return an Optional

The operation of some VP intrinsics do/will not map to regular
instruction opcodes.  Returning 'None' seems more intuitive here than
'Instruction::Call'.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D102778
The file was modifiedllvm/lib/CodeGen/ExpandVectorPredication.cpp
The file was modifiedllvm/unittests/IR/VPIntrinsicTest.cpp
The file was modifiedllvm/lib/IR/IntrinsicInst.cpp
The file was modifiedllvm/include/llvm/IR/IntrinsicInst.h
Commit 9383e9c1e627b49cc1c80c2e6117132734a2fba8 by thakis
Fix lld macho standalone build by including llvm/Config/llvm-config.h instead of llvm/Config/config.h

lld/MachO/Driver.cpp and lld/MachO/SyntheticSections.cpp include
llvm/Config/config.h which doesn't exist when building standalone lld.

This patch replaces llvm/Config/config.h include with llvm/Config/llvm-config.h
just like it is in lld/ELF/Driver.cpp and HAVE_LIBXAR with LLVM_HAVE_LIXAR and
moves LLVM_HAVE_LIBXAR from config.h to llvm-config.h

Also it adds LLVM_HAVE_LIBXAR to LLVMConfig.cmake and links liblldMachO2.so
with XAR_LIB if LLVM_HAVE_LIBXAR is set.

Differential Revision: https://reviews.llvm.org/D102084
The file was modifiedlld/MachO/SyntheticSections.cpp
The file was modifiedllvm/utils/gn/secondary/llvm/include/llvm/Config/BUILD.gn
The file was modifiedllvm/include/llvm/Config/config.h.cmake
The file was modifiedllvm/test/CMakeLists.txt
The file was modifiedllvm/include/llvm/Config/llvm-config.h.cmake
The file was modifiedllvm/test/lit.site.cfg.py.in
The file was modifiedllvm/utils/gn/secondary/llvm/test/BUILD.gn
The file was modifiedlld/tools/lld/CMakeLists.txt
The file was modifiedllvm/tools/llvm-objdump/MachODump.cpp
The file was modifiedllvm/tools/llvm-objdump/CMakeLists.txt
The file was modifiedlld/MachO/Driver.cpp
The file was modifiedlld/MachO/CMakeLists.txt
The file was modifiedlld/test/lit.site.cfg.py.in
The file was modifiedllvm/cmake/config-ix.cmake
The file was modifiedlld/CMakeLists.txt
The file was modifiedllvm/cmake/modules/LLVMConfig.cmake.in
The file was modifiedllvm/utils/gn/secondary/lld/test/BUILD.gn
The file was modifiedlld/test/CMakeLists.txt
Commit 84a880e1e23ebc2ca60e6e1f9e8d0d8db3f9a036 by nicolas.vasilache
[mlir][SCF] NFC - Drop SCF EDSC usage

Drop the SCF dialect EDSC subdirectory and update all uses.

Differential Revision: https://reviews.llvm.org/D102780
The file was modifiedmlir/test/Dialect/Linalg/affine.mlir
The file was modifiedmlir/lib/Dialect/SCF/CMakeLists.txt
The file was removedmlir/include/mlir/Dialect/SCF/EDSC/Intrinsics.h
The file was modifiedmlir/lib/Dialect/Linalg/EDSC/Builders.cpp
The file was modifiedmlir/include/mlir/Dialect/Affine/EDSC/Builders.h
The file was removedmlir/lib/Dialect/SCF/EDSC/Builders.cpp
The file was modifiedmlir/lib/Dialect/GPU/Transforms/MemoryPromotion.cpp
The file was modifiedmlir/include/mlir/EDSC/Builders.h
The file was modifiedmlir/lib/Dialect/Linalg/Utils/Utils.cpp
The file was modifiedmlir/include/mlir/Dialect/Linalg/Utils/Utils.h
The file was removedmlir/include/mlir/Dialect/SCF/EDSC/Builders.h
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/Tiling.cpp
The file was modifiedmlir/test/Dialect/Linalg/loops.mlir
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/Loops.cpp
The file was modifiedmlir/include/mlir/Dialect/MemRef/EDSC/Intrinsics.h
The file was modifiedmlir/include/mlir/Dialect/Affine/EDSC/Intrinsics.h
Commit 517857421d2ffcebc20da2c68862f7a2ddebaa51 by akhuang
Revert "Do actual DCE in LoopUnroll (try 3)"

This reverts commit b6320eeb8622f05e4a5d4c7f5420523357490fca
as it causes clang to assert; see
https://reviews.llvm.org/rGb6320eeb8622f05e4a5d4c7f5420523357490fca.
The file was modifiedllvm/lib/Transforms/Utils/LoopUnroll.cpp
The file was modifiedllvm/test/Transforms/LoopUnroll/unroll-header-exiting-with-phis.ll
The file was modifiedllvm/test/Transforms/LoopUnroll/nonlatchcondbr.ll
The file was modifiedllvm/test/Transforms/LoopUnroll/pr45939-peel-count-and-complete-unroll.ll
The file was removedllvm/test/Transforms/LoopUnroll/dce.ll
The file was modifiedllvm/test/Transforms/LoopUnroll/optsize-loop-size.ll
The file was modifiedllvm/test/Transforms/LoopUnroll/scevunroll.ll
The file was modifiedllvm/test/Transforms/LoopUnroll/unroll-unconditional-latch.ll
The file was modifiedllvm/test/Transforms/LoopUnrollAndJam/unroll-and-jam.ll
The file was modifiedllvm/test/Transforms/LoopUnroll/AArch64/full-unroll-trip-count-upper-bound.ll
The file was modifiedllvm/test/Transforms/LoopUnroll/full-unroll-invariant.ll
Commit 4ca6e37b9825db6d27a0aa2311b6530ac3faf021 by hoy
[CSSPGO] Overwrite branch weight annotated in previous pass.

Sample profile loader can be run in both LTO prelink and postlink. Currently the counts annoation in postilnk doesn't fully overwrite what's done in prelink. I'm adding a switch (`-overwrite-existing-weights=1`) to enable a full overwrite, which includes:

1. Clear old metadata for calls when their parent block has a zero count. This could be caused by prelink code duplication.

2. Clear indirect call metadata if somehow all the rest targets have a sum of zero count.

3. Overwrite branch weight for basic blocks.

With a CS profile, I was seeing #1 and #2 help reduce code size by preventing post-sample ICP and CGSCC inliner working on obsolete metadata, which come from a partial global inlining in prelink.  It's not expected to work well for non-CS case with a less-accurate post-inline count quality.

It's worth calling out that some prelink optimizations can damage counts quality in an irreversible way. One example is the loop rotate optimization. Due to lack of exact loop entry count (profiling can only give loop iteration count and loop exit count), moving one iteration out of the loop body leaves the rest iteration count unknown. We had to turn off prelink loop rotate to achieve a better postlink counts quality. A even better postlink counts quality can be archived by turning off prelink CGSCC inlining which is not context-sensitive.

Reviewed By: wenlei, wmi

Differential Revision: https://reviews.llvm.org/D102537
The file was modifiedllvm/lib/Transforms/IPO/SampleProfile.cpp
The file was modifiedllvm/test/Transforms/SampleProfile/branch.ll
The file was addedllvm/test/Transforms/SampleProfile/pseudo-probe-profile-metadata-2.ll
Commit 84ae1cf8edc00cbf02a7396fef256f39046c1e5b by Jessica Paquette
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known"

Add missing REQUIRES line to
prelegalizer-combiner-icmp-to-true-false-known-bits.
The file was modifiedllvm/include/llvm/Target/GlobalISel/Combine.td
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
The file was addedllvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-icmp-to-true-false-known-bits.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64Combine.td
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i64.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/urem.i64.ll
The file was modifiedllvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
The file was modifiedllvm/test/CodeGen/AArch64/fold-global-offsets.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
Commit 7014a101614367e05cec1ba72a6be07eb173b304 by Vedant Kumar
[profile] Skip mmap() if there are no counters

If there are no counters, an mmap() of the counters section would fail
due to the size argument being too small (EINVAL).

rdar://78175925

Differential Revision: https://reviews.llvm.org/D102735
The file was addedcompiler-rt/test/profile/ContinuousSyncMode/image-with-no-counters.c
The file was modifiedcompiler-rt/lib/profile/InstrProfilingFile.c
Commit b661a55a253f4a1cf5a0fbcb86e5ba7b9fb1387b by nikita.ppv
[ScalarEvolution] Remove unused ExitLimit::hasOperand() method (NFC)

We only use BackedgeTakenInfo::hasOperand().
The file was modifiedllvm/include/llvm/Analysis/ScalarEvolution.h
The file was modifiedllvm/lib/Analysis/ScalarEvolution.cpp
Commit 25207d5f81385e425f67283f7abd10d5f01b7f37 by spatel
[x86] add test check lines to demonstrate FMF propagation failure; NFC
The file was modifiedllvm/test/CodeGen/X86/fmf-propagation.ll
Commit f66ba4cfa7ca312caee5f8f32fcceff592a15acd by spatel
[x86] propagate FMF from x86-specific intrinsic nodes to others during lowering

This is another fast-math-flags failure exposed by D90901.
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was modifiedllvm/test/CodeGen/X86/fmf-propagation.ll
Commit 76b8754d1bba6a8490c0f7e8a9e2fb3d181f0b03 by frgossen
Revert "Reapply "[clang][deps] Support inferred modules""

This reverts commit c98833cdaad01787ea70ecdfabb05a7e142a6671.
The test `ClangScanDeps/modules-inferred-explicit-build.m` creates files
in the current directory.
The file was modifiedclang/test/ClangScanDeps/modules-full.cpp
The file was modifiedclang/lib/Tooling/DependencyScanning/ModuleDepCollector.cpp
The file was removedclang/test/ClangScanDeps/Inputs/modules_inferred_cdb.json
The file was removedclang/test/ClangScanDeps/Inputs/frameworks/Inferred.framework/Frameworks/Sub.framework/Headers/Sub.h
The file was removedclang/test/ClangScanDeps/Inputs/frameworks/Inferred.framework/Headers/Inferred.h
The file was removedclang/test/ClangScanDeps/Inputs/frameworks/System.framework/Headers/System.h
The file was removedclang/test/ClangScanDeps/modules-inferred.m
The file was removedclang/test/ClangScanDeps/modules-inferred-explicit-build.m
The file was removedclang/utils/module-deps-to-rsp.py
The file was removedclang/test/ClangScanDeps/Inputs/frameworks/System.framework/Modules/module.modulemap
The file was removedclang/test/ClangScanDeps/Inputs/frameworks/module.modulemap
Commit 449d14ebd23b80bbc8bb5a1ba7979b0e4092a2fc by listmail
Do actual DCE in LoopUnroll (try 4)

Turns out simplifyLoopIVs sometimes returns a non-dead instruction in it's DeadInsts out param.  I had done a bit of NFC cleanup which was only NFC if simplifyLoopIVs obeyed it's documentation.  I'm simplfy dropping that part of the change.

Commit message from try 3:

Recommitting after fixing a bug found post commit. Amusingly, try 1 had been correct, and by reverting to incorporate last minute review feedback, I introduce the bug. Oops. :)

Original commit message:

The problem was that recursively deleting an instruction can delete instructions beyond the current iterator (via a dead phi), thus invalidating iteration. Test case added in LoopUnroll/dce.ll to cover this case.

LoopUnroll does a limited DCE pass after unrolling, but if you have a chain of dead instructions, it only deletes the last one. Improve the code to recursively delete all trivially dead instructions.

Differential Revision: https://reviews.llvm.org/D102511
The file was modifiedllvm/test/Transforms/LoopUnroll/nonlatchcondbr.ll
The file was modifiedllvm/test/Transforms/LoopUnroll/scevunroll.ll
The file was modifiedllvm/test/Transforms/LoopUnrollAndJam/unroll-and-jam.ll
The file was modifiedllvm/test/Transforms/LoopUnroll/AArch64/full-unroll-trip-count-upper-bound.ll
The file was addedllvm/test/Transforms/LoopUnroll/dce.ll
The file was modifiedllvm/test/Transforms/LoopUnroll/optsize-loop-size.ll
The file was modifiedllvm/lib/Transforms/Utils/LoopUnroll.cpp
The file was modifiedllvm/test/Transforms/LoopUnroll/pr45939-peel-count-and-complete-unroll.ll
The file was modifiedllvm/test/Transforms/LoopUnroll/full-unroll-invariant.ll
The file was modifiedllvm/test/Transforms/LoopUnroll/unroll-header-exiting-with-phis.ll
The file was modifiedllvm/test/Transforms/LoopUnroll/unroll-unconditional-latch.ll
Commit e5d59db46938caf0280f7347e89181f2a7b0749c by andrea.dibiagio
[MCA] llvm-mca MCTargetStreamer segfault fix

In order to create the code regions for llvm-mca to analyze, llvm-mca creates an
AsmCodeRegionGenerator and calls AsmCodeRegionGenerator::parseCodeRegions().
Within this function, both an MCAsmParser and MCTargetAsmParser are created so
that MCAsmParser::Run() can be used to create the code regions for us.

These parser classes were created for llvm-mc so they are designed to emit code
with an MCStreamer and MCTargetStreamer that are expected to be setup and passed
into the MCAsmParser constructor. Because llvm-mca doesn’t want to emit any
code, an MCStreamerWrapper class gets created instead and passed into the
MCAsmParser constructor. This wrapper inherits from MCStreamer and overrides
many of the emit methods to just do nothing. The exception is the
emitInstruction() method which calls Regions.addInstruction(Inst).

This works well and allows llvm-mca to utilize llvm-mc’s MCAsmParser to build
our code regions, however there are a few directives which rely on the
MCTargetStreamer. llvm-mc assumes that the MCStreamer that gets passed into the
MCAsmParser’s constructor has a valid pointer to an MCTargetStreamer. Because
llvm-mca doesn’t setup an MCTargetStreamer, when the parser encounters one of
those directives, a segfault will occur.

In x86, each one of these 7 directives will cause this segfault if they exist in
the input assembly to llvm-mca:

.cv_fpo_proc
.cv_fpo_setframe
.cv_fpo_pushreg
.cv_fpo_stackalloc
.cv_fpo_stackalign
.cv_fpo_endprologue
.cv_fpo_endproc
I haven’t looked at other targets, but I wouldn’t be surprised if some of the
other ones also have certain directives which could result in this same
segfault.

My proposed solution is to simply initialize an MCTargetStreamer after we
initialize the MCStreamerWrapper. The MCTargetStreamer requires an ostream
object, but we don’t actually want any of these directives to be emitted
anywhere, so I use an ostream created with the nulls() function. Since this
needs to happen after the MCStreamerWrapper has been initialized, it needs to
happen within the AsmCodeRegionGenerator::parseCodeRegions() function. The
MCTargetStreamer also needs an MCInstPrinter which is easiest to initialize
within the main() function of llvm-mca. So this MCInstPrinter gets constructed
within main() then passed into the parseCodeRegions() function as a parameter.
(If you feel like it would be appropriate and possible to create the
MCInstPrinter within the parseCodeRegions() function, then feel free to modify
my solution. That would stop us from having to pass it into the function and
would limit its scope / lifetime.)

My solution stops the segfault from happening and still passes all of the
current (expected) llvm-mca tests. I also added a new test for x86 that checks
for this segfault on an input that includes one of the .cv_fpo directives (this
test fails without my solution, but passes with it).

As far as I can tell, all of the functions that I modified are only called from
within llvm-mca so there shouldn’t be any worries about breaking other tools.

Differential Revision: https://reviews.llvm.org/D102709
The file was modifiedllvm/tools/llvm-mca/llvm-mca.cpp
The file was modifiedllvm/tools/llvm-mca/CodeRegionGenerator.h
The file was addedllvm/test/tools/llvm-mca/X86/cv_fpo_directive_no_segfault.s
The file was modifiedllvm/tools/llvm-mca/CodeRegionGenerator.cpp
Commit b0bb2149b3711d5d7c4fd3182a7eac3f8fc17341 by lebedev.ri
[NFCI][Local] removeUnreachableBlocks(): use DeleteDeadBlocks()
The file was modifiedllvm/lib/Transforms/Utils/Local.cpp
Commit c60ca9856c9da19794b0f7b83b3002847e3fc9d9 by lebedev.ri
[NFCI][Local] MergeBlockIntoPredecessor(): use DeleteDeadBlocks()
The file was modifiedllvm/lib/Transforms/Utils/BasicBlockUtils.cpp
Commit 40fb4eeff9ee59382f6bc37c622bde99c2a9a02a by lebedev.ri
[NFCI][Local] TryToSimplifyUncondBranchFromEmptyBlock(): use DeleteDeadBlocks()
The file was modifiedllvm/lib/Transforms/Utils/Local.cpp
Commit e4274cfe06fe48ed8f0c9f965c8b519e30433bf8 by pirama
[CoverageMapping] Handle gaps in counter IDs for source-based coverage

For source-based coverage, the frontend sets the counter IDs and the
constraints of counter IDs is not defined.  For e.g., the Rust frontend
until recently had a reserved counter #0
(https://github.com/rust-lang/rust/pull/83774).  Rust coverage
instrumentation also creates counters on edges in addition to basic
blocks.  Some functions may have more counters than regions.

This breaks an assumption in CoverageMapping.cpp where the number of
counters in a function is assumed to be bounded by the number of
regions:
  Counts.assign(Record.MappingRegions.size(), 0);

This assumption causes CounterMappingContext::evaluate() to fail since
there are not enough counter values created in the above call to
`Counts.assign`.  Consequently, some uncovered functions are not
reported in coverage reports.

This change walks a Function's CoverageMappingRecord to find the maximum
counter ID, and uses it to initialize the counter array when instrprof
records are missing for a function in sparse profiles.

Differential Revision: https://reviews.llvm.org/D101780
The file was modifiedllvm/include/llvm/ProfileData/Coverage/CoverageMapping.h
The file was modifiedllvm/lib/ProfileData/Coverage/CoverageMapping.cpp
The file was modifiedllvm/unittests/ProfileData/CoverageMappingTest.cpp
Commit 29a50c5864ddab283c1ff38694fb5926ce37b39a by stephen.neuendorffer
[MLIR] Update Vector To LLVM conversion to be aware of assume_alignment

vector.transfer_read and vector.transfer_write operations are converted
to llvm intrinsics with specific alignment information, however there
doesn't seem to be a way in llvm to take information from llvm.assume
intrinsics and change this alignment information.  In any
event, due the to the structure of the llvm.assume instrinsic, applying
this information at the llvm level is more cumbersome.  Instead, let's
generate the masked vector load and store instrinsic with the right
alignment information from MLIR in the first place.  Since
we're bothering to do this, lets just emit the proper alignment for
loads, stores, scatter, and gather ops too.

Differential Revision: https://reviews.llvm.org/D100444
The file was modifiedmlir/test/Conversion/VectorToLLVM/vector-to-llvm.mlir
The file was modifiedmlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp