SuccessChanges

Summary

  1. [libcxx][gardening] Re-order includes across libcxx. (details)
  2. [Verifier] Move some atomicrmw/cmpxchg checks to instruction creation (details)
  3. [LLD][COFF] PR49068: Include the IMAGE_REL_BASED_HIGHLOW relocation base type when the machine is 64 bits and the relocation type is ADDR32 (details)
  4. [OpenMP] libomp: move warnings to after library initialization (details)
  5. RISCV: add a few deprecated aliases for CSRs (details)
  6. [clang] Don't pass multiple backend options if mixing -mimplicit-it and -Wa,-mimplicit-it (details)
  7. [NFC][sanitizer] Fix android bot after D102815 (details)
  8. [NFC][HIP] fix comments in __clang_hip_cmath.h (details)
  9. [compiler-rt][profile] Explicitly specify PROFILE_SOURCES extensions. NFC (details)
  10. [lld][WebAssembly] Fix for PIC output + TLS + non-shared-memory (details)
  11. [mlir][docs] Add memref and sparse_tensor to Passes.md (details)
Commit 8110a7316401b30632d7efb0211f6059243260ac by zoecarver
[libcxx][gardening] Re-order includes across libcxx.

This commit alphabetizes all includes in libcxx. This is a NFC.

This can also serve as a pseudo "announcement" for how we should order these headers going forward (note: double underscores go before other headers).

Differential Revision: https://reviews.llvm.org/D102941
The file was modifiedlibcxx/include/__ranges/data.h
The file was modifiedlibcxx/include/__ranges/size.h
The file was modifiedlibcxx/include/__support/win32/limits_msvc_win32.h
The file was modifiedlibcxx/include/__iterator/iterator_traits.h
The file was modifiedlibcxx/include/__support/ibm/xlocale.h
The file was modifiedlibcxx/include/__iterator/concepts.h
The file was modifiedlibcxx/include/__support/win32/locale_win32.h
The file was modifiedlibcxx/include/__memory/shared_ptr.h
The file was modifiedlibcxx/include/__support/openbsd/xlocale.h
The file was modifiedlibcxx/include/__bsd_locale_fallbacks.h
Commit 7a29a1230148385e93493891cc7eb7f7f3b4a6cb by aeubanks
[Verifier] Move some atomicrmw/cmpxchg checks to instruction creation

These checks already exist as asserts when creating the corresponding
instruction. Anybody creating these instructions already need to take
care to not break these checks.

Move the checks for success/failure ordering in cmpxchg from the
verifier to the LLParser and BitcodeReader plus an assert.

Add some tests for cmpxchg ordering. The .bc files are created from the
.ll files with an llvm-as with these checks disabled.

Reviewed By: dblaikie

Differential Revision: https://reviews.llvm.org/D102803
The file was addedllvm/test/Assembler/cmpxchg-ordering-3.ll
The file was modifiedllvm/test/Bitcode/invalid.test
The file was addedllvm/test/Assembler/cmpxchg-ordering-4.ll
The file was modifiedllvm/lib/AsmParser/LLParser.cpp
The file was addedllvm/test/Bitcode/Inputs/invalid-cmpxchg-ordering.bc
The file was modifiedllvm/include/llvm/IR/Instructions.h
The file was modifiedllvm/lib/IR/Verifier.cpp
The file was addedllvm/test/Assembler/cmpxchg-ordering-2.ll
The file was addedllvm/test/Assembler/cmpxchg-ordering.ll
The file was addedllvm/test/Bitcode/Inputs/invalid-cmpxchg-ordering-4.bc
The file was addedllvm/test/Bitcode/Inputs/invalid-cmpxchg-ordering-2.bc
The file was addedllvm/test/Bitcode/Inputs/invalid-cmpxchg-ordering-3.bc
The file was modifiedllvm/lib/IR/Instructions.cpp
The file was modifiedllvm/lib/Bitcode/Reader/BitcodeReader.cpp
Commit 4fb131b49795ea11f7f56af1f4896fb6996faf0f by martin
[LLD][COFF] PR49068: Include the IMAGE_REL_BASED_HIGHLOW relocation base type when the machine is 64 bits and the relocation type is ADDR32

The COFF driver produces an ABSOLUTE relocation base for an ADDR32
relocation type and the system is 64 bits (machine=AMD64). The
relocation information won't be added in the output and could
produce an incorrect address access during run-time. This change
set checks if the relocation type is IMAGE_REL_AMD64_ADDR32 and
if so, adds the relocated symbol as IMAGE_REL_BASED_HIGHLOW base.

Differential Revision: https://reviews.llvm.org/D96619
The file was modifiedlld/COFF/Chunks.cpp
The file was addedlld/test/COFF/reloc-x64-add32.s
Commit aa6e7e8da8f5a2706f0b330718df203b3650408e by Andrey.Churbanov
[OpenMP] libomp: move warnings to after library initialization

Warnings on deprecated api cannot be suppressed if the library is not initialized.
With this change it is possible to set KMP_WARNINGS=false to suppress the warnings.

Differential Revision: https://reviews.llvm.org/D102676
The file was modifiedopenmp/runtime/src/kmp_ftn_entry.h
The file was addedopenmp/runtime/test/api/omp_deprecated.c
Commit 6c6b3e3afe7cbf43d6ab2aa780367e6942f1b6b4 by Saleem Abdulrasool
RISCV: add a few deprecated aliases for CSRs

This adds the {s,u,m}badaddr CSR aliases as well as the sptbr alias.
These are for compatibility with binutils.  Furthermore, these are used
by the RISC-V Proxy Kernel and are required to enable building the Proxy
Kernel with the LLVM IAS.

The aliases here are deprecated.  These are being introduced in order to
provide a compatibility story for the existing GNU toolchain, which
still supports the deprecated spelling in the assembler.  However, in
order to encourage the migration of existing coding, we provide warnings
indicating that the aliased CSRs are deprecated and should be replaced.

Differential Revision: https://reviews.llvm.org/D101919
Reviewed By: Craig Topper
The file was addedllvm/test/MC/RISCV/deprecated-csr-names.s
The file was modifiedllvm/lib/Target/RISCV/RISCVSystemOperands.td
The file was modifiedllvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
The file was modifiedllvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
Commit 4468e5b8999291cc84b78f33f207dcd0e58146bc by martin
[clang] Don't pass multiple backend options if mixing -mimplicit-it and -Wa,-mimplicit-it

If multiple instances of the -arm-implicit-it option is passed to
the backend, it errors out.

Also fix cases where there are multiple -Wa,-mimplicit-it; the existing
tests indicate that the last one specified takes effect, while in
practice it passed double options, which didn't work as intended.

Differential Revision: https://reviews.llvm.org/D102812
The file was modifiedclang/lib/Driver/ToolChains/Clang.cpp
The file was modifiedclang/test/Driver/arm-target-as-mimplicit-it.s
Commit f50b87e9ef42efe80e2b3364df848d102075dd11 by Vitaly Buka
[NFC][sanitizer] Fix android bot after D102815

https://lab.llvm.org/buildbot/#/builders/77/builds/6519
The file was modifiedcompiler-rt/lib/sanitizer_common/tests/CMakeLists.txt
The file was modifiedcompiler-rt/lib/sanitizer_common/tests/sanitizer_stacktrace_test.cpp
Commit 91dfd68e90156dab3cbf11c9ae677cf60b2df65c by Yaxun.Liu
[NFC][HIP] fix comments in __clang_hip_cmath.h
The file was modifiedclang/lib/Headers/__clang_hip_cmath.h
Commit cc9c895d8844d69a6962a5a5952034a9e466b2f0 by jonathan_roelofs
[compiler-rt][profile] Explicitly specify PROFILE_SOURCES extensions. NFC
The file was modifiedcompiler-rt/cmake/Modules/CompilerRTDarwinUtils.cmake
Commit 8544b40b6e1d4e34650af66e25102ebcdf360e62 by sbc
[lld][WebAssembly] Fix for PIC output + TLS + non-shared-memory

Prior to this change build with `-shared/-pie` and using TLS (but
without -shared-memory) would hit this assert:

  "Currenly only a single data segment is supported in PIC mode"

This is because we were not including TLS data when merging data
segments.  However, when we build without shared-memory (i.e.  without
threads) we effectively lower away TLS into a normal active data
segment.. so we were ending up with two active data segments: the merged
data, and the lowered TLS data.

To fix this problem we can instead avoid combining data segments at
all when running in shared memory mode (because in this case all
segment initialization is passive).  And then in non-shared memory
mode we know that TLS has been lowered and therefore we can can
and should combine all segments.

So with this new behavior we have two different modes:

1. With shared memory / mutli-threaded: Never combine data segments
   since it is not necessary.  (All data segments as passive already).

2. Wihout shared memory / single-threaded: Combine *all* data segments
   since we treat TLS as normal data.  (We end up with a single
   active data segment).

Differential Revision: https://reviews.llvm.org/D102937
The file was modifiedlld/wasm/OutputSections.cpp
The file was modifiedlld/test/wasm/data-segments.ll
The file was modifiedlld/wasm/Relocations.cpp
The file was modifiedlld/wasm/Writer.cpp
The file was modifiedlld/test/wasm/relocation-bad-tls.s
The file was addedlld/test/wasm/tls-non-shared-memory.s
The file was removedlld/test/wasm/tls-no-shared.s
Commit ab3cd2601bac99b26952c6f1015387d60800d2e2 by youngar17
[mlir][docs] Add memref and sparse_tensor to Passes.md

These pass documents belong on the main pass page, and not generated as
top level pages.

Reviewed By: rriddle

Differential Revision: https://reviews.llvm.org/D102947
The file was modifiedmlir/docs/Passes.md