Changes

Summary

  1. [OpenCL] Add clang extension for bit-fields. (details)
  2. [AArch64][SVE] Improve codegen for fixed length vector concat (details)
  3. [AArch64][SVE] Add fixed length codegen for FP_ROUND/FP_EXTEND (details)
  4. [OpenCL] Fix test by adding SPIR triple (details)
  5. [VPlan] Add mayReadOrWriteMemory & friends. (details)
  6. [VectorCombine] Fix load extract scalarization tests with assumes. (details)
  7. [CostModel][X86] Improve accuracy of vector non-uniform shift costs on XOP/AVX2 targets (details)
  8. [OpenCL][Docs] Minor update to OpenCL 3.0 (details)
  9. [lldb] Reland "Fix UB in half2float" to fix the ubsan bot. (details)
Commit 237c6924bd46ec0e33da71f9616caf9bf9965b23 by anastasia.stulova
[OpenCL] Add clang extension for bit-fields.

Allow use of bit-fields as a clang extension
in OpenCL. The extension can be enabled using
pragma directives.

This fixes PR45339!

Differential Revision: https://reviews.llvm.org/D101843
The file was modifiedclang/lib/Sema/SemaDecl.cpp
The file was modifiedclang/test/Misc/amdgcn.languageOptsOpenCL.cl
The file was modifiedclang/test/Misc/nvptx.languageOptsOpenCL.cl
The file was modifiedclang/test/Misc/r600.languageOptsOpenCL.cl
The file was modifiedclang/docs/LanguageExtensions.rst
The file was modifiedclang/test/SemaOpenCL/unsupported.cl
The file was modifiedclang/include/clang/Basic/OpenCLExtensions.def
The file was modifiedclang/lib/Basic/Targets/AMDGPU.h
The file was modifiedclang/lib/Basic/Targets/NVPTX.h
Commit 4bc14be259672257d5c05c58a0ba604002698e93 by bradley.smith
[AArch64][SVE] Improve codegen for fixed length vector concat

Differential Revision: https://reviews.llvm.org/D102498
The file was addedllvm/test/CodeGen/AArch64/sve-fixed-length-concat.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.h
The file was modifiedllvm/test/CodeGen/AArch64/sve-fixed-length-shuffles.ll
Commit e40513252a2598c2a88366e9466de53edc5a5a51 by bradley.smith
[AArch64][SVE] Add fixed length codegen for FP_ROUND/FP_EXTEND

Depends on D102498

Differential Revision: https://reviews.llvm.org/D102607
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.h
The file was modifiedllvm/test/CodeGen/AArch64/sve-fixed-length-fp-converts.ll
The file was addedllvm/test/CodeGen/AArch64/sve-fixed-length-fp-extend-trunc.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp
Commit 626e9641a2f5fde638b86d4e043f82fc58b908f8 by anastasia.stulova
[OpenCL] Fix test by adding SPIR triple
The file was modifiedclang/test/SemaOpenCL/unsupported.cl
Commit e9d97d7d9d904bc075565197b560e8424ac6a0dc by flo
[VPlan] Add mayReadOrWriteMemory & friends.

This patch adds initial implementation of mayReadOrWriteMemory,
mayReadFromMemory and mayWriteToMemory to VPRecipeBase.

Used by D100258.
The file was modifiedllvm/lib/Transforms/Vectorize/VPlan.cpp
The file was modifiedllvm/lib/Transforms/Vectorize/VPlan.h
The file was modifiedllvm/unittests/Transforms/Vectorize/VPlanTest.cpp
Commit d251d6f8128bbc38378a69e7fec405f0935a89de by flo
[VectorCombine] Fix load extract scalarization tests with assumes.

The input IR for @load_extract_idx_var_i64_known_valid_by_assume
and @load_extract_idx_var_i64_not_known_valid_by_assume_after_load
has been swapped.

This patch fixes the test so that @load_extract_idx_var_i64_known_valid_by_assume
has the assume before the load and the other test has it after.
The file was modifiedllvm/test/Transforms/VectorCombine/AArch64/load-extractelement-scalarization.ll
Commit 1ad4f887bd7692a9e63fb42586f0ece366f2fe01 by llvm-dev
[CostModel][X86] Improve accuracy of vector non-uniform shift costs on XOP/AVX2 targets

By llvm-mca analysis, Haswell/Broadwell has a non-uniform vector shift recip-throughput cost of the AVX2 targets at 2 for both 128 and 256-bit vectors - XOP capable targets have better 128-bit vector shifts so improve the fallback in those cases.
The file was modifiedllvm/test/Analysis/CostModel/X86/vshift-ashr-cost-inseltpoison.ll
The file was modifiedllvm/test/Transforms/VectorCombine/X86/insert-binop-with-constant.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/fshl.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/vshift-ashr-cost.ll
The file was modifiedllvm/lib/Target/X86/X86TargetTransformInfo.cpp
The file was modifiedllvm/test/Analysis/CostModel/X86/vshift-shl-cost-inseltpoison.ll
The file was modifiedllvm/test/Transforms/VectorCombine/X86/insert-binop-with-constant-inseltpoison.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/vshift-shl-cost.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/div.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/rem.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/vshift-lshr-cost-inseltpoison.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/vshift-lshr-cost.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/fshr.ll
Commit 5ccc79dc38b2df18cca5a9b4d66dcd4603f948e9 by anastasia.stulova
[OpenCL][Docs] Minor update to OpenCL 3.0
The file was modifiedclang/docs/OpenCLSupport.rst
Commit 42a9c0c80c23fa0de3e3b00fef0dfa6d85e18e55 by Raphael Isemann
[lldb] Reland "Fix UB in half2float" to fix the ubsan bot.

This relands part of the UB fix in 4b074b49be206306330076b9fa40632ef1960823.
The original commit also added some additional tests that uncovered some
other issues (see D102845). I landed all the passing tests in
48780527dd6820698f3537f5ebf76499030ee349 and this patch is now just fixing
the UB in half2float. See D102846 for a proposed rewrite of the function.

Original commit message:

  The added DumpDataExtractorTest uncovered that this is lshifting a negative
  integer which upsets ubsan and breaks the sanitizer bot. This patch just
  changes the variable we shift to be unsigned.
The file was modifiedlldb/source/Core/DumpDataExtractor.cpp