SuccessChanges

Summary

  1. [RISCV] Teach vsetvli insertion to use vsetvl x0, x0 form when we can tell that VLMAX and AVL haven't changed. (details)
  2. [CostModel][X86] Improve accuracy of sext/zext to 256-bit vector costs on AVX1 targets (details)
  3. [NFC][X86][Codegen] Re-autogenerate check lines in a few tests to remove noise from future changes (details)
  4. Revert "[libc++] NFC: Parenthesize expression to satisfy GCC 11" (details)
  5. [NFC][scudo] Rename internal function (details)
  6. MC: mark `dump` with `LLVM_DUMP_METHOD` (details)
  7. [mlir] AsyncRefCounting: check that LivenessBlockInfo is not nullptr (details)
  8. [mlir] Update cmake variable post D102976 (details)
  9. [NFC][scudo] Check zeros on smaller allocations (details)
  10. [libc++] NFC: Refactor raw_storage_iterator test to use UNSUPPORTED markup (details)
  11. [RISCV] Add a test showing missed opportunity to avoid a vsetvli in a loop. (details)
  12. [lldb][intel-pt] Remove old plugin (details)
  13. [mlir:Async] Convert assertions to async errors only inside async functions (details)
Commit 527cd013144d3fb3b578640721530fa2d2da4da9 by craig.topper
[RISCV] Teach vsetvli insertion to use vsetvl x0, x0 form when we can tell that VLMAX and AVL haven't changed.

This can help avoid needing a virtual register for the vsetvl output
when the AVL is X0. For other register AVLs it can shorter the live
range of the AVL register if it isn't needed later.

There's probably no advantage when AVL is a 5 bit immediate that
can use vsetivli. But do it anyway for consistency.

Reviewed By: rogfer01

Differential Revision: https://reviews.llvm.org/D103215
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vxor-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmsgeu-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmsgt-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmfne-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmflt-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vssubu-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmfge-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmadd-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmsltu-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-extload-truncstore.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmfgt-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmfne-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmsle-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmsgtu-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmsge-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vnmsub-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vdiv-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmaxu-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/extload-truncstore.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmax-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vdivu-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vitofp-sdnode.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmsleu-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmfeq-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmin-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmulhsu-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vtruncs-sdnode-rv32.ll
The file was modifiedllvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vadd-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/setcc-fp-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vlseg-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmfgt-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmulhu-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/setcc-fp-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfptrunc-sdnode.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vasubu-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vrem-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-conv.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmseq-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmulh-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmsgt-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmslt-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vaadd-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vasub-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmsne-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vsub-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vaaddu-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmfeq-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmsltu-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/named-vector-shuffle-reverse.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vlsseg-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmsge-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vssub-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-exttrunc.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmslt-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vsadd-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/zvlsseg-zero-vl.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vremu-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmflt-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vnmsac-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vtruncs-sdnode-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vlsseg-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmsgeu-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vsaddu-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vor-rv32.ll
The file was modifiedllvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-i1.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmacc-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmsle-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/saddo-sdnode.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmfle-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfcopysign-sdnode.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfptoi-sdnode.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmfle-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfpext-sdnode.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vminu-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmsne-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/interleave-crash.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmsleu-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vand-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vlseg-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmsgtu-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmseq-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmul-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vsmul-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vrsub-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/legalize-scalable-vectortype.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmfge-rv64.ll
Commit 90d25808c4207d22eec27f2677b7e658308dd2f9 by llvm-dev
[CostModel][X86] Improve accuracy of sext/zext to 256-bit vector costs on AVX1 targets

Determined from llvm-mca analysis (btver2 vs bdver2 vs sandybridge), the split+extends+concat sequence on AVX1 capable targets are cheaper than the #ops that the cost was previously based on.
The file was modifiedllvm/test/Analysis/CostModel/X86/arith.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/reduce-mul.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/arith-fix.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/cast.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/masked-intrinsic-cost-inseltpoison.ll
The file was modifiedllvm/lib/Target/X86/X86TargetTransformInfo.cpp
The file was modifiedllvm/test/Analysis/CostModel/X86/arith-overflow.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/extend.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/rem.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/masked-intrinsic-cost.ll
Commit bafbec8535690d625f1ed770db77f762a825ac0b by lebedev.ri
[NFC][X86][Codegen] Re-autogenerate check lines in a few tests to remove noise from future changes
The file was modifiedllvm/test/CodeGen/X86/combine-srl.ll
The file was modifiedllvm/test/CodeGen/X86/shuffle-vs-trunc-256.ll
The file was modifiedllvm/test/CodeGen/X86/vector-trunc-packus.ll
The file was modifiedllvm/test/CodeGen/X86/vector-trunc-math.ll
The file was modifiedllvm/test/CodeGen/X86/avx2-conversions.ll
The file was modifiedllvm/test/CodeGen/X86/vector-shuffle-256-v16.ll
The file was modifiedllvm/test/CodeGen/X86/vector-trunc-usat.ll
The file was modifiedllvm/test/CodeGen/X86/vector-trunc-ssat.ll
The file was modifiedllvm/test/CodeGen/X86/psubus.ll
The file was modifiedllvm/test/CodeGen/X86/vector-trunc.ll
The file was modifiedllvm/test/CodeGen/X86/vector-shuffle-256-v32.ll
The file was modifiedllvm/test/CodeGen/X86/combine-shl.ll
The file was modifiedllvm/test/CodeGen/X86/oddshuffles.ll
The file was modifiedllvm/test/CodeGen/X86/vector-shuffle-combining.ll
The file was modifiedllvm/test/CodeGen/X86/combine-sra.ll
Commit b6399e85d80d2bea522e4bce1c8c3744e45673e2 by Louis Dionne
Revert "[libc++] NFC: Parenthesize expression to satisfy GCC 11"

That fix was actually incorrect and caused tests to start failing.
The file was modifiedlibcxx/test/std/iterators/iterator.primitives/range.iter.ops/range.iter.ops.next/check_round_trip.h
Commit eb69763ad8ea18ef1b0d739847da0be4ab099d51 by Vitaly Buka
[NFC][scudo] Rename internal function
The file was modifiedcompiler-rt/lib/scudo/standalone/linux.cpp
Commit 4cc5a971010efd48c60820b17c8de8ed086aa45f by Saleem Abdulrasool
MC: mark `dump` with `LLVM_DUMP_METHOD`

Mark the `ELFRelocationEntry::dump` method as `LLVM_DUMP_METHOD` to
annotate it properly as used to prevent the function being dead stripped
away.  This allows use of `dump` in the debugger.  This is purely to
improve the developer experience.
The file was modifiedllvm/include/llvm/MC/MCELFObjectWriter.h
Commit 9136b7d075d26a04db9dfed43c37e4c05cd3ccff by ezhulenev
[mlir] AsyncRefCounting: check that LivenessBlockInfo is not nullptr

Differential Revision: https://reviews.llvm.org/D103270
The file was modifiedmlir/lib/Dialect/Async/Transforms/AsyncRuntimeRefCounting.cpp
Commit 5618a5a0594403bc8a22b60e06abd7f9d1e57afc by jpienaar
[mlir] Update cmake variable post D102976
The file was modifiedmlir/tools/mlir-vulkan-runner/CMakeLists.txt
Commit c261edb277020471b7670a8b2f826efc73c5d941 by Vitaly Buka
[NFC][scudo] Check zeros on smaller allocations

1Tb counting was the slowest test under the QEMU with MTE.
The file was modifiedcompiler-rt/lib/scudo/standalone/tests/common_test.cpp
Commit 8d7d7f340ea0202cedddc786b484048da4bbc767 by Louis Dionne
[libc++] NFC: Refactor raw_storage_iterator test to use UNSUPPORTED markup

The test would previously disable itself using `#if TEST_STD_VER` instead
of using UNSUPPORTED markup.
The file was modifiedlibcxx/test/std/utilities/memory/storage.iterator/raw_storage_iterator.base.pass.cpp
Commit d7ae2438b9bd062159fa9bfa8e4db2b8a0d66e38 by craig.topper
[RISCV] Add a test showing missed opportunity to avoid a vsetvli in a loop.

This is another case we need to look through a phi to prove.
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll
Commit 32bacb74107e45cdcedaf3bb2be11bd6e3015390 by walter erquinigo
[lldb][intel-pt] Remove old plugin

Now that LLDB proper has built-in support for intel-pt traces, we can remove the old plugin written by Intel. It has less features and it's hard to work with.

As a test, I ran "ninja lldbIntelFeatures" and it worked.

Differential Revision: https://reviews.llvm.org/D102866
The file was modifiedlldb/tools/intel-features/CMakeLists.txt
The file was removedlldb/tools/intel-features/intel-pt/PTDecoder.h
The file was removedlldb/tools/intel-features/intel-pt/interface/PTDecoder.i
The file was modifiedlldb/tools/intel-features/cli-wrapper.cpp
The file was removedlldb/tools/intel-features/intel-pt/README_CLI.txt
The file was removedlldb/tools/intel-features/intel-pt/cli-wrapper-pt.cpp
The file was removedlldb/tools/intel-features/intel-pt/PTDecoder.cpp
The file was removedlldb/tools/intel-features/scripts/CMakeLists.txt
The file was removedlldb/tools/intel-features/scripts/lldb-intel-features.swig
The file was removedlldb/tools/intel-features/intel-pt/Decoder.cpp
The file was removedlldb/tools/intel-features/intel-pt/Decoder.h
The file was removedlldb/tools/intel-features/intel-pt/CMakeLists.txt
The file was removedlldb/tools/intel-features/scripts/python-typemaps.txt
The file was removedlldb/tools/intel-features/intel-pt/README_TOOL.txt
The file was modifiedlldb/tools/intel-features/README.txt
The file was removedlldb/tools/intel-features/intel-pt/cli-wrapper-pt.h
Commit 8f23fac4da254e8cd2a3160a4fa029613a284ebe by ezhulenev
[mlir:Async] Convert assertions to async errors only inside async functions

Differential Revision: https://reviews.llvm.org/D103278
The file was modifiedmlir/lib/Dialect/Async/Transforms/AsyncToAsyncRuntime.cpp