Changes

Summary

[libcxx] [test] Add UNSUPPORTED: msvc in a couple verify.cpp tests (details)
[LangRef] update according to unwinding support in inline asm (details)
[mlir] Support permutation maps in vector transfer op folder (details)
[mlir][NFC] Remove illegal TanhOp in LLVMConversionTarget (details)
[WebAssembly][CodeGen] IR support for WebAssembly local variables (details)
[clang] Add support for the "abstract" contextual keyword of MSVC (details)
Revert "[WebAssembly][CodeGen] IR support for WebAssembly local variables" (details)
[clang] NFC: split HeaderMapTest to have re-usable header map implementation for testing (details)
[RISCV] Support vector conversions between fp and i1 (details)
[lldb][NFC] Remove unused var in SBDebugger::GetInternalVariableValue (details)
[DSE] Remove stores in the same loop iteration (details)
[InsCombine] Fix a few remaining vec transforms to use poison instead of undef (details)
[RISCV] Scale scalably-typed split argument offsets by VSCALE (details)
[LiveDebugVariables] Stop trimming locations of non-inlined vars (details)

Commit 7d7b72bad7ff1fc22c79d535826de43452f3379d by martin [libcxx] [test] Add UNSUPPORTED: msvc in a couple verify.cpp tests Due to issues with the detection of the clang-verify feature, these tests have been skipped in the Windows CI configuration so far. Differential Revision: https://reviews.llvm.org/D103308
	libcxx/test/std/language.support/cmp/cmp.categories.pre/zero_type.verify.cpp
	libcxx/test/std/utilities/meta/meta.trans/meta.trans.other/underlying_type.fail.cpp
Commit 22f635b1b31a6bee1b0b8df58d5c8207c835b216 by amanieu [LangRef] update according to unwinding support in inline asm https://reviews.llvm.org/D95745 introduced a new `unwind` keyword for inline assembler expressions. Inline asms marked with the `unwind` keyword allows stack unwinding from inline assembly because the compiler emits unwinding information ("around" the inline asm) as it would for calls/invokes. Unwinding the stack from within non-unwind inline asm may cause UB. Reviewed By: Amanieu Differential Revision: https://reviews.llvm.org/D102642
	llvm/docs/LangRef.rst
Commit 2bc8ffa8afabeaf1cc97640419c1c2a926265170 by springerm [mlir] Support permutation maps in vector transfer op folder Fold away in_bounds attribute even if the transfer op has a non-identity permutation map. Differential Revision: https://reviews.llvm.org/D103133
	mlir/test/Dialect/Linalg/vectorization.mlir
	mlir/lib/Dialect/Vector/VectorOps.cpp
Commit 2290a80b4dcbeb230ea47ea59b00205ccefbaa96 by tpopp [mlir][NFC] Remove illegal TanhOp in LLVMConversionTarget No tests fail and this seems to be technical debt from when the math dialect was created. This should not be there as it prevents users from configuring their converion target freely and results in unexpected behavior on seemingly unrelated ops. Differential Revision: https://reviews.llvm.org/D103388
	mlir/lib/Conversion/StandardToLLVM/StandardToLLVM.cpp
Commit bf35f4af51cddd743435bb6b94a45592c967891a by wingo [WebAssembly][CodeGen] IR support for WebAssembly local variables This patch adds TargetStackID::WasmLocal. This stack holds locations of values that are only addressable by name -- not via a pointer to memory. For the WebAssembly target, these objects are lowered to WebAssembly local variables, which are managed by the WebAssembly run-time and are not addressable by linear memory. For the WebAssembly target IR indicates that an AllocaInst should be put on TargetStackID::WasmLocal by putting it in the non-integral address space WASM_ADDRESS_SPACE_WASM_VAR, with value 1. SROA will mostly lift these allocations to SSA locals, but any alloca that reaches instruction selection (usually in non-optimized builds) will be assigned the new TargetStackID there. Loads and stores to those values are transformed to new WebAssemblyISD::LOCAL_GET / WebAssemblyISD::LOCAL_SET nodes, which then lower to the type-specific LOCAL_GET_I32 etc instructions via tablegen patterns. Differential Revision: https://reviews.llvm.org/D101140
	llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.td
	llvm/include/llvm/CodeGen/MIRYamlMapping.h
	llvm/include/llvm/CodeGen/TargetFrameLowering.h
	llvm/lib/Target/WebAssembly/WebAssemblyExplicitLocals.cpp
	llvm/lib/Target/WebAssembly/WebAssemblyFrameLowering.cpp
	llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
	llvm/lib/Target/WebAssembly/Utils/WebAssemblyUtilities.h
	llvm/test/CodeGen/WebAssembly/ir-locals.ll
	llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
	llvm/test/CodeGen/WebAssembly/ir-locals-stackid.ll
	llvm/lib/Target/WebAssembly/WebAssemblyISD.def
	llvm/lib/Target/WebAssembly/WebAssemblyISelDAGToDAG.cpp
	llvm/lib/Target/WebAssembly/Utils/WebAssemblyUtilities.cpp
	llvm/lib/Target/WebAssembly/WebAssemblyFrameLowering.h
	llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
Commit 818338add77411f5e9713247ea66142f332ef350 by hans [clang] Add support for the "abstract" contextual keyword of MSVC https://docs.microsoft.com/en-us/cpp/extensions/abstract-cpp-component-extensions?view=msvc-160 Note: like the already supported "sealed" keyword, the "abstract" keyword is supported by MSVC by default. Differential revision: https://reviews.llvm.org/D102517
	clang/lib/Sema/SemaDecl.cpp
	clang/test/SemaCXX/MicrosoftExtensions.cpp
	clang/include/clang/Parse/Parser.h
	clang/lib/Parse/ParseDeclCXX.cpp
	clang/lib/Sema/DeclSpec.cpp
	clang/include/clang/Basic/DiagnosticParseKinds.td
	clang/include/clang/Sema/DeclSpec.h
	clang/include/clang/AST/DeclCXX.h
	clang/include/clang/Sema/Sema.h
	clang/include/clang/Basic/DiagnosticGroups.td
Commit bc1ad6e3c49dacea862ca6fa44297c64bb053ad8 by wingo Revert "[WebAssembly][CodeGen] IR support for WebAssembly local variables" This reverts commit bf35f4af51cddd743435bb6b94a45592c967891a. There was an error in a shared-library build.
	llvm/lib/Target/WebAssembly/Utils/WebAssemblyUtilities.cpp
	llvm/lib/Target/WebAssembly/Utils/WebAssemblyUtilities.h
	llvm/lib/Target/WebAssembly/WebAssemblyISD.def
	llvm/include/llvm/CodeGen/TargetFrameLowering.h
	llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.td
	llvm/test/CodeGen/WebAssembly/ir-locals-stackid.ll
	llvm/lib/Target/WebAssembly/WebAssemblyExplicitLocals.cpp
	llvm/lib/Target/WebAssembly/WebAssemblyFrameLowering.cpp
	llvm/lib/Target/WebAssembly/WebAssemblyFrameLowering.h
	llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
	llvm/include/llvm/CodeGen/MIRYamlMapping.h
	llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
	llvm/test/CodeGen/WebAssembly/ir-locals.ll
	llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
	llvm/lib/Target/WebAssembly/WebAssemblyISelDAGToDAG.cpp
Commit 37b530a2ea8bdc28a22a3f8ca701455fb7febdea by dmitry.polukhin [clang] NFC: split HeaderMapTest to have re-usable header map implementation for testing NFC changes required for https://reviews.llvm.org/D103142 Test Plan: check-clang Differential Revision: https://reviews.llvm.org/D103229
	clang/unittests/Lex/HeaderMapTestUtils.h
	clang/unittests/Lex/HeaderMapTest.cpp
Commit eb2393659113696adf2bd770917f3109d1455c76 by fraser [RISCV] Support vector conversions between fp and i1 This patch custom lowers FP_TO_[US]INT and [US]INT_TO_FP conversions between floating-point and boolean vectors. As the default action is scalarization, this patch both supports scalable-vector conversions and improves the code generation for fixed-length vectors. The lowering for these conversions can piggy-back on the existing lowering, which lowers the operations to a supported narrowing/widening conversion and then either an extension or truncation. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D103312
	llvm/lib/Target/RISCV/RISCVISelLowering.cpp
	llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll
	llvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll
	llvm/test/CodeGen/RISCV/rvv/vfptoi-sdnode.ll
	llvm/test/CodeGen/RISCV/rvv/vitofp-sdnode.ll
Commit 24ee6d3d3c6215db11e9015e94f5f4a9b5a7b750 by Raphael Isemann [lldb][NFC] Remove unused var in SBDebugger::GetInternalVariableValue This variable was originally just the default return value but got unused in 6920b52be6f8731692a9bff4fe6a7b596cda00c5 .
	lldb/source/API/SBDebugger.cpp
Commit 222aeb4d51a46c5a81c9e4ccb16d1d19dd21ec95 by david.green [DSE] Remove stores in the same loop iteration DSE will currently only remove stores in the same block unless they can be guaranteed to be loop invariant. This expands that to any stores that are in the same Loop, at the same loop level. This should still account for where AA/MSSA will not handle aliasing between loops, but allow the dead stores to be removed where they overlap in the same loop iteration. It requires adding loop info to DSE, but that looks fairly harmless. The test case this helps is from code like this, which can come up in certain matrix operations: for(i=..) dst[i] = 0; for(j=..) dst[i] += src[in+j]; After LICM, this becomes: for(i=..) dst[i] = 0; sum = 0; for(j=..) sum += src[in+j]; dst[i] = sum; The first store is dead, and with this patch is now removed. Differntial Revision: https://reviews.llvm.org/D100464
	llvm/test/Other/opt-O3-pipeline-enable-matrix.ll
	llvm/test/Transforms/DeadStoreElimination/multiblock-loops.ll
	llvm/lib/Transforms/Scalar/DeadStoreElimination.cpp
	llvm/test/Other/opt-O2-pipeline.ll
	llvm/test/Other/opt-O3-pipeline.ll
	llvm/test/CodeGen/AMDGPU/opt-pipeline.ll
	llvm/test/Other/opt-Os-pipeline.ll
Commit 7161bb87c914684562bfb20fec7d60e533150f7a by aqjune [InsCombine] Fix a few remaining vec transforms to use poison instead of undef This is a patch that replaces shufflevector and insertelement's placeholder value with poison. Underlying motivation is to fix the semantics of shufflevector with undef mask to return poison instead (D93818) The consensus has been made in the late 2020 via mailing list as well as the thread in https://bugs.llvm.org/show_bug.cgi?id=44185 . This patch is a simple syntactic change to the existing code, hence directly pushed as a commit.
	llvm/test/Transforms/InstCombine/extractelement.ll
	llvm/test/Transforms/SLPVectorizer/X86/operandorder.ll
	llvm/test/Transforms/SLPVectorizer/X86/pr46983.ll
	llvm/test/Transforms/LoopVectorize/X86/metadata-enable.ll
	llvm/test/Transforms/InstCombine/insert-extract-shuffle.ll
	llvm/test/Transforms/InstCombine/bitcast-vec-canon-inseltpoison.ll
	llvm/test/Transforms/InstCombine/X86/x86-pshufb-inseltpoison.ll
	llvm/test/Transforms/InstCombine/X86/x86-pshufb.ll
	llvm/test/Transforms/SLPVectorizer/X86/alternate-int.ll
	llvm/test/Transforms/InstCombine/bitcast-vec-canon.ll
	llvm/test/Transforms/InstCombine/broadcast-inseltpoison.ll
	llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
	llvm/test/Transforms/InstCombine/masked_intrinsics.ll
	llvm/test/Transforms/SLPVectorizer/AArch64/getelementptr.ll
	llvm/test/Transforms/SLPVectorizer/X86/pr47629.ll
	llvm/test/Transforms/InstCombine/broadcast.ll
	llvm/test/Transforms/InstCombine/masked_intrinsics-inseltpoison.ll
	llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
	llvm/test/Transforms/InstCombine/extractelement-inseltpoison.ll
	llvm/test/Transforms/SLPVectorizer/X86/alternate-int-inseltpoison.ll
	llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
	llvm/test/Transforms/InstCombine/insert-extract-shuffle-inseltpoison.ll
	llvm/lib/Transforms/InstCombine/InstCombineVectorOps.cpp
	llvm/test/Transforms/InstCombine/canonicalize-vector-extract.ll
	llvm/test/Transforms/SLPVectorizer/X86/pr47629-inseltpoison.ll
Commit 2b37c405cc18019ea5056a63fa65f839a4890b50 by fraser [RISCV] Scale scalably-typed split argument offsets by VSCALE This patch fixes a bug in lowering scalable-vector types in RISC-V's main calling convention. When scalable-vector types are split and passed indirectly, the target is responsible for scaling the offset -- initially set to the known-minimum store size -- by the scalable factor. Before this we were issuing overlapping loads or stores to the different parts, leading to incorrect codegen. Credit to @HsiangKai for spotting this. Reviewed By: HsiangKai Differential Revision: https://reviews.llvm.org/D103262
	llvm/lib/Target/RISCV/RISCVISelLowering.cpp
	llvm/test/CodeGen/RISCV/rvv/calling-conv.ll
Commit dee85d47d9f15fc268f7b18f279dac2774836615 by djtodoro [LiveDebugVariables] Stop trimming locations of non-inlined vars The D35953, D62650 and D73691 introduced trimming of variables locations in LiveDebugVariables pass, since there are some cases where after the virtregrewrite we have exploded number of DBG_VALUEs created for some inlined variables. As it looks, all problematic cases were regarding inlined variables, so it seems reasonable to stop trimming the location ranges for non-inlined variables. It has very good impact on the llvm-locstats report. Differential Revision: https://reviews.llvm.org/D102917
	llvm/test/CodeGen/PowerPC/non-debug-mi-search-frspxsrsp.ll
	llvm/lib/CodeGen/LiveDebugVariables.cpp
	llvm/test/DebugInfo/X86/dbg-addr-dse.ll
	llvm/test/DebugInfo/MIR/Mips/livedebugvars-stop-trimming-loc.mir
	llvm/test/CodeGen/AMDGPU/ptr-arg-dbg-value.ll