SuccessChanges

Summary

  1. [libc][NFC][Obvious] Compare against size_t values in ArrayRef tests. (details)
  2. [JITLink][MachO] Split C-string literal sections on null-terminators. (details)
  3. [OpenMP] Add an information flag for device data transfers (details)
  4. Add llvm_unreacheable to silence warning "not all control paths return a value" (NFC) (details)
  5. Revert "Add a static assertions for custom Op<> to not defined data members (NFC)" (details)
  6. Rename compiler-rt/lib/orc/endian.h to endianness.h to avoid conflict with system headers (details)
  7. Add a couple of missing includes (details)
  8. ORTRT: Add tests for string_view equality and inequality operators (details)
  9. Reland "[AMDGPU] Add gfx1013 target" (details)
  10. [PowerPC][Dwarf] Assign MMA register's dwarf register number to negative value (details)
  11. [NFC][XCOFF] Use yaml2obj in llvm-objdump/XCOFF/section-headers.test instead of binary files. (details)
  12. [RISCV][NFC] Add a single space after comma for VType (details)
Commit 3d515cb185d86d8f89fe60a4e5ef2a6278baa368 by sivachandra
[libc][NFC][Obvious] Compare against size_t values in ArrayRef tests.

Different platforms treat size_t differently so we should compare sizes
of ArrayRef objects with size_t values (instead of the current unsigned
long values.)
The file was modifiedlibc/test/utils/CPP/arrayref_test.cpp
Commit f9649d123db64e38bce7bcb4cc5791239820f3e2 by Lang Hames
[JITLink][MachO] Split C-string literal sections on null-terminators.

MachO C-string literal sections should be split on null-terminator boundaries,
rather than the usual symbol boundaries. This patch updates
MachOLinkGraphBuilder to do that.
The file was modifiedllvm/lib/ExecutionEngine/JITLink/MachOLinkGraphBuilder.cpp
The file was modifiedllvm/lib/ExecutionEngine/JITLink/MachOLinkGraphBuilder.h
Commit df965513a9aa0cbf0d20e8458fa07577f58e112d by huberjn
[OpenMP] Add an information flag for device data transfers

This patch adds an information flag that indicated when data is being copied to
and from the device. This will be helpful for finding redundant or unnecessary
data transfers in applications.

Reviewed By: jdoerfert, grokos

Differential Revision: https://reviews.llvm.org/D103927
The file was modifiedopenmp/docs/design/Runtimes.rst
The file was modifiedopenmp/libomptarget/test/offloading/info.c
The file was modifiedopenmp/libomptarget/include/Debug.h
The file was modifiedopenmp/libomptarget/src/device.cpp
Commit 2c8115482312fc0c7ce836f0f0886d0e153183eb by joker.eph
Add llvm_unreacheable to silence warning "not all control paths return a value" (NFC)
The file was modifiedmlir/lib/IR/SymbolTable.cpp
Commit a0ac51467697d45a353ed9710ca5c75b6bf9b763 by joker.eph
Revert "Add a static assertions for custom Op<> to not defined data members (NFC)"

This reverts commit c0edcec630eb26e12d66dae2f0e1fbf5258cb6ac.

The windows bot was broken by this change.
The file was modifiedmlir/include/mlir/IR/OpDefinition.h
Commit cb09f2b10cbebb76842998b9ac6173f9723e419e by dblaikie
Rename compiler-rt/lib/orc/endian.h to endianness.h to avoid conflict with system headers
The file was removedcompiler-rt/lib/orc/endian.h
The file was modifiedcompiler-rt/lib/orc/CMakeLists.txt
The file was addedcompiler-rt/lib/orc/endianness.h
The file was modifiedcompiler-rt/lib/orc/wrapper_function_utils.h
The file was modifiedcompiler-rt/lib/orc/unittests/endian_test.cpp
Commit 4d9cc7c244e7fe2ce60202f1a7174109efb92504 by dblaikie
Add a couple of missing includes
The file was modifiedcompiler-rt/lib/orc/stl_extras.h
The file was modifiedcompiler-rt/lib/orc/c_api.h
Commit 8051a48e65cc78ccedc9bbd590dbc34a21a07184 by dblaikie
ORTRT: Add tests for string_view equality and inequality operators
The file was modifiedcompiler-rt/lib/orc/unittests/adt_test.cpp
Commit 294efbbd3e3d55671ef8b220c231a2807c38eefe by brendon.cahoon
Reland "[AMDGPU] Add gfx1013 target"

This reverts commit 211e584fa2a4c032e4d573e7cdbffd622aad0a8f.

Fixed a use-after-free error that caused the sanitizers to fail.
The file was modifiedllvm/docs/AMDGPUUsage.rst
The file was modifiedllvm/lib/ObjectYAML/ELFYAML.cpp
The file was modifiedopenmp/libomptarget/plugins/amdgpu/impl/get_elf_mach_gfx_name.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
The file was modifiedllvm/tools/llvm-readobj/ELFDumper.cpp
The file was modifiedclang/lib/Basic/Targets/NVPTX.cpp
The file was modifiedllvm/test/tools/llvm-readobj/ELF/amdgpu-elf-headers.test
The file was modifiedllvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
The file was modifiedllvm/test/Object/AMDGPU/elf-header-flags-mach.yaml
The file was modifiedllvm/lib/Support/TargetParser.cpp
The file was modifiedllvm/include/llvm/Support/TargetParser.h
The file was modifiedclang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp
The file was modifiedllvm/lib/Target/AMDGPU/SIISelLowering.cpp
The file was modifiedclang/test/Driver/amdgpu-mcpu.cl
The file was modifiedllvm/test/CodeGen/AMDGPU/elf-header-flags-mach.ll
The file was modifiedclang/lib/Basic/Cuda.cpp
The file was modifiedllvm/include/llvm/BinaryFormat/ELF.h
The file was modifiedllvm/test/MC/AMDGPU/dl-insts-err.s
The file was modifiedllvm/test/tools/llvm-objdump/ELF/AMDGPU/subtarget.ll
The file was modifiedllvm/lib/Object/ELFObjectFile.cpp
The file was modifiedllvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
The file was modifiedclang/test/Misc/target-invalid-cpu-note.c
The file was modifiedllvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp
The file was modifiedllvm/lib/Target/AMDGPU/GCNProcessors.td
The file was modifiedllvm/lib/Target/AMDGPU/GCNSubtarget.h
The file was modifiedllvm/lib/Target/AMDGPU/MIMGInstructions.td
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
The file was modifiedclang/lib/Basic/Targets/AMDGPU.cpp
The file was modifiedllvm/test/MC/AMDGPU/gfx10_unsupported.s
The file was modifiedclang/test/CodeGenOpenCL/amdgpu-features.cl
The file was modifiedclang/test/Driver/amdgpu-macros.cl
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/directive-amdgcn-target.ll
The file was modifiedclang/include/clang/Basic/Cuda.h
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPU.td
Commit c87c294397ea4c3dae31f5a7fd6e38602338fd57 by lkail
[PowerPC][Dwarf] Assign MMA register's dwarf register number to negative value

According to ELF V2 ABI, `0` should be the dwarf number of `r0`. Currently MMA's register also uses `0` as its dwarf number, this confuses `RegisterInfoEmitter` and generates wrong dwarf -> llvm mapping.
```
extern const MCRegisterInfo::DwarfLLVMRegPair PPCDwarfFlavour1Dwarf2L[] = {
  { 0U, PPC::VSRp31 },
```
This leads to wrong cfi output in https://reviews.llvm.org/D100290.

Reviewed By: jsji

Differential Revision: https://reviews.llvm.org/D103761
The file was modifiedllvm/lib/Target/PowerPC/PPCRegisterInfo.td
Commit db4ac5a63e11b90ab585abf9531edb4ed6f69be0 by esme.yi
[NFC][XCOFF] Use yaml2obj in llvm-objdump/XCOFF/section-headers.test instead of binary files.

Summary: This a minor patch to refactor the test file,
llvm-objdump/XCOFF/section-headers.test, to use yaml2obj
for this testing rather than a canned binary.

Reviewed By: jhenderson

Differential Revision: https://reviews.llvm.org/D103146
The file was removedllvm/test/tools/llvm-objdump/XCOFF/Inputs/xcoff-long-sec-names.o
The file was modifiedllvm/test/tools/llvm-objdump/XCOFF/section-headers.test
The file was removedllvm/test/tools/llvm-objdump/XCOFF/Inputs/xcoff-section-headers-truncate.o
Commit 242ddd50897cef56de3e4f993bbd0c70a22f528f by jim
[RISCV][NFC] Add a single space after comma for VType

In most of cases, it has a single space after comma in assembly operands.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D103790
The file was modifiedllvm/test/CodeGen/RISCV/rvv/calling-conv-fastcc.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vwaddu.w-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfmsub-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfwcvt-f-x-rv32.ll
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The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfwsub-rv32.ll
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The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfwsub-rv64.ll
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The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-setcc.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/viota-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmsbc-rv32.ll
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The file was modifiedllvm/test/CodeGen/RISCV/rvv/vsra-vp.ll
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The file was modifiedllvm/test/CodeGen/RISCV/rvv/vsaddu-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfslide1down-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vredmax-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfdiv-sdnode.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfsgnjn-rv32.ll
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The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfnmacc-rv32.ll
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The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmsgtu-rv64.ll
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The file was modifiedllvm/test/CodeGen/RISCV/rvv/insertelt-fp-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vor-vp.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vse-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vdiv-vp.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vnsra-rv32.ll
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The file was modifiedllvm/test/CodeGen/RISCV/rvv/vremu-vp.ll
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The file was modifiedllvm/test/CodeGen/RISCV/rvv/vsaddu-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfncvt-f-f-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfmsac-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vsseg-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfnmsub-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmfle-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vwaddu-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-x-f-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-int.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vzext-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/constant-folding.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vredsum-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vrsub-sdnode-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-xu-f-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmin-sdnode-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vmsgtu-rv32.ll
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The file was modifiedllvm/test/CodeGen/RISCV/rvv/vamomaxu-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vfcvt-f-xu-rv32.ll
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