SuccessChanges

Summary

  1. [static initializers] Emit global_ctors and global_dtors in reverse order when .ctors/.dtors are used. (details)
  2. [IR] Value: Fix OpCode checks (details)
  3. [RISCV] Add test cases that show failure to use some W instructions if they are proceeded by a load. NFC (details)
  4. [SDAG] Fix pow2 assumption when splitting vectors (details)
  5. [ValueTypes] Define MVTs for v6i32, v6f32, v7i32, v7f32 (details)
  6. [AArch64][GlobalISel] Fix incorrectly generating uxtw/sxtw for addressing modes. (details)
  7. [mlir][IR] Move MemRefElementTypeInterface to a new BuiltinTypeInterfaces file (details)
  8. [mlir] Add new SubElementAttr/SubElementType Interfaces (details)
  9. [mlir-ir-printing] Prefix the dump message with the split marker(// -----) (details)
  10. [Flang] Compile fix after D99459. (details)
  11. [RISCV] Use ComputeNumSignBits/MaskedValueIsZero in RISCVDAGToDAGISel::selectSExti32/selectZExti32. (details)
  12. [VectorCombine] Fix alignment in single element store (details)
  13. Revert "[clang] Implement P2266 Simpler implicit move" (details)
  14. Revert "[clang] NRVO: Improvements and handling of more cases." (details)
  15. [RISCV] Remove extra assignment of intrinsic ID in ManualCodegen. NFC (details)
Commit 5a1589fc6d1131e6d73c498cc5987433d1c5e098 by wolfgang_pieb
[static initializers] Emit global_ctors and global_dtors in reverse order when .ctors/.dtors are used.

Reviewed By: rnk, MaskRay, efriedma

Differential Revision: https://reviews.llvm.org/D103495
The file was modifiedllvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
The file was modifiedllvm/test/CodeGen/X86/2011-08-29-InitOrder.ll
The file was modifiedllvm/test/CodeGen/X86/constructor.ll
The file was modifiedllvm/test/CodeGen/SPARC/constructor.ll
Commit ffaca140d01b0b93723c3322b08351b03b95831f by ndesaulniers
[IR] Value: Fix OpCode checks

Value::SubclassID cannot be directly compared to Instruction enums, such as
Instruction::{Call,Invoke,CallBr}. We have to first subtract InstructionVal
from the SubclassID to get the OpCode, similar to Instruction::getOpCode().

Reviewed By: nickdesaulniers

Differential Revision: https://reviews.llvm.org/D104043
The file was modifiedllvm/lib/IR/Value.cpp
Commit b35a842581f089daa57dd7e6b78ccb08d92709b2 by craig.topper
[RISCV] Add test cases that show failure to use some W instructions if they are proceeded by a load. NFC

The loads end up becoming sextload/zextload which prevent our
isel patterns from finding the sign_extend_inreg or AND instruction
we need.

The easiest way to fix this is to use computeKnownBits or
ComputeNumSignBits in our isel matching to catch this.
The file was modifiedllvm/test/CodeGen/RISCV/double-convert.ll
The file was modifiedllvm/test/CodeGen/RISCV/float-convert.ll
The file was modifiedllvm/test/CodeGen/RISCV/rv64zbb.ll
The file was modifiedllvm/test/CodeGen/RISCV/half-convert.ll
Commit cfbb92441f17d1f5a9d9c3e195646df4117cb0ca by carl.ritson
[SDAG] Fix pow2 assumption when splitting vectors

When reducing vector builds to shuffles it possible that
the DAG combiner may try to extract invalid subvectors.

This happens as the existing code assumes vectors will be power
of 2 sizes, which is already untrue, but becomes more noticable
with v6 and v7 types.
Specifically the existing code assumes that half PowerOf2Ceil of
a given vector index will fit twice into a given vector.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D103880
The file was modifiedllvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Commit 2c2d2922a24b7fa8a92f38d9043ab476d330210d by carl.ritson
[ValueTypes] Define MVTs for v6i32, v6f32, v7i32, v7f32

For use in AMDGPU selection DAG.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D103881
The file was modifiedllvm/utils/TableGen/CodeGenTarget.cpp
The file was modifiedllvm/include/llvm/Support/MachineValueType.h
The file was modifiedllvm/include/llvm/CodeGen/ValueTypes.td
The file was modifiedllvm/lib/CodeGen/ValueTypes.cpp
Commit 670edf3ee0045ce007f2f6aec94a2c3344c5682e by Amara Emerson
[AArch64][GlobalISel] Fix incorrectly generating uxtw/sxtw for addressing modes.

When the extend is from 8 or 16 bits, the addressing modes don't support those
extensions, but we weren't checking that and therefore always generated the 32->64b
extension mode. Fun.

Differential Revision: https://reviews.llvm.org/D104070
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/select-arith-extended-reg.mir
Commit f8a1d652da00ecff448213c58522da5a61d9bc4b by riddleriver
[mlir][IR] Move MemRefElementTypeInterface to a new BuiltinTypeInterfaces file

This allows for using other type interfaces in the builtin dialect, which currently results in a compile time failure (as it generates duplicate interface declarations).
The file was modifiedmlir/include/mlir/IR/BuiltinTypes.td
The file was modifiedmlir/lib/IR/CMakeLists.txt
The file was addedmlir/include/mlir/IR/BuiltinTypeInterfaces.td
The file was modifiedmlir/include/mlir/IR/CMakeLists.txt
Commit c42dd5dbb015afaef99cf876195c474c63c2393e by riddleriver
[mlir] Add new SubElementAttr/SubElementType Interfaces

These interfaces allow for a composite attribute or type to opaquely provide access to any held attributes or types. There are several intended use cases for this interface. The first of which is to allow the printer to create aliases for non-builtin dialect attributes and types. In the future, this interface will also be extended to allow for SymbolRefAttr to be placed on other entities aside from just DictionaryAttr and ArrayAttr.

To limit potential test breakages, this revision only adds the new interfaces to the builtin attributes/types that are currently hardcoded during AsmPrinter alias generation. In a followup the remaining builtin attributes/types, and non-builtin attributes/types can be extended to support it.

Differential Revision: https://reviews.llvm.org/D102945
The file was modifiedmlir/lib/IR/BuiltinAttributes.cpp
The file was addedmlir/unittests/IR/SubElementInterfaceTest.cpp
The file was modifiedmlir/include/mlir/IR/BuiltinTypes.h
The file was modifiedmlir/unittests/IR/CMakeLists.txt
The file was modifiedmlir/include/mlir/IR/BuiltinTypes.td
The file was modifiedmlir/lib/IR/BuiltinTypes.cpp
The file was addedmlir/lib/IR/SubElementInterfaces.cpp
The file was modifiedmlir/include/mlir/IR/BuiltinAttributes.h
The file was modifiedmlir/lib/IR/CMakeLists.txt
The file was addedmlir/include/mlir/IR/SubElementInterfaces.td
The file was modifiedmlir/include/mlir/IR/CMakeLists.txt
The file was modifiedmlir/include/mlir/IR/BuiltinAttributes.td
The file was modifiedmlir/lib/IR/AsmPrinter.cpp
The file was addedmlir/include/mlir/IR/SubElementInterfaces.h
Commit 8800047707a9cd86fb7143699af0e5564c28f4aa by riddleriver
[mlir-ir-printing] Prefix the dump message with the split marker(// -----)

This allows for better interaction with tools (such as mlir-lsp-server), as it separates the IR into separate modules for consecutive dumps.

Differential Revision: https://reviews.llvm.org/D104073
The file was modifiedmlir/test/Pass/run-reproducer.mlir
The file was modifiedmlir/test/Pass/ir-printing.mlir
The file was modifiedmlir/lib/Pass/IRPrinting.cpp
Commit 7836d058c7e115eace62e324ef6c01670326f518 by llvm-project
[Flang] Compile fix after D99459.

Fix Flang build after addition of a new OpenMP clauses for a Clang
patch (D99459). Flang is using TableGen to generation the declaration
of clause checks and the new clause was missing a definiton.
The file was modifiedflang/lib/Semantics/check-omp-structure.cpp
Commit 420bd5ee8ec996a2c2e305541e59465a5ba436e3 by craig.topper
[RISCV] Use ComputeNumSignBits/MaskedValueIsZero in RISCVDAGToDAGISel::selectSExti32/selectZExti32.

This helps us select W instructions in more cases. Most of the
affected tests have had the sign_extend_inreg or AND folded into
sextload/zextload.

Differential Revision: https://reviews.llvm.org/D104079
The file was modifiedllvm/test/CodeGen/RISCV/double-convert.ll
The file was modifiedllvm/test/CodeGen/RISCV/float-convert.ll
The file was modifiedllvm/test/CodeGen/RISCV/rv64zbb.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoB.td
The file was modifiedllvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
The file was modifiedllvm/test/CodeGen/RISCV/half-convert.ll
The file was modifiedllvm/test/CodeGen/RISCV/rem.ll
Commit 2670c7dd5b25e87825edc0aca7729c1d3dba5afc by qiucofan
[VectorCombine] Fix alignment in single element store

This fixes the concern in single element store scalarization that the
alignment of new store may be larger than it should be. It calculates
the largest alignment if index is constant, and a safe one if not.

Reviewed By: lebedev.ri, spatel

Differential Revision: https://reviews.llvm.org/D103419
The file was modifiedllvm/test/Transforms/VectorCombine/load-insert-store.ll
The file was modifiedllvm/lib/Transforms/Vectorize/VectorCombine.cpp
Commit db26615aa6a165483e6540b3f6ed684a0cbe06df by aeubanks
Revert "[clang] Implement P2266 Simpler implicit move"

This reverts commit cbd0054b9eb17ec48f0702e3828209646c8f5ebd.
The file was modifiedclang/include/clang/Sema/Sema.h
The file was modifiedclang/test/SemaCXX/coroutines.cpp
The file was modifiedclang/lib/Sema/SemaExprCXX.cpp
The file was modifiedclang/lib/Sema/SemaType.cpp
The file was modifiedclang/test/SemaCXX/constant-expression-cxx11.cpp
The file was modifiedclang/lib/Sema/SemaCoroutine.cpp
The file was modifiedclang/test/SemaCXX/constant-expression-cxx14.cpp
The file was modifiedclang/test/SemaCXX/return-stack-addr.cpp
The file was modifiedclang/test/CXX/expr/expr.prim/expr.prim.lambda/p4-cxx14.cpp
The file was modifiedclang/test/SemaCXX/deduced-return-type-cxx14.cpp
The file was modifiedclang/test/CXX/temp/temp.decls/temp.mem/p5.cpp
The file was modifiedclang/test/SemaCXX/warn-return-std-move.cpp
The file was modifiedclang/test/CXX/drs/dr3xx.cpp
The file was modifiedclang/lib/Sema/SemaStmt.cpp
The file was modifiedclang/test/CXX/class/class.init/class.copy.elision/p3.cpp
The file was modifiedclang/test/CXX/dcl.dcl/dcl.spec/dcl.type/dcl.spec.auto/p7-cxx14.cpp
The file was modifiedclang/test/SemaCXX/coroutine-rvo.cpp
Commit 85ca7e424fd050582026a299906c9e8397043c52 by aeubanks
Revert "[clang] NRVO: Improvements and handling of more cases."

This reverts commit 667fbcdd0b2ee5e78f5ce9789b862e3bbca94644.

Causes crashes on a stage 2 build on Windows.
The file was modifiedclang/lib/Sema/SemaTemplateInstantiateDecl.cpp
The file was modifiedclang/include/clang/Sema/Sema.h
The file was modifiedclang/lib/Sema/SemaStmt.cpp
The file was modifiedclang/lib/Sema/SemaExprCXX.cpp
The file was modifiedclang/lib/Sema/Sema.cpp
The file was modifiedclang/lib/Sema/SemaCoroutine.cpp
The file was modifiedclang/test/CodeGen/nrvo-tracking.cpp
Commit 081ae5fe1aa3ead6d9da75747d3698f09ff89cb9 by craig.topper
[RISCV] Remove extra assignment of intrinsic ID in ManualCodegen. NFC

There's already an autogenerated assignment.

Fixes static analyzer warning reported in PR50593.
The file was modifiedclang/include/clang/Basic/riscv_vector.td