SuccessChanges

Changes from Git (git http://labmaster3.local/git/llvm-project.git)

Summary

  1. Restore diagnostic handler after CodeGenAction::ExecuteAction (details)
  2. [RISCV] Convert VSLIDE(UP|DOWN) nodes to "VL" versions (NFC) (details)
  3. [TTI] Unify FavorPostInc and FavorBackedgeIndex into getPreferredAddressingMode (details)
  4. Revert "[TTI] Unify FavorPostInc and FavorBackedgeIndex into getPreferredAddressingMode" (details)
  5. [LoopLoadElim] Pass ScalarEvolution in old pass manager. PR49141 (details)
  6. Recommit "[TTI] Unify FavorPostInc and FavorBackedgeIndex into getPreferredAddressingMode" (details)
  7. [X86][SSE] Add missing USUBSAT test coverage (details)
  8. [X86][AVX] Regenerate PSUBUS tests for slow/fast shuffle AVX2 targets (details)
  9. [lldb] Remove the legacy FreeBSD plugin (details)
  10. [lldb] Rename FreeBSDRemote to FreeBSD (NFC) (details)
  11. [sanitizer] [arm] Disable some LSAN tests for arm-linux-gnueabihf (details)
  12. Add Semantic check for Flang OpenMP 4.5 - 2.7.1  Do Loop restrictions. (details)
  13. [ARM] Extend search for increment in load/store optimizer (details)
  14. [analyzer][NFC] Fix test failures for builds w/o assertions (details)
  15. [CodeGen][SelectionDAG]Add new intrinsic  experimental.vector.reverse (details)
  16. [mlir] Use the interface-based translation for LLVM "intrinsic" dialects (details)
  17. Fix MSVC natvis visualisation of llvm::FixedVectorTyID and ScalableVectorTyID (details)
  18. [LoopVectorizer] Require no-signed-zeros-fp-math=true for fmin/fmax (details)
  19. [llvm] NFC: Cleanup llvm-yaml-numeric-parser-fuzzer (details)
  20. [llvm-nm] Tidy up error messages (details)
  21. [llvm-nm][test] Add additional test coverage for llvm-nm options (details)
  22. [mlir] use new cmake targets in mlir-*-runner (details)
  23. [X86] Add SSE2+SSE3 common check prefix to psubus tests (details)
  24. [debuginfo-tests] Remove explicit checks for Python 3 (details)
  25. [debuginfo-tests] Remove some unused config variables (details)
  26. [CostModel]Add cost model for experimental.vector.reverse (details)
  27. [debuginfo-tests] Delete unused/duplicate imports (details)
  28. Make shape.is_broadcastable/shape.cstr_broadcastable nary (details)
  29. [ARM] Add some basic Min/Max costs (details)
  30. [LangRef] Increase size of title underline for experimental.vector.reverse (details)
  31. [AArch64] Move machine bundle unpacking to PreEmit2 phase. (details)
  32. [NFC] Remove spurious ';' on return line in python code (details)
  33. [DAG] visitVSELECT - move OpLHS == LHS into inner if() in USUBSAT matching. NFCI. (details)
  34. [clangd] Delay binding LSP methods until initialize. NFC (details)
  35. [mlir] Add clone method to ShapedType (details)
  36. [CMake] Delete LLVM_RUNTIME_BUILD_ID_LINK_TARGETS (details)
  37. Support emitting complex expressions that include entry values (details)
  38. [OpenMP][NFC] Pre-commit test changes regarding PR48933 (details)
  39. [OpenMP] Attribute target diagnostics properly (details)
  40. [OpenMP] Delay more diagnostics of potentially non-emitted code (details)
  41. [llvm-objcopy] Delete --build-id-link-{dir,input,output} (details)
  42. [AMDGPU] Add two TSFlags: IsAtomicNoRtn and IsAtomicRtn (details)
  43. [lto] Enable new PM when the PM config is non-empty (details)
  44. TransformUtils: Fix metadata handling in CloneModule (and improve CloneFunctionInto) (details)
  45. [clangd] Pass raw client capabilities to modules. NFC (details)
  46. Define new/delete in libc++ when using libcxxrt (details)
  47. [ValueTracking] add scan limit for assumes (details)
  48. [libc++] Mark __cpp_lib_constexpr_memory as being implemented (details)
  49. [LLDB] Skip TestMultipleTargets.py on Arm/AArch64 Linux (details)
  50. [RISCV][LegalizeTypes] Try to expand BITREVERSE before promoting if the promoted BITREVERSE would expand anyway. (details)
  51. [RISCV] Add support for fixed vector floating point setcc. (details)
Commit e54811ff7e0bc99f337bcbb569311bb166187322 by marco.antognini
Restore diagnostic handler after CodeGenAction::ExecuteAction

Fix dangling pointer to local variable and address some typos.

Reviewed By: xur

Differential Revision: https://reviews.llvm.org/D96487
The file was modifiedclang/lib/CodeGen/CodeGenAction.cpp
The file was modifiedllvm/include/llvm/IR/LLVMContext.h
Commit 4bd5bd40094c7b8b691cf394d813efc48d82acfd by fraser
[RISCV] Convert VSLIDE(UP|DOWN) nodes to "VL" versions (NFC)

This patch prepares the RISCV VSLIDEUP and VSLIDEDOWN custom nodes to
ones carrying additional mask and vector-length operands. This is
primarily so they can be used by both systems.

This also takes the opportunity to create some helper functions to deal
with the common task of getting the default (unmasked) VL operands.

Reviewed By: craig.topper, arcbbb

Differential Revision: https://reviews.llvm.org/D96505
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.h
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.cpp
Commit cd6de0e8de4a5fd558580be4b1a07116914fc8ed by sjoerd.meijer
[TTI] Unify FavorPostInc and FavorBackedgeIndex into getPreferredAddressingMode

This refactors shouldFavorPostInc() and shouldFavorBackedgeIndex() into
getPreferredAddressingMode() so that we have one interface to steer LSR in
generating the preferred addressing mode.

Differential Revision: https://reviews.llvm.org/D96600
The file was modifiedllvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
The file was modifiedllvm/lib/Target/Hexagon/HexagonTargetTransformInfo.h
The file was modifiedllvm/include/llvm/Analysis/TargetTransformInfoImpl.h
The file was modifiedllvm/lib/Target/ARM/ARMTargetTransformInfo.h
The file was modifiedllvm/include/llvm/Analysis/TargetTransformInfo.h
The file was modifiedllvm/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp
The file was modifiedllvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
The file was modifiedllvm/lib/Analysis/TargetTransformInfo.cpp
Commit effc3b079927a6dd3084b4ff712ec07f926366f0 by sjoerd.meijer
Revert "[TTI] Unify FavorPostInc and FavorBackedgeIndex into getPreferredAddressingMode"

This reverts commit cd6de0e8de4a5fd558580be4b1a07116914fc8ed.
The file was modifiedllvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
The file was modifiedllvm/lib/Target/Hexagon/HexagonTargetTransformInfo.h
The file was modifiedllvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
The file was modifiedllvm/lib/Target/ARM/ARMTargetTransformInfo.h
The file was modifiedllvm/include/llvm/Analysis/TargetTransformInfo.h
The file was modifiedllvm/include/llvm/Analysis/TargetTransformInfoImpl.h
The file was modifiedllvm/lib/Analysis/TargetTransformInfo.cpp
The file was modifiedllvm/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp
Commit e3c759bd583db3ff71ed6607103f75848287af26 by mkazantsev
[LoopLoadElim] Pass ScalarEvolution in old pass manager. PR49141

Loop canonicalization may end up deleting blocks from CFG. And
Scalar Evolution may still keep cached referenced to those blocks
unless updated properly.
The file was modifiedllvm/lib/Transforms/Scalar/LoopLoadElimination.cpp
The file was addedllvm/test/Transforms/LoopLoadElim/pr-49141.ll
Commit 357237e93ec1c75302bf11975cfadc8fc2220a55 by sjoerd.meijer
Recommit "[TTI] Unify FavorPostInc and FavorBackedgeIndex into getPreferredAddressingMode"

This reverts commit effc3b079927a6dd3084b4ff712ec07f926366f0, with the build
problem fixed.
The file was modifiedllvm/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp
The file was modifiedllvm/lib/Target/Hexagon/HexagonTargetTransformInfo.h
The file was modifiedllvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
The file was modifiedllvm/include/llvm/Analysis/TargetTransformInfo.h
The file was modifiedllvm/lib/Analysis/TargetTransformInfo.cpp
The file was modifiedllvm/lib/Target/ARM/ARMTargetTransformInfo.h
The file was modifiedllvm/include/llvm/Analysis/TargetTransformInfoImpl.h
The file was modifiedllvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
Commit 7f0ed92667249b48e2064c0e67cc256b6141752b by llvm-dev
[X86][SSE] Add missing USUBSAT test coverage

Before we start removing combineSubToSubus (PR40111) - make sure we have actually have test coverage for SUB(X,TRUNC(UMIN(ZEXT(X),Y))) -> USUBSAT(X,TRUNC(UMIN(Y,C)))) patterns
The file was modifiedllvm/test/CodeGen/X86/psubus.ll
Commit f32dc6bb42fd24517289fd1e3418994daa4fec20 by llvm-dev
[X86][AVX] Regenerate PSUBUS tests for slow/fast shuffle AVX2 targets

update_llc_test_checks.py isn't reporting when we don't have a usable prefix for a particular run any more - so we lost all AVX2 testing!
The file was modifiedllvm/test/CodeGen/X86/psubus.ll
Commit cd443398566b953642ead7c81528ab5b4e211eb9 by mgorny
[lldb] Remove the legacy FreeBSD plugin

The new FreeBSDRemote plugin has reached feature parity with the legacy
plugin, so we can finally remove the latter.  The new plugin will
be renamed to FreeBSD in a separate commit to avoid confusion.

Differential Revision: https://reviews.llvm.org/D96555
The file was removedlldb/source/Plugins/Process/FreeBSD/RegisterContextPOSIXProcessMonitor_arm.h
The file was modifiedlldb/source/Plugins/Process/CMakeLists.txt
The file was removedlldb/source/Plugins/Process/FreeBSD/RegisterContextPOSIXProcessMonitor_x86.cpp
The file was removedlldb/source/Plugins/Process/FreeBSD/FreeBSDThread.h
The file was removedlldb/source/Plugins/Process/FreeBSD/POSIXStopInfo.h
The file was removedlldb/source/Plugins/Process/FreeBSD/RegisterContextPOSIX.h
The file was removedlldb/source/Plugins/Process/FreeBSD/RegisterContextPOSIXProcessMonitor_x86.h
The file was removedlldb/source/Plugins/Process/FreeBSD/RegisterContextPOSIXProcessMonitor_powerpc.h
The file was modifiedlldb/tools/lldb-server/CMakeLists.txt
The file was removedlldb/source/Plugins/Process/FreeBSD/RegisterContextPOSIXProcessMonitor_mips64.cpp
The file was removedlldb/source/Plugins/Process/FreeBSD/CMakeLists.txt
The file was removedlldb/source/Plugins/Process/FreeBSD/RegisterContextPOSIXProcessMonitor_arm64.h
The file was removedlldb/source/Plugins/Process/FreeBSD/RegisterContextPOSIXProcessMonitor_arm64.cpp
The file was removedlldb/source/Plugins/Process/FreeBSD/ProcessFreeBSD.cpp
The file was removedlldb/source/Plugins/Process/FreeBSD/POSIXStopInfo.cpp
The file was removedlldb/source/Plugins/Process/FreeBSD/RegisterContextPOSIXProcessMonitor_mips64.h
The file was removedlldb/source/Plugins/Process/FreeBSD/RegisterContextPOSIXProcessMonitor_powerpc.cpp
The file was removedlldb/source/Plugins/Process/FreeBSD/ProcessFreeBSD.h
The file was modifiedlldb/source/Plugins/Platform/FreeBSD/PlatformFreeBSD.cpp
The file was removedlldb/source/Plugins/Process/FreeBSD/ProcessMonitor.cpp
The file was removedlldb/source/Plugins/Process/FreeBSD/FreeBSDThread.cpp
The file was removedlldb/source/Plugins/Process/FreeBSD/ProcessMonitor.h
The file was removedlldb/source/Plugins/Process/FreeBSD/RegisterContextPOSIXProcessMonitor_arm.cpp
The file was modifiedlldb/source/Plugins/Platform/FreeBSD/PlatformFreeBSD.h
Commit bee4d6efe1781365cb82dcc94ad959309354af6f by mgorny
[lldb] Rename FreeBSDRemote to FreeBSD (NFC)

Differential Revision: https://reviews.llvm.org/D96557
The file was removedlldb/source/Plugins/Process/FreeBSDRemote/NativeRegisterContextFreeBSD_x86_64.h
The file was removedlldb/source/Plugins/Process/FreeBSDRemote/NativeRegisterContextFreeBSD_arm64.cpp
The file was addedlldb/source/Plugins/Process/FreeBSD/NativeRegisterContextFreeBSD_powerpc.h
The file was removedlldb/source/Plugins/Process/FreeBSDRemote/NativeRegisterContextFreeBSD_mips64.h
The file was removedlldb/source/Plugins/Process/FreeBSDRemote/NativeThreadFreeBSD.h
The file was addedlldb/source/Plugins/Process/FreeBSD/NativeRegisterContextFreeBSD_arm.h
The file was addedlldb/source/Plugins/Process/FreeBSD/NativeThreadFreeBSD.h
The file was modifiedlldb/source/Plugins/Process/CMakeLists.txt
The file was addedlldb/source/Plugins/Process/FreeBSD/NativeRegisterContextFreeBSD_arm.cpp
The file was removedlldb/source/Plugins/Process/FreeBSDRemote/NativeRegisterContextFreeBSD.cpp
The file was addedlldb/source/Plugins/Process/FreeBSD/NativeRegisterContextFreeBSD_x86_64.h
The file was removedlldb/source/Plugins/Process/FreeBSDRemote/NativeRegisterContextFreeBSD_mips64.cpp
The file was addedlldb/source/Plugins/Process/FreeBSD/NativeRegisterContextFreeBSD_x86_64.cpp
The file was removedlldb/source/Plugins/Process/FreeBSDRemote/NativeProcessFreeBSD.h
The file was removedlldb/source/Plugins/Process/FreeBSDRemote/NativeRegisterContextFreeBSD_arm.cpp
The file was removedlldb/source/Plugins/Process/FreeBSDRemote/CMakeLists.txt
The file was removedlldb/source/Plugins/Process/FreeBSDRemote/NativeRegisterContextFreeBSD_arm.h
The file was addedlldb/source/Plugins/Process/FreeBSD/NativeRegisterContextFreeBSD_arm64.cpp
The file was addedlldb/source/Plugins/Process/FreeBSD/NativeThreadFreeBSD.cpp
The file was modifiedlldb/tools/lldb-server/lldb-gdbserver.cpp
The file was addedlldb/source/Plugins/Process/FreeBSD/CMakeLists.txt
The file was removedlldb/source/Plugins/Process/FreeBSDRemote/NativeRegisterContextFreeBSD_x86_64.cpp
The file was addedlldb/source/Plugins/Process/FreeBSD/NativeProcessFreeBSD.h
The file was removedlldb/source/Plugins/Process/FreeBSDRemote/NativeRegisterContextFreeBSD_arm64.h
The file was removedlldb/source/Plugins/Process/FreeBSDRemote/NativeRegisterContextFreeBSD_powerpc.cpp
The file was addedlldb/source/Plugins/Process/FreeBSD/NativeRegisterContextFreeBSD.h
The file was removedlldb/source/Plugins/Process/FreeBSDRemote/NativeProcessFreeBSD.cpp
The file was modifiedlldb/tools/lldb-server/CMakeLists.txt
The file was addedlldb/source/Plugins/Process/FreeBSD/NativeProcessFreeBSD.cpp
The file was addedlldb/source/Plugins/Process/FreeBSD/NativeRegisterContextFreeBSD_powerpc.cpp
The file was removedlldb/source/Plugins/Process/FreeBSDRemote/NativeRegisterContextFreeBSD_powerpc.h
The file was addedlldb/source/Plugins/Process/FreeBSD/NativeRegisterContextFreeBSD.cpp
The file was removedlldb/source/Plugins/Process/FreeBSDRemote/NativeRegisterContextFreeBSD.h
The file was removedlldb/source/Plugins/Process/FreeBSDRemote/NativeThreadFreeBSD.cpp
The file was addedlldb/source/Plugins/Process/FreeBSD/NativeRegisterContextFreeBSD_arm64.h
The file was addedlldb/source/Plugins/Process/FreeBSD/NativeRegisterContextFreeBSD_mips64.cpp
The file was addedlldb/source/Plugins/Process/FreeBSD/NativeRegisterContextFreeBSD_mips64.h
Commit b9d3234c70588e6591f3607da39cc03bded160fd by adhemerval.zanella
[sanitizer] [arm] Disable some LSAN tests for arm-linux-gnueabihf

Reinstate D90628 since the fix done by D96337 does not change the outcome
of the https://bugs.llvm.org/show_bug.cgi?id=48052
The file was modifiedcompiler-rt/test/lsan/TestCases/Linux/use_tls_pthread_specific_dynamic.cpp
The file was modifiedcompiler-rt/test/lsan/TestCases/ignore_object.c
The file was modifiedcompiler-rt/test/lsan/TestCases/disabler.c
The file was modifiedcompiler-rt/test/lsan/TestCases/use_after_return.cpp
The file was modifiedcompiler-rt/test/lsan/TestCases/Linux/cleanup_in_tsd_destructor.c
The file was modifiedcompiler-rt/test/lsan/TestCases/do_leak_check_override.cpp
Commit 20e3a6cb6270b68139f74529ab8efdfad1263533 by yhegde
Add Semantic check for Flang OpenMP 4.5 - 2.7.1  Do Loop restrictions.
Implementation of Do loop iteration variable check, Do while loop check, Do loop cycle restrictions.
Also to check whether the ordered clause is present on the loop construct if any ordered region ever
binds to a loop region arising from the loop construct.

Files:

check-omp-structure.h
check-omp-structure.cpp
resolve-directives.cpp

Testcases:

omp-do06-positivecases.f90
omp-do06.f90
omp-do08.f90
omp-do09.f90
omp-do10.f90
omp-do11.f90
omp-do12.f90
omp-do13.f90
omp-do14.f90
omp-do15.f90
omp-do16.f90
omp-do17.f90

Reviewed by: Kiran Chandramohan @kiranchandramohan , Valentin Clement @clementval

Differential Revision: https://reviews.llvm.org/D92732
The file was addedflang/test/Semantics/omp-do17.f90
The file was modifiedflang/lib/Semantics/check-omp-structure.h
The file was addedflang/test/Semantics/omp-do11.f90
The file was modifiedflang/test/Semantics/omp-do08.f90
The file was modifiedflang/test/Semantics/omp-do09.f90
The file was modifiedflang/test/Semantics/omp-do10.f90
The file was modifiedflang/lib/Semantics/resolve-directives.cpp
The file was addedflang/test/Semantics/omp-do15.f90
The file was addedflang/test/Semantics/omp-do16.f90
The file was modifiedflang/lib/Semantics/check-omp-structure.cpp
The file was addedflang/test/Semantics/omp-do06-positivecases.f90
The file was modifiedflang/test/Semantics/omp-do06.f90
The file was addedflang/test/Semantics/omp-do12.f90
The file was addedflang/test/Semantics/omp-do14.f90
The file was addedflang/test/Semantics/omp-do13.f90
Commit a838a4f69f500fc8e39fb4c9a1476f162ccf8423 by david.green
[ARM] Extend search for increment in load/store optimizer

Currently the findIncDecAfter will only look at the next instruction for
post-inc candidates in the load/store optimizer. This extends that to a
search through the current BB, until an instruction that modifies or
uses the increment reg is found. This allows more post-inc load/stores
and ldm/stm's to be created, especially in cases where a schedule might
move instructions further apart.

We make sure not to look any further for an SP, as that might invalidate
stack slots that are still in use.

Differential Revision: https://reviews.llvm.org/D95881
The file was modifiedllvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
The file was modifiedllvm/test/CodeGen/Thumb2/mve-vecreduce-loops.ll
The file was modifiedllvm/test/CodeGen/Thumb2/mve-postinc-lsr.ll
The file was modifiedllvm/test/CodeGen/Thumb2/mve-satmul-loops.ll
The file was modifiedllvm/test/CodeGen/Thumb2/mve-float32regloops.ll
The file was modifiedllvm/test/CodeGen/ARM/indexed-mem.ll
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-float-loops.ll
The file was modifiedllvm/test/CodeGen/Thumb2/mve-vldshuffle.ll
The file was modifiedllvm/test/CodeGen/Thumb2/LowOverheadLoops/fast-fp-loops.ll
The file was modifiedllvm/test/CodeGen/Thumb2/mve-postinc-distribute.ll
Commit 6f21adac6dd7082f7231ae342d40ed04f4885e79 by vsavchenko
[analyzer][NFC] Fix test failures for builds w/o assertions
The file was modifiedclang/test/Analysis/reinterpret-cast-pointer-to-member.cpp
Commit 2d728bbff5c688284b8b8306ecfd3000b0ab8bb1 by caroline.concatto
[CodeGen][SelectionDAG]Add new intrinsic  experimental.vector.reverse

This patch adds  a new intrinsic experimental.vector.reduce that takes a single
vector and returns a vector of matching type but with the original lane order
reversed. For example:

```
vector.reverse(<A,B,C,D>) ==> <D,C,B,A>
```

The new intrinsic supports fixed and scalable vectors types.
The fixed-width vector relies on shufflevector to maintain existing behaviour.
Scalable vector uses the new ISD node - VECTOR_REVERSE.

This new intrinsic is one of the named shufflevector intrinsics proposed on the
mailing-list in the RFC at [1].

Patch by Paul Walker (@paulwalker-arm).

[1] https://lists.llvm.org/pipermail/llvm-dev/2020-November/146864.html

Differential Revision: https://reviews.llvm.org/D94883
The file was modifiedllvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
The file was modifiedllvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
The file was modifiedllvm/include/llvm/IR/Intrinsics.td
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp
The file was modifiedllvm/lib/Analysis/InstructionSimplify.cpp
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
The file was modifiedllvm/lib/Target/AArch64/AArch64FastISel.cpp
The file was modifiedllvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.h
The file was addedllvm/test/CodeGen/AArch64/named-vector-shuffle-reverse-sve.ll
The file was addedllvm/test/CodeGen/AArch64/named-vector-shuffle-reverse-neon.ll
The file was modifiedllvm/include/llvm/Target/TargetSelectionDAG.td
The file was modifiedllvm/include/llvm/CodeGen/ISDOpcodes.h
The file was addedllvm/test/CodeGen/X86/named-vector-shuffle-reverse.ll
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
The file was modifiedllvm/docs/LangRef.rst
The file was addedllvm/test/Transforms/InstSimplify/named-vector-shuffle-reverse.ll
Commit 176379e0c8f9dbde2b357fb3b6a6802b83282e71 by zinenko
[mlir] Use the interface-based translation for LLVM "intrinsic" dialects

Port the translation of five dialects that define LLVM IR intrinsics
(LLVMAVX512, LLVMArmNeon, LLVMArmSVE, NVVM, ROCDL) to the new dialect
interface-based mechanism. This allows us to remove individual translations
that were created for each of these dialects and just use one common
MLIR-to-LLVM-IR translation that potentially supports all dialects instead,
based on what is registered and including any combination of translatable
dialects. This removal was one of the main goals of the refactoring.

To support the addition of GPU-related metadata, the translation interface is
extended with the `amendOperation` function that allows the interface
implementation to post-process any translated operation with dialect attributes
from the dialect for which the interface is implemented regardless of the
operation's dialect. This is currently applied to "kernel" functions, but can
be used to construct other metadata in dialect-specific ways without
necessarily affecting operations.

Depends On D96591, D96504

Reviewed By: nicolasvasilache

Differential Revision: https://reviews.llvm.org/D96592
The file was addedmlir/include/mlir/Target/LLVMIR/Dialect/LLVMAVX512/LLVMAVX512ToLLVMIRTranslation.h
The file was modifiedmlir/include/mlir/Target/LLVMIR/Dialect/LLVMIR/LLVMToLLVMIRTranslation.h
The file was addedmlir/lib/Target/LLVMIR/Dialect/LLVMAVX512/LLVMAVX512ToLLVMIRTranslation.cpp
The file was modifiedmlir/tools/mlir-tblgen/LLVMIRConversionGen.cpp
The file was addedmlir/lib/Target/LLVMIR/Dialect/ROCDL/CMakeLists.txt
The file was addedmlir/lib/Target/LLVMIR/Dialect/NVVM/CMakeLists.txt
The file was modifiedmlir/include/mlir/Target/LLVMIR/LLVMTranslationInterface.h
The file was modifiedmlir/include/mlir/InitAllTranslations.h
The file was removedmlir/lib/Target/LLVMIR/LLVMAVX512Intr.cpp
The file was removedmlir/lib/Target/LLVMIR/LLVMArmNeonIntr.cpp
The file was modifiedmlir/include/mlir/Dialect/LLVMIR/LLVMOpBase.td
The file was modifiedmlir/lib/Target/CMakeLists.txt
The file was modifiedmlir/include/mlir/Target/LLVMIR/ModuleTranslation.h
The file was modifiedmlir/lib/Target/LLVMIR/Dialect/CMakeLists.txt
The file was modifiedmlir/test/lib/Transforms/CMakeLists.txt
The file was modifiedmlir/lib/Target/LLVMIR/ModuleTranslation.cpp
The file was modifiedmlir/test/Target/avx512.mlir
The file was modifiedmlir/examples/standalone/test/Standalone/standalone-translate.mlir
The file was removedmlir/include/mlir/Target/NVVMIR.h
The file was addedmlir/lib/Target/LLVMIR/Dialect/LLVMArmNeon/CMakeLists.txt
The file was addedmlir/lib/Target/LLVMIR/Dialect/LLVMArmSVE/LLVMArmSVEToLLVMIRTranslation.cpp
The file was addedmlir/include/mlir/Target/LLVMIR/Dialect/NVVM/NVVMToLLVMIRTranslation.h
The file was modifiedmlir/test/Target/arm-neon.mlir
The file was modifiedmlir/test/Target/arm-sve.mlir
The file was modifiedmlir/tools/mlir-rocm-runner/mlir-rocm-runner.cpp
The file was modifiedmlir/include/mlir/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.h
The file was modifiedmlir/lib/Target/LLVMIR/ConvertToLLVMIR.cpp
The file was addedmlir/lib/Target/LLVMIR/Dialect/LLVMArmNeon/LLVMArmNeonToLLVMIRTranslation.cpp
The file was modifiedmlir/include/mlir/Target/LLVMIR.h
The file was modifiedmlir/test/Target/rocdl.mlir
The file was addedmlir/lib/Target/LLVMIR/Dialect/ROCDL/ROCDLToLLVMIRTranslation.cpp
The file was addedmlir/lib/Target/LLVMIR/Dialect/LLVMAVX512/CMakeLists.txt
The file was removedmlir/lib/Target/LLVMIR/LLVMArmSVEIntr.cpp
The file was removedmlir/include/mlir/Target/ROCDLIR.h
The file was removedmlir/lib/Target/LLVMIR/ConvertToNVVMIR.cpp
The file was modifiedmlir/test/lib/Transforms/TestConvertGPUKernelToCubin.cpp
The file was modifiedmlir/lib/Target/LLVMIR/Dialect/LLVMIR/LLVMToLLVMIRTranslation.cpp
The file was addedmlir/include/mlir/Target/LLVMIR/Dialect/LLVMArmSVE/LLVMArmSVEToLLVMIRTranslation.h
The file was addedmlir/lib/Target/LLVMIR/Dialect/LLVMArmSVE/CMakeLists.txt
The file was modifiedmlir/include/mlir/Dialect/LLVMIR/LLVMOps.td
The file was addedmlir/include/mlir/Target/LLVMIR/Dialect/LLVMArmNeon/LLVMArmNeonToLLVMIRTranslation.h
The file was addedmlir/lib/Target/LLVMIR/Dialect/NVVM/NVVMToLLVMIRTranslation.cpp
The file was modifiedmlir/tools/mlir-cuda-runner/mlir-cuda-runner.cpp
The file was modifiedmlir/test/lib/Transforms/TestConvertGPUKernelToHsaco.cpp
The file was removedmlir/lib/Target/LLVMIR/ConvertToROCDLIR.cpp
The file was modifiedmlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td
The file was addedmlir/include/mlir/Target/LLVMIR/Dialect/ROCDL/ROCDLToLLVMIRTranslation.h
The file was modifiedmlir/test/Target/nvvmir.mlir
Commit 50c19b4c11ec9946fca536b9940680311726d2ef by llvm-dev
Fix MSVC natvis visualisation of llvm::FixedVectorTyID and ScalableVectorTyID

VectorTyID was replaced with FixedVectorTyID and ScalableVectorTyID
The file was modifiedllvm/utils/LLVMVisualizers/llvm.natvis
Commit 5fe15934388f9ce7b3c564eb48d2fe8bafea14cf by kerry.mclaughlin
[LoopVectorizer] Require no-signed-zeros-fp-math=true for fmin/fmax

Currently, setting the `no-nans-fp-math` attribute to true will allow
loops with fmin/fmax to vectorize, though we should be requiring that
`no-signed-zeros-fp-math` is also set.

This patch adds the check for no-signed-zeros at the function level and includes
tests to make sure we don't vectorize functions with only one of the attributes
associated.

Reviewed By: spatel

Differential Revision: https://reviews.llvm.org/D96604
The file was modifiedllvm/include/llvm/Analysis/IVDescriptors.h
The file was modifiedllvm/test/Transforms/LoopVectorize/X86/reduction-fastmath.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/minmax_reduction.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/float-minmax-instruction-flag.ll
The file was modifiedllvm/lib/Analysis/IVDescriptors.cpp
Commit eefd620a2572d1a640b9085ea60dbf37e680159a by kbobyrev
[llvm] NFC: Cleanup llvm-yaml-numeric-parser-fuzzer

* Use static variables instead of non-trivially destructible global ones.
* Remove unused header.

Differential Revision: https://reviews.llvm.org/D91600
The file was modifiedllvm/tools/llvm-yaml-numeric-parser-fuzzer/yaml-numeric-parser-fuzzer.cpp
Commit 94828afd0a178d00abec87143b48fe0d7c063198 by james.henderson
[llvm-nm] Tidy up error messages

This adds colons to separate the file name from the message, removes a
duplicate space, and removes a trailing full stop from some messages.
These help bring the error messages into line with other tools, as well
as making all llvm-nm message more self-consistent.

Differential Revision: https://reviews.llvm.org/D96601

Reviewed by: Higuoxing, rupprecht, MaskRay
The file was modifiedllvm/test/tools/llvm-nm/dynamic.test
The file was modifiedllvm/test/Object/nm-tapi-invalids.test
The file was modifiedllvm/test/Object/nm-shared-object.test
The file was modifiedllvm/test/tools/llvm-nm/invalid-input.test
The file was modifiedllvm/test/Object/macho-invalid.test
The file was modifiedllvm/test/Object/nm-archive.test
The file was modifiedllvm/tools/llvm-nm/llvm-nm.cpp
Commit 37c89803d860c6dd954cda1480dae6917f006972 by james.henderson
[llvm-nm][test] Add additional test coverage for llvm-nm options

Some of these options have a degree of incidental coverage, or are for
Mach-O only. This patch adds dedicated ELF (where applicable) coverage.

Differential Revision: https://reviews.llvm.org/D96602

Reviewed by: rupprecht, Higuoxing
The file was addedllvm/test/tools/llvm-nm/reverse-sort.test
The file was addedllvm/test/tools/llvm-nm/X86/bitcode.test
The file was addedllvm/test/tools/llvm-nm/format-bsd.test
The file was addedllvm/test/tools/llvm-nm/just-symbol-name.test
The file was addedllvm/test/tools/llvm-nm/defined-only.test
Commit 1d6f08e61d9771baf5381198ac5d306f6cbcd302 by zinenko
[mlir] use new cmake targets in mlir-*-runner
The file was modifiedmlir/tools/mlir-rocm-runner/CMakeLists.txt
The file was modifiedmlir/tools/mlir-cuda-runner/CMakeLists.txt
Commit 65292fe3a2101a5ce9b01f089cdc077320e53b13 by llvm-dev
[X86] Add SSE2+SSE3 common check prefix to psubus tests

Noticed by @pengfei on D96703
The file was modifiedllvm/test/CodeGen/X86/psubus.ll
Commit 6c330f0df8da7f6b94f511fc3f5573003fdda093 by james.henderson
[debuginfo-tests] Remove explicit checks for Python 3

LLVM has a minimum requirement of python 3.6 now, and Python is
explicitly checked for in the LLVM CMakeLists.txt, so this check is no
longer needed here.

Differential Revision: https://reviews.llvm.org/D96499

Reviewed by: aprantl
The file was modifieddebuginfo-tests/lit.cfg.py
The file was modifieddebuginfo-tests/lit.site.cfg.py.in
The file was modifieddebuginfo-tests/CMakeLists.txt
Commit d6236524993e81904e75e9ddc3d497230b858a89 by james.henderson
[debuginfo-tests] Remove some unused config variables

Differential Revision: https://reviews.llvm.org/D96500

Reviewed by: aprantl
The file was modifieddebuginfo-tests/lit.site.cfg.py.in
Commit b52e6c58911f60eebd20b59bc89d7a230aececab by caroline.concatto
[CostModel]Add cost model for experimental.vector.reverse

This patch uses the function getShuffleCost with SK_Reverse to compute the cost
for experimental.vector.reverse.
For scalable vector type, it adds a table will the legal types on
AArch64TTIImpl::getShuffleCost to not assert in BasicTTIImpl::getShuffleCost,
and for fixed vector, it relies on the existing cost model in BasicTTIImpl.

Depends on D94883

Differential Revision: https://reviews.llvm.org/D95603
The file was addedllvm/test/Analysis/CostModel/AArch64/sve-getIntrinsicInstrCost-vector-reverse.ll
The file was addedllvm/test/Analysis/CostModel/AArch64/getIntrinsicInstrCost-vector-reverse.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
The file was modifiedllvm/include/llvm/CodeGen/BasicTTIImpl.h
Commit e8b9da712f579cbd18f5b993e984c18c501f4802 by james.henderson
[debuginfo-tests] Delete unused/duplicate imports

Differential Revision: https://reviews.llvm.org/D96502

Reviewed by: aprantl
The file was modifieddebuginfo-tests/lit.cfg.py
Commit 3842d4b6791f6fbd67a1d12806f05a05654728cf by tpopp
Make shape.is_broadcastable/shape.cstr_broadcastable nary

This corresponds with the previous work to make shape.broadcast nary.
Additionally, simplify the ConvertShapeConstraints pass. It now doesn't
lower an implicit shape.is_broadcastable. This is still the same in
combination with shape-to-standard when the 2 passes are used in either
order.

Differential Revision: https://reviews.llvm.org/D96401
The file was modifiedmlir/test/Conversion/ShapeToStandard/convert-shape-constraints.mlir
The file was modifiedmlir/lib/Conversion/ShapeToStandard/ConvertShapeConstraints.cpp
The file was modifiedmlir/lib/Dialect/Shape/IR/ShapeCanonicalization.td
The file was modifiedmlir/test/Dialect/Shape/invalid.mlir
The file was modifiedmlir/lib/Dialect/Shape/IR/Shape.cpp
The file was modifiedmlir/lib/Conversion/ShapeToStandard/ShapeToStandard.td
The file was modifiedmlir/lib/Conversion/ShapeToStandard/ShapeToStandard.cpp
The file was modifiedmlir/include/mlir/Dialect/Shape/IR/ShapeOps.td
The file was modifiedmlir/test/Conversion/ShapeToStandard/shape-to-standard.mlir
Commit 0a98efb049393a579a1e44a68bfa886475ea672c by david.green
[ARM] Add some basic Min/Max costs

This adds basic MVE costs for SMIN/SMAX/UMIN/UMAX, as well as MINNUM and
MAXNUM representing fmin and fmax. It tightens up the costs, not using a
ICmp+Select cost.

Differential Revision: https://reviews.llvm.org/D96603
The file was modifiedllvm/test/Analysis/CostModel/ARM/mve-minmax.ll
The file was modifiedllvm/test/Analysis/CostModel/ARM/intrinsic-cost-kinds.ll
The file was modifiedllvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
Commit 99dbc0fa76010f3dcbb4c1b63bfa410c1ad44e7c by caroline.concatto
[LangRef] Increase size of title underline for experimental.vector.reverse
The file was modifiedllvm/docs/LangRef.rst
Commit ca23b2c8ed2733f0584ca8bc0514b173938f1cdc by flo
[AArch64] Move machine bundle unpacking to PreEmit2 phase.

This patch adjusts the placement of the bundle unpacking to just before
code emission. In particular, this means bundle unpacking happens AFTER
the machine outliner. With the previous position, the machine outliner
may outline parts of a bundle, which breaks them up.

This is an issue for BLR_RVMARKER handling, as illustrated by the
rvmarker-pseudo-expansion-and-outlining.mir test case. The machine
outliner should not break up the bundles created during pseudo
expansion.

This should fix PR49082.

Reviewed By: SjoerdMeijer

Differential Revision: https://reviews.llvm.org/D96294
The file was modifiedllvm/test/CodeGen/AArch64/rvmarker-pseudo-expansion-and-outlining.mir
The file was modifiedllvm/test/CodeGen/AArch64/O3-pipeline.ll
The file was modifiedllvm/test/CodeGen/AArch64/arm64-opt-remarks-lazy-bfi.ll
The file was modifiedllvm/test/CodeGen/AArch64/O0-pipeline.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64TargetMachine.cpp
Commit 7549524ac541e0366f16d2bb9f37de7607fdde29 by mtrofin
[NFC] Remove spurious ';' on return line in python code
The file was modifiedllvm/utils/UpdateTestChecks/common.py
Commit e47f21da6153159809f84aa3d6b7d78113e7842f by llvm-dev
[DAG] visitVSELECT - move OpLHS == LHS into inner if() in USUBSAT matching. NFCI.

This will be necessary for the update of D25987 where we'll need to match OpLHS against other ops.
The file was modifiedllvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Commit 6c5f17e701ff586d69a43b3cfc1e25314b84892d by sam.mccall
[clangd] Delay binding LSP methods until initialize. NFC

This is NFC because the MessageHandler refused to dispatch to them until the
server is initialized anyway.

This is a more natural time to bind them - it's when they become callable, and
it's when client capabalities are available and server ones can be set.

One module-lifecycle function will be responsible for all three.

Differential Revision: https://reviews.llvm.org/D96608
The file was modifiedclang-tools-extra/clangd/ClangdLSPServer.h
The file was modifiedclang-tools-extra/clangd/ClangdLSPServer.cpp
Commit 381a65fa066171977bc9119432917a1444f99f87 by jpienaar
[mlir] Add clone method to ShapedType

Allow clients to create a new ShapedType of the same "container" type
but with different element or shape. First use case is when refining
shape during shape inference without needing to consider which
ShapedType is being refined.

Differential Revision: https://reviews.llvm.org/D96682
The file was addedmlir/unittests/IR/ShapedTypeTest.cpp
The file was modifiedmlir/include/mlir/IR/BuiltinTypes.h
The file was modifiedmlir/unittests/IR/CMakeLists.txt
The file was modifiedmlir/lib/IR/BuiltinTypes.cpp
Commit 02413b097e72a3aab17e0504af135a95c0d300a1 by i
[CMake] Delete LLVM_RUNTIME_BUILD_ID_LINK_TARGETS

Announcement: https://lists.llvm.org/pipermail/llvm-dev/2021-February/148446.html

Differential Revision: https://reviews.llvm.org/D96360
The file was modifiedllvm/runtimes/CMakeLists.txt
The file was removedllvm/runtimes/llvm-strip-link.in
The file was modifiedclang/cmake/caches/Fuchsia-stage2.cmake
Commit 09b832e74f6c71c2023a3094727bc5c24c639985 by Adrian Prantl
Support emitting complex expressions that include entry values

This patch enables AsmPrinter support for complex expression with
entry values. It shouldn't AsmPrinter's call whether these are safe or
not but the pass who introduces the DW_OP_LLVM_entry_value. This patch
on its own has no effect on clang.

Differential Revision: https://reviews.llvm.org/D96559
The file was addedllvm/test/DebugInfo/MIR/X86/complex-entryvalue.mir
The file was modifiedllvm/lib/CodeGen/AsmPrinter/DwarfExpression.cpp
Commit 3b2f19d0bc2803697526191a8a607efa0b38f7e4 by johannes
[OpenMP][NFC] Pre-commit test changes regarding PR48933

This will highlight the effective changes in subsequent commits.

Reviewed By: ABataev

Differential Revision: https://reviews.llvm.org/D95903
The file was modifiedclang/test/OpenMP/nvptx_unsupported_type_messages.cpp
Commit f9286b434b764b366f1aad9249c04e7741ed5518 by johannes
[OpenMP] Attribute target diagnostics properly

Type errors in function declarations were not (always) diagnosed prior
to this patch. Furthermore, certain remarks did not get associated
properly which caused them to be emitted multiple times.

Reviewed By: JonChesterfield

Differential Revision: https://reviews.llvm.org/D95912
The file was modifiedclang/include/clang/Sema/Sema.h
The file was modifiedclang/test/OpenMP/nvptx_unsupported_type_messages.cpp
The file was modifiedclang/lib/Sema/Sema.cpp
The file was modifiedclang/lib/Sema/SemaDecl.cpp
The file was modifiedclang/lib/Sema/SemaOpenMP.cpp
The file was modifiedclang/lib/Sema/SemaExpr.cpp
Commit 1dd66e6111a8247c6c7931143251c0cf1442b905 by johannes
[OpenMP] Delay more diagnostics of potentially non-emitted code

Even code in target and declare target regions might not be emitted.
With this patch we delay more diagnostics and use laziness and linkage
to determine if a function is emitted (for the device). Note that we
still eagerly emit diagnostics for target regions, unfortunately, see
the TODO for the reason.

This hopefully fixes PR48933.

Reviewed By: JonChesterfield

Differential Revision: https://reviews.llvm.org/D95928
The file was modifiedclang/test/OpenMP/nvptx_allocate_messages.cpp
The file was modifiedclang/test/OpenMP/nvptx_target_exceptions_messages.cpp
The file was modifiedclang/lib/Sema/SemaDecl.cpp
The file was modifiedclang/lib/Sema/SemaOpenMP.cpp
The file was modifiedclang/test/OpenMP/nvptx_unsupported_type_messages.cpp
Commit c465429f286f50e52a8d2b3b39f38344f3381cce by i
[llvm-objcopy] Delete --build-id-link-{dir,input,output}

The few options are niche. They solved a problem which was traditionally solved
with more shell commands (`llvm-readelf -n` fetches the Build ID. Then
`ln` is used to hard link the file to a directory derived from the Build ID.)

Due to limitation, they are no longer used by Fuchsia and they don't appear to
be used elsewhere (checked with Google Search and Debian Code Search). So delete
them without a transition period.

Announcement: https://lists.llvm.org/pipermail/llvm-dev/2021-February/148446.html

Differential Revision: https://reviews.llvm.org/D96310
The file was modifiedllvm/tools/llvm-objcopy/CopyConfig.h
The file was removedllvm/test/tools/llvm-objcopy/ELF/no-build-id.test
The file was removedllvm/test/tools/llvm-objcopy/ELF/no-build-id-no-notes.test
The file was modifiedllvm/tools/llvm-objcopy/wasm/WasmObjcopy.cpp
The file was removedllvm/test/tools/llvm-objcopy/ELF/build-id-link-dir.test
The file was modifiedllvm/docs/ReleaseNotes.rst
The file was modifiedllvm/tools/llvm-objcopy/MachO/MachOObjcopy.cpp
The file was modifiedllvm/docs/CommandGuide/llvm-objcopy.rst
The file was removedllvm/test/tools/llvm-objcopy/ELF/bad-build-id.test
The file was modifiedllvm/tools/llvm-objcopy/ELF/ELFObjcopy.cpp
The file was modifiedllvm/tools/llvm-objcopy/CopyConfig.cpp
The file was modifiedllvm/tools/llvm-objcopy/COFF/COFFObjcopy.cpp
The file was modifiedllvm/tools/llvm-objcopy/ObjcopyOpts.td
Commit 5cf9292ce341d2002f5d6e0189d54e29f9e71afe by Stanislav.Mekhanoshin
[AMDGPU] Add two TSFlags: IsAtomicNoRtn and IsAtomicRtn

We are using AtomicNoRet map in multiple places to determine
if an instruction atomic, rtn or nortn atomic. This method
does not work always since we have some instructions which
only has rtn or nortn version.

One such instruction is ds_wrxchg_rtn_b32 which does not have
nortn version. This has caused changes in memory legalizer
tests.

Differential Revision: https://reviews.llvm.org/D96639
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.h
The file was modifiedllvm/test/CodeGen/AMDGPU/memory-legalizer-local-system.ll
The file was modifiedllvm/lib/Target/AMDGPU/BUFInstructions.td
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.td
The file was modifiedllvm/lib/Target/AMDGPU/DSInstructions.td
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrFormats.td
The file was modifiedllvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
The file was modifiedllvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/memory-legalizer-local-agent.ll
The file was modifiedllvm/lib/Target/AMDGPU/FLATInstructions.td
The file was modifiedllvm/lib/Target/AMDGPU/MIMGInstructions.td
The file was modifiedllvm/test/CodeGen/AMDGPU/memory-legalizer-local-workgroup.ll
The file was modifiedllvm/lib/Target/AMDGPU/SIDefines.h
The file was modifiedllvm/lib/Target/AMDGPU/SIFormMemoryClauses.cpp
Commit 715dc556b782f718ce1815aaf5c58626f5fe839c by benny.kra
[lto] Enable new PM when the PM config is non-empty

This restores the behavior before 964f8103c58d, which broke 2 tests:
  LLVM :: tools/llvm-lto2/X86/pipeline.ll
  lld :: ELF/lto/ltopasses-custom.ll
The file was modifiedllvm/lib/LTO/LTOBackend.cpp
Commit 22a52dfddcefad4f275eb8ad1cc0e200074c2d8a by Duncan P. N. Exon Smith
TransformUtils: Fix metadata handling in CloneModule (and improve CloneFunctionInto)

This commit fixes how metadata is handled in CloneModule to be sound,
and improves how it's handled in CloneFunctionInto (although the latter
is still awkward when called within a module).

Ruiling Song pointed out in PR48841 that CloneModule was changed to
unsoundly use the RF_ReuseAndMutateDistinctMDs flag (renamed in
fa35c1f80f0ea080a7cbc581416929b0a654f25c for clarity). This flag papered
over a crash caused by other various changes made to CloneFunctionInto
over the past few years that made it unsound to use cloning between
different modules.

(This commit partially addresses PR48841, fixing the repro from
preprocessed source but not textual IR. MDNodeMapper::mapDistinctNode
became unsound in df763188c9a1ecb1e7e5c4d4ea53a99fbb755903 and this
commit does not address that regression.)

RF_ReuseAndMutateDistinctMDs is designed for the IRMover to use,
avoiding unnecessary clones of all referenced metadata when linking
between modules (with IRMover, the source module is discarded after
linking). It never makes sense to use when you're not discarding the
source. This commit drops its incorrect use in CloneModule.

Sadly, the right thing to do with metadata when cloning a function is
complicated, and this patch doesn't totally fix it.

The first problem is that there are two different types of referenceable
metadata and it's not obvious what to with one of them when remapping.

- `!0 = !{!1}` is metadata's version of a constant. Programatically it's
  called "uniqued" (probably a better term would be "constant") because,
  like `ConstantArray`, it's stored in uniquing tables. Once it's
  constructed, it's illegal to change its arguments.
- `!0 = distinct !{!1}` is a bit closer to a global variable. It's legal
  to change the operands after construction.

What should be done with distinct metadata when cloning functions within
the same module?

- Should new, cloned nodes be created?
- Should all references point to the same, old nodes?

The answer depends on whether that metadata is effectively owned by a
function.

And that's the second problem. Referenceable metadata's ownership model
is not clear or explicit. Technically, it's all stored on an
LLVMContext. However, any metadata that is `distinct`, that transitively
references a `distinct` node, or that transitively references a
GlobalValue is specific to a Module and is effectively owned by it. More
specifically, some metadata is effectively owned by a specific Function
within a module.

Effectively function-local metadata was introduced somewhere around
c10d0e5ccd12f049bddb24dcf8bbb7fbbc6c68f2, which made it illegal for two
functions to share a DISubprogram attachment.

When cloning a function within a module, you need to clone the
function-local debug info and suppress cloning of global debug info (the
status quo suppresses cloning some global debug info but not all). When
cloning a function to a new/different module, you need to clone all of
the debug info.

Here's what I think we should do (eventually? soon? not this patch
though):
- Distinguish explicitly (somehow) between pure constant metadata owned
  by the LLVMContext, global metadata owned by the Module, and local
  metadata owned by a GlobalValue (such as a function).
- Update CloneFunctionInto to trigger cloning of all "local" metadata
  (only), perhaps by adding a bit to RemapFlag. Alternatively, split
  out a separate function CloneFunctionMetadataInto to prime the
  metadata map that callers are updated to call ahead of time as
  appropriate.

Here's the somewhat more isolated fix in this patch:
- Converted the `ModuleLevelChanges` parameter to `CloneFunctionInto` to
  an enum called `CloneFunctionChangeType` that is one of
  LocalChangesOnly, GlobalChanges, DifferentModule, and ClonedModule.
- The code maintaining the "functions uniquely own subprograms"
  invariant is now only active in the first two cases, where a function
  is being cloned within a single module. That's necessary because this
  code inhibits cloning of (some) "global" metadata that's effectively
  owned by the module.
- The code maintaining the "all compile units must be explicitly
  referenced by !llvm.dbg.cu" invariant is now only active in the
  DifferentModule case, where a function is being cloned into a new
  module in isolation.
- CoroSplit.cpp's call to CloneFunctionInto in CoroCloner::create
  uses LocalChangeOnly, since fa635d730f74f3285b77cc1537f1692184b8bf5b
  only set `ModuleLevelChanges` to trigger cloning of local metadata.
- CloneModule drops its unsound use of RF_ReuseAndMutateDistinctMDs
  and special handling of !llvm.dbg.cu.
- Fixed some outdated header docs and left a couple of FIXMEs.

Differential Revision: https://reviews.llvm.org/D96531
The file was modifiedllvm/lib/Transforms/Utils/CloneModule.cpp
The file was modifiedllvm/lib/Target/AMDGPU/R600OpenCLImageTypeLoweringPass.cpp
The file was modifiedllvm/include/llvm/Transforms/Utils/Cloning.h
The file was modifiedllvm/lib/Transforms/Coroutines/CoroSplit.cpp
The file was modifiedllvm/unittests/Transforms/Utils/CloningTest.cpp
The file was modifiedllvm/lib/Transforms/Utils/CloneFunction.cpp
The file was modifiedllvm/lib/Transforms/IPO/Attributor.cpp
The file was modifiedllvm/lib/ExecutionEngine/Orc/IndirectionUtils.cpp
Commit 4d700fb0603e6fbdd6f597443b29414f7e133912 by sam.mccall
[clangd] Pass raw client capabilities to modules. NFC
The file was modifiedclang-tools-extra/clangd/Module.h
The file was modifiedclang-tools-extra/clangd/Protocol.h
The file was modifiedclang-tools-extra/clangd/unittests/ClangdLSPServerTests.cpp
The file was modifiedclang-tools-extra/clangd/ClangdLSPServer.cpp
The file was modifiedclang-tools-extra/clangd/Protocol.cpp
Commit 328261019f50a76b11fa625739cbf32ceb2ce2f7 by dimitry
Define new/delete in libc++ when using libcxxrt

Always turn on LIBCXX_ENABLE_NEW_DELETE_DEFINITIONS, if libcxxrt is used
as the C++ ABI library, since libcxxrt does not provide the full set
ofnew and delete operators. In particular, the aligned versions of these
operators are completely missing. This primarily addresses builds on
FreeBSD, as this platform uses libcxxrt by default.

Also, attempt to provide a FreeBSD.cmake cache file, with hopefully sane
settings, partially copied from the Apple.cmake cache file. This needs
more work, probably some additions to ci build scripts (although I am
not aware of any 'official' FreeBSD build bots).

Reviewed By: ldionne, #libc

Differential Revision: https://reviews.llvm.org/D96720
The file was modifiedlibcxx/cmake/Modules/HandleLibCXXABI.cmake
The file was addedlibcxx/cmake/caches/FreeBSD.cmake
Commit 378941f611ab46b985721874081df88bdf3b7cb1 by spatel
[ValueTracking] add scan limit for assumes

In the motivating example from https://llvm.org/PR49171 and
reduced test here, we would unroll and clone assumes so much
that compile-time effectively became infinite while analyzing
all of those assumes.
The file was addedllvm/test/Transforms/LoopUnroll/assume-timeout.ll
The file was modifiedllvm/lib/Analysis/ValueTracking.cpp
Commit 5d0d465ad4d25398519b85879d61fc126abd641c by Louis Dionne
[libc++] Mark __cpp_lib_constexpr_memory as being implemented
The file was modifiedlibcxx/test/std/language.support/support.limits/support.limits.general/memory.version.pass.cpp
The file was modifiedlibcxx/docs/FeatureTestMacroTable.rst
The file was modifiedlibcxx/include/version
The file was modifiedlibcxx/test/std/language.support/support.limits/support.limits.general/version.version.pass.cpp
The file was modifiedlibcxx/utils/generate_feature_test_macro_components.py
Commit c2123a82cd0076c548d2b8c2acc14408681d7f89 by omair.javaid
[LLDB] Skip TestMultipleTargets.py on Arm/AArch64 Linux

TestMultipleTargets.py fails randomly on Arm/AArch64 Linux buildbot with
no reasonable clues. I am marking it skipped for avoiding LLDB buildbot
failures due to this test.
The file was modifiedlldb/test/API/api/multiple-targets/TestMultipleTargets.py
Commit eb75f250feb6822d57be95e8535e28724cde6e9d by craig.topper
[RISCV][LegalizeTypes] Try to expand BITREVERSE before promoting if the promoted BITREVERSE would expand anyway.

If we're going to end up expanding anyway, we should do it early
so we don't create extra operations to handle the bytes added by
promotion.

Simlilar was done for BSWAP previously.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D96681
The file was modifiedllvm/test/CodeGen/RISCV/rv32Zbp.ll
The file was modifiedllvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
The file was modifiedllvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
The file was modifiedllvm/include/llvm/CodeGen/TargetLowering.h
The file was modifiedllvm/test/CodeGen/RISCV/rv64Zbp.ll
The file was modifiedllvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
Commit 7ba2e1c6011eeb1b91ce3f5d8fa7187b7518e77a by craig.topper
[RISCV] Add support for fixed vector floating point setcc.

This is annoying because the condition code legalization belongs
to LegalizeDAG, but our custom handler runs in Legalize vector ops
which occurs earlier.

This adds some of the mask binary operations so that we can combine
multiple compares that we need for expansion.

I've also fixed up RISCVISelDAGToDAG.cpp to handle copies of masks.

This patch contains a subset of the integer setcc patch as well.
That patch is dependent on the integer binary ops patch. I'll rebase
based on what order the patches go in.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D96567
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.cpp
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.h
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
The file was modifiedllvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
The file was addedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll