FailedChanges

Summary

  1. [mlir][Linalg] Fix padding related bugs. (details)
  2. [RISCV] Add support for fixed vector FMA. (details)
  3. [RISCV] Add support for splat fixed length build_vectors using RVV. (details)
  4. Revert "[Utils] Add a switch controlling prefix warnings in UpdateTestChecks" (details)
  5. [GWP-ASan] Add aligned allocations. (details)
  6. [RISCV] Use _COMMUTABLE fma pseudos for fixed vectors. (details)
  7. [lld-macho] Try to make ubsan happy (details)
  8. [dfsan] Refactor visitCallBase (details)
  9. [libomptarget][amdgcn] Fix language linkage post D95300, drop use of assert (details)
  10. [flang][NFC] Update comments. (details)
  11. [scudo/standalone] Use .arch_extension memtag, not mte (details)
  12. DebugInfo/Symbolize: Allow STT_NOTYPE/STT_GNU_IFUNC symbols for .symtab symbolization (details)
  13. [AArch64] Use '//' as comment string for MSVC assembly (details)
  14. Revert "[Test] Add failing test for PR49087" (details)
  15. [AArch64][GlobalISel] Support the 'returned' parameter attribute. (details)
  16. [CMake] [MinGW] Enable use of LLVM_USE_SANITIZER in a MinGW environment (details)
  17. [gn build] reformat all gn files (details)
  18. [SimpleLoopUnswitch] Don't non-trivially unswitch loops that are unsafe to clone (details)
  19. [ARM] One-off identity shuffle (details)
  20. [Verifier] Allow DW_TAG_class_type/DW_TAG_union_type to have no filename (details)
  21. [FileCheck] Default --allow-unused-prefixes to false (details)
  22. [test] Fix unused check prefixes (details)
  23. [flang][NFC] Add comment. (details)
  24. [NVPTX][NewPM] Re-enable NVVMReflectPass (details)
  25. AMDGPU/GlobalISel: Remove dead check prefixes (details)
  26. AMDGPU: Stop adding stack passed wide arguments to call conv handler (details)
  27. GlobalISel: Use correct calling convention in handleAssignments (details)
  28. [RISCV] Initial support of LoopVectorizer for RISC-V Vector. (details)
  29. Renovate CMake files in the `llvm-exegesis` tool. (details)
  30. Renovate CMake file for the `llvm-cfi-verify` tool (details)
  31. [flang][fir] Add OpaqueAttr. (details)
  32. [CUDA][HIP] Pass -fgpu-rdc to host clang -cc1 (details)
  33. Make sure a module file with errors produced via '-fallow-pcm-with-compiler-errors' can be loaded when using implicit modules (details)
  34. Revert "Renovate CMake files in the `llvm-exegesis` tool." (details)
  35. [SPARC] Recognize and handle the %lm(sym) operator (details)
  36. Fix failure in cuda-external-tools.cu (details)
  37. [MLIR][NFC] Fix std.copysign op documentation (details)
  38. [TableGen] Use return value from EmitVBRValue instead of calling GetVBRSize on the same value. Consistently use unsigned for child sizes. NFCI (details)
  39. [MC][WebAssembly] Fix provisional values for data alias relocations (details)
Commit d57a305fdf312920e38500306b7a945c341f73d9 by nicolas.vasilache
[mlir][Linalg] Fix padding related bugs.

This revision fixes the fact that the padding transformation did not have enough information to set the proper type for the padding value.
Additionally, the verifier for Yield in the presence of PadTensorOp is fixed to properly report incorrect number of results or operands. Previously, the error would be silently ignored which made the core issue difficult to debug.

Differential Revision: https://reviews.llvm.org/D96264
The file was modifiedmlir/test/Dialect/Linalg/invalid.mlir (diff)
The file was modifiedmlir/test/Dialect/Linalg/tile-and-pad-tensors.mlir (diff)
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/Transforms.cpp (diff)
The file was modifiedmlir/lib/Dialect/Linalg/IR/LinalgOps.cpp (diff)
The file was modifiedmlir/test/lib/Transforms/TestLinalgTransforms.cpp (diff)
The file was modifiedmlir/include/mlir/Dialect/Linalg/Transforms/Transforms.h (diff)
Commit b8d719fbe81c88ec9e8c9dbe406c1b7de4c1ba05 by craig.topper
[RISCV] Add support for fixed vector FMA.

Follow up to D95705. Does not include the commuting support from D95800.

Differential Revision: https://reviews.llvm.org/D96103
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.cpp (diff)
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.h (diff)
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td (diff)
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll (diff)
Commit 8d8cafa32e83e9557980b9906a71d0890b860c76 by craig.topper
[RISCV] Add support for splat fixed length build_vectors using RVV.

Building on the fixed vector support from D95705

I've added ISD nodes for vmv.v.x and vfmv.v.f and switched to
lowering the intrinsics to it. This allows us to share the same
isel patterns for both.

This doesn't handle splats of i64 on RV32 yet. The build_vector
gets converted to a vXi32 build_vector+bitcast during type
legalization. Not sure the best way to handle this at the moment.

Differential Revision: https://reviews.llvm.org/D96108
The file was addedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-splat-rv64.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td (diff)
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.cpp (diff)
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.h (diff)
The file was addedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-splat.ll
The file was addedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-splat-rv32.ll
Commit f31ea86c808cbd841a348e35eb548b0046c8fdf7 by mtrofin
Revert "[Utils] Add a switch controlling prefix warnings in UpdateTestChecks"

This reverts commit 87f8a08ce36e5bc72f11129d2cf36b5848f86f63.
The file was modifiedllvm/test/tools/UpdateTestChecks/update_llc_test_checks/common-label-different-bodies.test (diff)
The file was modifiedllvm/utils/UpdateTestChecks/common.py (diff)
Commit 3d8823b8e48a3f064b1e2dd52881b3ac581f6f2b by 31459023+hctim
[GWP-ASan] Add aligned allocations.

Adds a new allocation API to GWP-ASan that handles size+alignment
restrictions.

Reviewed By: cryptoad, eugenis

Differential Revision: https://reviews.llvm.org/D94830
The file was modifiedcompiler-rt/lib/gwp_asan/common.cpp (diff)
The file was modifiedcompiler-rt/lib/gwp_asan/tests/alignment.cpp (diff)
The file was removedcompiler-rt/lib/gwp_asan/utilities.cpp
The file was modifiedcompiler-rt/lib/gwp_asan/options.inc (diff)
The file was modifiedcompiler-rt/lib/gwp_asan/guarded_pool_allocator.cpp (diff)
The file was modifiedcompiler-rt/lib/scudo/standalone/combined.h (diff)
The file was modifiedcompiler-rt/lib/gwp_asan/guarded_pool_allocator.h (diff)
The file was modifiedcompiler-rt/lib/gwp_asan/tests/basic.cpp (diff)
The file was modifiedcompiler-rt/lib/gwp_asan/crash_handler.cpp (diff)
The file was modifiedcompiler-rt/lib/gwp_asan/utilities.h (diff)
The file was modifiedcompiler-rt/lib/gwp_asan/tests/crash_handler_api.cpp (diff)
The file was modifiedcompiler-rt/lib/gwp_asan/common.h (diff)
The file was modifiedcompiler-rt/lib/gwp_asan/CMakeLists.txt (diff)
Commit b49aaed8c750c8e6c4ece9a7f2b76e14b32c5484 by craig.topper
[RISCV] Use _COMMUTABLE fma pseudos for fixed vectors.

This matches what we do in the VLMAX SDNode patterns.
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll (diff)
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td (diff)
Commit ac9dd247da5a54119851cd766e4e9aa3a2be8a19 by jezng
[lld-macho] Try to make ubsan happy

Summary: We should avoid passing a null pointer to memcpy.
The file was modifiedlld/MachO/UnwindInfoSection.cpp (diff)
Commit 64b448b983b130bb59b1328473da0e9289d2e39d by jianzhouzh
[dfsan] Refactor visitCallBase

To simplify the review of https://reviews.llvm.org/D95835.

Reviewed-by: morehouse

Differential Revision: https://reviews.llvm.org/D96177
The file was modifiedllvm/lib/Transforms/Instrumentation/DataFlowSanitizer.cpp (diff)
Commit 2fa4186d4e1c0c5ce05efb4275f94bb7c2538dda by jonathanchesterfield
[libomptarget][amdgcn] Fix language linkage post D95300, drop use of assert
The file was modifiedopenmp/libomptarget/deviceRTLs/amdgcn/src/target_impl.hip (diff)
Commit bdf3ad582e50b06863026b72a1371353a257fc56 by eschweitz
[flang][NFC] Update comments.
The file was modifiedflang/include/flang/Optimizer/Dialect/FIRDialect.h (diff)
Commit 4c9adbb287e7e6cfea866b3c3254b50f21e5ce1f by mcgrathr
[scudo/standalone] Use .arch_extension memtag, not mte

GNU binutils accepts only `.arch_extension memtag` while Clang
accepts either that or `.arch_extension mte` to mean the same thing.

Reviewed By: pcc

Differential Revision: https://reviews.llvm.org/D95996
The file was modifiedcompiler-rt/lib/scudo/standalone/memtag.h (diff)
Commit 6d766c8bf9df3c22590a78c77879080736ad55ae by i
DebugInfo/Symbolize: Allow STT_NOTYPE/STT_GNU_IFUNC symbols for .symtab symbolization

In assembly files, omitting `.type foo,@function` is common. Such functions have
type `STT_NOTYPE` and llvm-symbolizer reports `??` for them.

An ifunc symbol usually has an associated resolver symbol which is defined at
the same address. Returning either one is fine for symbolization. The resolver
symbol may not end up in the symbol table if (object file) `.L` is used (linked
image) .symtab is stripped while .dynsym is retained.

This patch allows ELF STT_NOTYPE/STT_GNU_IFUNC symbols for .symtab symbolization.

I have left TODO in the test files for an unimplemented STT_FILE heuristic.

Differential Revision: https://reviews.llvm.org/D95916
The file was addedllvm/test/DebugInfo/Symbolize/ELF/symtab-ifunc.s
The file was addedllvm/test/DebugInfo/Symbolize/ELF/symtab-ignored.s
The file was modifiedllvm/lib/DebugInfo/Symbolize/SymbolizableObjectFile.cpp (diff)
The file was addedllvm/test/DebugInfo/Symbolize/ELF/symtab-file.s
The file was addedllvm/test/DebugInfo/Symbolize/ELF/symtab-notype.s
Commit 71c29b4cf3fb2b5610991bfbc12b8bda97d60005 by martin
[AArch64] Use '//' as comment string for MSVC assembly

As the actual MSVC toolset doesn't use the GAS-style assembly that
Clang/LLVM produces and consumes, there's no reference for what
string to use for e.g. comments when building with a MSVC triple.

This frees up the use of semicolon as separator string, just like
was done for GNU targets in 23413195649d0cf6f3860ae8b5fb115b35032075.
(Previously, both the separator and comment strings were set to
the same, a semicolon.)

Compiler-rt extensively uses separator chars in its assembly,
and that assembly should be buildable with clang-cl for MSVC too.

Differential Revision: https://reviews.llvm.org/D96259
The file was modifiedllvm/test/CodeGen/AArch64/reloc-specifiers.mir (diff)
The file was modifiedllvm/test/MC/AArch64/coff-relocations.s (diff)
The file was modifiedllvm/test/CodeGen/AArch64/seh_funclet_x1.ll (diff)
The file was modifiedllvm/test/CodeGen/AArch64/wineh-try-catch.ll (diff)
The file was modifiedllvm/test/CodeGen/AArch64/wineh-try-catch-nobase.ll (diff)
The file was modifiedllvm/test/CodeGen/AArch64/cfguard-checks.ll (diff)
The file was removedllvm/test/MC/AArch64/coff-gnu.s
The file was modifiedllvm/test/CodeGen/AArch64/win64-no-uwtable.ll (diff)
The file was addedllvm/test/MC/AArch64/coff-separator.s
The file was modifiedllvm/test/CodeGen/AArch64/landingpad-ifcvt.ll (diff)
The file was modifiedllvm/lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.cpp (diff)
The file was modifiedllvm/test/CodeGen/AArch64/windows-extern-weak.ll (diff)
Commit 3d471d7f06ff66aaf23d2dee9283e3a38a33d499 by thakis
Revert "[Test] Add failing test for PR49087"

This reverts commit 0fc1738eb75d613b9e16143b83e7cb80512e84eb.
The test passes (unexpectedly, due to the XFAIL: *) when x86 isn't
the default triple (such as on an arm machine).
The file was removedllvm/test/CodeGen/X86/pr49087.ll
Commit ec41ed5b1b9458d5e06b77ee808823b274cc2ac4 by Amara Emerson
[AArch64][GlobalISel] Support the 'returned' parameter attribute.

On AArch64 (which seems to be the only target that supports it), this
attribute allows codegen to avoid saving/restoring the value in x0
across a call.

Gives a 0.1% geomean -Os code size improvement on CTMark.

Differential Revision: https://reviews.llvm.org/D96099
The file was modifiedllvm/include/llvm/CodeGen/TargetCallingConv.h (diff)
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp (diff)
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/CallLowering.h (diff)
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64CallLowering.h (diff)
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-switch.ll (diff)
The file was modifiedllvm/lib/CodeGen/GlobalISel/CallLowering.cpp (diff)
The file was modifiedllvm/test/CodeGen/AArch64/arm64-this-return.ll (diff)
Commit 99dfcfd14c1fef46891ba7aa7e0bf5ffad1f0de9 by martin
[CMake] [MinGW] Enable use of LLVM_USE_SANITIZER in a MinGW environment

Currently using LLVM_USE_SANITIZER with a MinGW target leads to a fatal
configuration error due to an unsupported platform. MinGW targets on
clang however implement a few sanitizers, currently ASAN and UBSAN.

This patch enables LLVM_USE_SANITIZER in a MinGW environment as well.

Differential Revision: https://reviews.llvm.org/D95750
The file was modifiedllvm/cmake/modules/HandleLLVMOptions.cmake (diff)
Commit 69f5bd2ec50c407fda52734f44eb706250a25e48 by thakis
[gn build] reformat all gn files

$ git ls-files '*.gn' '*.gni' | xargs llvm/utils/gn/gn.py format
The file was modifiedllvm/utils/gn/secondary/llvm/include/llvm/Frontend/OpenMP/BUILD.gn (diff)
The file was modifiedllvm/utils/gn/secondary/compiler-rt/lib/builtins/BUILD.gn (diff)
The file was modifiedllvm/utils/gn/secondary/llvm/lib/Target/RISCV/MCTargetDesc/BUILD.gn (diff)
The file was modifiedllvm/utils/gn/secondary/libcxx/include/BUILD.gn (diff)
The file was modifiedllvm/utils/gn/build/BUILD.gn (diff)
The file was modifiedllvm/utils/gn/secondary/llvm/lib/Transforms/Scalar/BUILD.gn (diff)
Commit 0eda4547969e0f5c12af6b4e26afd34ff8c95015 by aeubanks
[SimpleLoopUnswitch] Don't non-trivially unswitch loops that are unsafe to clone

Non-trivial unswitching can clone loops.

The legacy -loop-unswitch pass also checks for this.

Fixes PR49085.

Reviewed By: asbirlea

Differential Revision: https://reviews.llvm.org/D96288
The file was addedllvm/test/Transforms/SimpleLoopUnswitch/not-safe-to-clone.ll
The file was modifiedllvm/lib/Transforms/Scalar/SimpleLoopUnswitch.cpp (diff)
Commit 0c7e044a7f62bba3fb43bf9e5fa7f31289d7e216 by david.green
[ARM] One-off identity shuffle

A One-Off Identity mask is a shuffle that is mostly an identity mask
from as single source but contains a single element out-of-place, either
from a different vector or from another position in the same vector. As
opposed to lowering this via a ARMISD::BUILD_VECTOR we can generate an
extract/insert pair directly. Under ARM with individually accessible
lane elements this often becomes a simple lane move.

This also alters the LowerVECTOR_SHUFFLEUsingMovs code to use v4f32 (not
v4i32), a more natural type for lane moves.

Differential Revision: https://reviews.llvm.org/D95551
The file was modifiedllvm/test/CodeGen/Thumb2/mve-vld3.ll (diff)
The file was modifiedllvm/test/CodeGen/Thumb2/mve-vst3.ll (diff)
The file was modifiedllvm/test/CodeGen/Thumb2/mve-vst4.ll (diff)
The file was modifiedllvm/lib/Target/ARM/ARMISelLowering.cpp (diff)
The file was modifiedllvm/test/CodeGen/Thumb2/mve-shuffle.ll (diff)
The file was modifiedllvm/test/CodeGen/Thumb2/mve-float16regloops.ll (diff)
Commit ad60802a7187aa39b0374536be3fa176fe3d6256 by i
[Verifier] Allow DW_TAG_class_type/DW_TAG_union_type to have no filename

`clang/lib/CodeGen/CGOpenMPRuntime.cpp` synthesized union
(`distinct !DICompositeType(tag: DW_TAG_union_type, name: "kmp_cmplrdata_t", size: 64, elements: <0x62b690>)`)
does not have meaningful filename/line number.

D94735 dropped the previously arbitrary and untested filename/line from the union and caused a verifier error here.

This fixes `check-libarcher` failures.

Differential Revision: https://reviews.llvm.org/D96212
The file was modifiedllvm/lib/IR/Verifier.cpp (diff)
Commit 87dbdd2e3bb63b681f8cc3179ef5c2d5929bbf61 by i
[FileCheck] Default --allow-unused-prefixes to false

Link: https://lists.llvm.org/pipermail/llvm-dev/2020-October/146162.html "[RFC] FileCheck: (dis)allowing unused prefixes"

If a downstream project using lit needs time for transition,
add the following to `lit.local.cfg`:

```
from lit.llvm.subst import ToolSubst

fc = ToolSubst('FileCheck', unresolved='fatal')
config.substitutions.insert(0, (fc.regex, 'FileCheck --allow-unused-prefixes'))
```

Differential Revision: https://reviews.llvm.org/D95849
The file was modifiedclang/test/lit.cfg.py (diff)
The file was removedllvm/test/Reduce/lit.local.cfg
The file was modifiedllvm/test/FileCheck/lit.local.cfg (diff)
The file was modifiedllvm/test/Other/opt-bisect-legacy-pass-manager.ll (diff)
The file was modifiedllvm/test/lit.cfg.py (diff)
The file was modifiedllvm/test/FileCheck/allow-unused-prefixes.txt (diff)
The file was modifiedclang/test/Driver/crash-report-null.test (diff)
The file was modifiedllvm/test/Transforms/Attributor/lit.local.cfg (diff)
The file was modifiedclang/test/OpenMP/lit.local.cfg (diff)
The file was modifiedllvm/utils/FileCheck/FileCheck.cpp (diff)
Commit 830ead58fe07f0a8365aabf16b0a5f736e788e6c by i
[test] Fix unused check prefixes
The file was modifiedlld/test/ELF/aarch64-prel16.s (diff)
The file was modifiedlld/test/MachO/load-command-sequence.s (diff)
Commit e892109c3e55eefcd197d9ef8dc701550d5f268e by eschweitz
[flang][NFC] Add comment.
The file was modifiedflang/lib/Optimizer/Dialect/FIRAttr.cpp (diff)
Commit e84a4650eb7ecd5d2e3b266d63d2f7ed83d49f98 by aeubanks
[NVPTX][NewPM] Re-enable NVVMReflectPass

Disabled alongside NVVMIntrRangePass in https://reviews.llvm.org/D96166,
but turns out NVVMIntrRangePass was the issue.

Reviewed By: tra

Differential Revision: https://reviews.llvm.org/D96291
The file was modifiedllvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp (diff)
The file was modifiedllvm/test/CodeGen/NVPTX/nvvm-reflect-arch.ll (diff)
Commit e855cc6d04ff540b20ff48cd6bfee3fbf85328b9 by Matthew.Arsenault
AMDGPU/GlobalISel: Remove dead check prefixes
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.store.2d.d16.ll (diff)
Commit bcf723b2fd6d92e7dd0d7cf4a645a2b1cb974966 by Matthew.Arsenault
AMDGPU: Stop adding stack passed wide arguments to call conv handler

The generated calling convention code shouldn't see these types since
we split large types into 32-bit chunks before the calling convention
code is triggered.

GlobalISel ends up directly calls the generated CC code before
checking for the register count breakdown. Arguably this difference is
a bug, but this was dead code for the DAG anyway.
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUCallingConv.td (diff)
Commit 87e280110d91edda0353eddb621cb96f72c7ece3 by Matthew.Arsenault
GlobalISel: Use correct calling convention in handleAssignments

This was using the calling convention of the calling function, not the
callee. Avoids regressions in a future patch.
The file was modifiedllvm/lib/CodeGen/GlobalISel/CallLowering.cpp (diff)
Commit a5b07a221a5772c0d3733a0bc8ff0b57dd5705de by kai.wang
[RISCV] Initial support of LoopVectorizer for RISC-V Vector.

Define an option -riscv-vector-bits-max to specify the maximum vector
bits for vectorizer. Loop vectorizer will use the value to check if it
is safe to use the whole vector registers to vectorize the loop.

It is not the optimum solution for loop vectorizing for scalable vector.
It assumed the whole vector registers will be used to vectorize the code.
If it is possible, we should configure vl to do vectorize instead of
using whole vector registers.

We only consider LMUL = 1 in this patch.

This patch just an initial work for loop vectorizer for RISC-V Vector.

Differential Revision: https://reviews.llvm.org/D95659
The file was modifiedllvm/lib/Target/RISCV/RISCVSubtarget.h (diff)
The file was addedllvm/test/Transforms/LoopVectorize/RISCV/scalable-vf-hint.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVSubtarget.cpp (diff)
The file was addedllvm/test/Transforms/LoopVectorize/RISCV/lit.local.cfg
The file was modifiedllvm/lib/Target/RISCV/RISCVTargetTransformInfo.h (diff)
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.cpp (diff)
The file was modifiedllvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp (diff)
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.h (diff)
Commit 549a1e2e59508d4aeaf9a93912b479798954bd5e by vtjnash
Renovate CMake files in the `llvm-exegesis` tool.

This attempts to move all tools over to using `add_llvm_library` for
better consistency. After doing this, I noticed it ended up as nearly a
reimplementation of https://reviews.llvm.org/rL342148, which later got
reverted in r342336 (b09a8c9bd9b819741b38071a7ccd95042ef2643a).

With ccache and ninja on a large core machine (40), I haven't run into
build errors, so I'm hopeful it's better now, though it doesn't seem to
be any different / new.

Reviewed By: stephenneuendorffer

Differential Revision: https://reviews.llvm.org/D90970
The file was modifiedllvm/tools/llvm-exegesis/lib/AArch64/CMakeLists.txt (diff)
The file was modifiedllvm/tools/llvm-exegesis/lib/CMakeLists.txt (diff)
The file was modifiedllvm/tools/llvm-exegesis/lib/Mips/CMakeLists.txt (diff)
The file was modifiedllvm/tools/llvm-exegesis/lib/PowerPC/CMakeLists.txt (diff)
The file was modifiedllvm/tools/llvm-exegesis/CMakeLists.txt (diff)
The file was modifiedllvm/utils/TableGen/GlobalISel/CMakeLists.txt (diff)
The file was modifiedllvm/tools/llvm-exegesis/lib/X86/CMakeLists.txt (diff)
Commit 16e7973c5d8fb543ea9e91735be8610a8b1c262a by vtjnash
Renovate CMake file for the `llvm-cfi-verify` tool

Hopefully this is the non-problematic part from https://reviews.llvm.org/rL342148, which later got reverted in r342336 (b09a8c9bd9b819741b38071a7ccd95042ef2643a) due to problems with the llvm-exegesis part of the change. That part would also still be desirable, but currently appears not to be possible (https://reviews.llvm.org/D81922).

I think this should replace https://reviews.llvm.org/D44650, per Keno's comment there.

Reviewed By: hctim

Differential Revision: https://reviews.llvm.org/D90969
The file was modifiedllvm/tools/llvm-cfi-verify/lib/CMakeLists.txt (diff)
Commit 2cd0a113df2c12405e7a81f970f2df5a0de46df2 by eschweitz
[flang][fir] Add OpaqueAttr.

Add the opaque attribute class used in flang.

https://github.com/flang-compiler/f18-llvm-project/pull/402

Differential Revision: https://reviews.llvm.org/D96293
The file was modifiedflang/lib/Optimizer/Dialect/FIRDialect.cpp (diff)
The file was modifiedflang/test/Fir/fir-ops.fir (diff)
The file was modifiedflang/include/flang/Optimizer/Dialect/FIRAttr.h (diff)
The file was modifiedflang/lib/Optimizer/Dialect/FIRAttr.cpp (diff)
Commit 1dab94f9ede5d506d6ff9c61448a8e20d43e05a7 by Yaxun.Liu
[CUDA][HIP] Pass -fgpu-rdc to host clang -cc1

Currently -fgpu-rdc is not passed to host clang -cc1.
This causes issue because -fgpu-rdc affects shadow
variable linkage in host compilation.

Reviewed by: Artem Belevich

Differential Revision: https://reviews.llvm.org/D96105
The file was modifiedclang/test/Driver/hip-toolchain-rdc.hip (diff)
The file was modifiedclang/lib/Driver/ToolChains/Cuda.cpp (diff)
The file was modifiedclang/test/Driver/hip-toolchain-rdc-separate.hip (diff)
The file was modifiedclang/test/Driver/hip-rdc-device-only.hip (diff)
The file was modifiedclang/lib/Driver/ToolChains/Clang.cpp (diff)
The file was modifiedclang/lib/Driver/ToolChains/HIP.cpp (diff)
The file was modifiedclang/test/Driver/hip-toolchain-rdc-static-lib.hip (diff)
Commit a8cb39bab04c317c9886ec3a332f3b70ce27ae4f by kyrtzidis
Make sure a module file with errors produced via '-fallow-pcm-with-compiler-errors' can be loaded when using implicit modules

A module with errors would be marked as out-of-date, then the `compilerModule` action would produce it, but due to the error it would be treated as failure and the resulting PCM would not get used.

rdar://74087062

Differential Revision: https://reviews.llvm.org/D96246
The file was modifiedclang/lib/Serialization/ASTReader.cpp (diff)
The file was modifiedclang/include/clang/Serialization/ASTReader.h (diff)
The file was modifiedclang/lib/Frontend/CompilerInstance.cpp (diff)
The file was modifiedclang/test/Modules/load-module-with-errors.m (diff)
Commit 10c1d290d92fe435634051a4ad47f76c0f948796 by vtjnash
Revert "Renovate CMake files in the `llvm-exegesis` tool."

This reverts commit 549a1e2e59508d4aeaf9a93912b479798954bd5e.

I see some buildbot failures, so reverting while I look into them.
The file was modifiedllvm/tools/llvm-exegesis/lib/PowerPC/CMakeLists.txt (diff)
The file was modifiedllvm/tools/llvm-exegesis/CMakeLists.txt (diff)
The file was modifiedllvm/tools/llvm-exegesis/lib/CMakeLists.txt (diff)
The file was modifiedllvm/tools/llvm-exegesis/lib/AArch64/CMakeLists.txt (diff)
The file was modifiedllvm/utils/TableGen/GlobalISel/CMakeLists.txt (diff)
The file was modifiedllvm/tools/llvm-exegesis/lib/Mips/CMakeLists.txt (diff)
The file was modifiedllvm/tools/llvm-exegesis/lib/X86/CMakeLists.txt (diff)
Commit 45e33e8ba9e081afffd261e78be788a9709651d9 by brad
[SPARC] Recognize and handle the %lm(sym) operator

Reviewed By: joerg

Differential Revision: https://reviews.llvm.org/D77737
The file was modifiedllvm/test/MC/Sparc/sparc-relocations.s (diff)
The file was modifiedllvm/lib/Target/Sparc/MCTargetDesc/SparcMCExpr.h (diff)
The file was modifiedllvm/lib/Target/Sparc/MCTargetDesc/SparcELFObjectWriter.cpp (diff)
The file was modifiedllvm/lib/Target/Sparc/MCTargetDesc/SparcFixupKinds.h (diff)
The file was modifiedllvm/lib/Target/Sparc/SparcAsmPrinter.cpp (diff)
The file was modifiedllvm/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp (diff)
The file was modifiedllvm/lib/Target/Sparc/MCTargetDesc/SparcMCExpr.cpp (diff)
Commit 52f312c69e1049e1f3034baf7cb9d88875f45c9a by Yaxun.Liu
Fix failure in cuda-external-tools.cu

-fgpu-rdc is output in different order
The file was modifiedclang/test/Driver/cuda-external-tools.cu (diff)
Commit 333d2cfc707d3939f44b24f87e799a5b2fc7ca5a by uday
[MLIR][NFC] Fix std.copysign op documentation

Fix std.copysign op documentation. NFC.

Differential Revision: https://reviews.llvm.org/D96217
The file was modifiedmlir/include/mlir/Dialect/StandardOps/IR/Ops.td (diff)
Commit 622611f7e5b2c42ad3c34aec4a77a82adf6d9e36 by craig.topper
[TableGen] Use return value from EmitVBRValue instead of calling GetVBRSize on the same value. Consistently use unsigned for child sizes. NFCI

getSize and setSize both use unsigned. So size_t doesn't
increase range here and might get truncated if passed to
setSize.

Also not sure why EmitVBRValue was returning uint64_t, but used
an unsigned to supply the value.
The file was modifiedllvm/utils/TableGen/DAGISelMatcherEmitter.cpp (diff)
Commit 01a48535c31169461d4eedddb48c00b79277f388 by sbc
[MC][WebAssembly] Fix provisional values for data alias relocations

When calculating the symbol offsets to write as provisitonal values
in object files we are only interested in the offset of the symbol
itself.  For aliases this offset already includes the offset of the
base symbol.

The testin question was added back in https://reviews.llvm.org/D87407
but I believe the expectations here were incorrect.   sym_a lives
at offset 4 and sym_b lives 4 bytes into that (should be 8).

The addresses of the 3 symbosl in this object file are:

foo  : 0
sym_a: 4
sym_b: 8

Differential Revision: https://reviews.llvm.org/D96234
The file was modifiedllvm/test/MC/WebAssembly/alias-offset.s (diff)
The file was modifiedllvm/lib/MC/WasmObjectWriter.cpp (diff)