SuccessChanges

Summary

  1. [DAG] foldLogicOfSetCCs - Generalize and/or (setcc X, CMax, ne), (setcc X, CMin, ne/eq) fold. NFCI. (details)
  2. [RISCV] Add support loads, stores, and splats of vXi1 fixed vectors. (details)
  3. [flang] Remove `LINK_WITH_FIR` cmake switch (details)
  4. [LV] Add tests showing suboptimal vectorization for narrow types. (details)
  5. [sanitizer] Fix suffix-log-path_test.c on arm-linux-gnu (details)
  6. Support multi-configuration generators correctly in several config files (details)
  7. [gn build] port ed98676fa483 (details)
  8. [ELF] Resolve defined symbols before undefined symbols (details)
  9. [TargetLowering][RISCV][AArch64][PowerPC] Enable BuildUDIV/BuildSDIV on illegal types before type legalization if we can find a larger legal type that supports MUL. (details)
  10. [AMDGPU] Better selection of base offset when merging DS reads/writes (details)
  11. [ARM] Single source vmovnt tests. NFC (details)
  12. [asan][test] Fix Linux/odr-violation.cpp on gcc (details)
  13. [libc++][format] Improve Add basic_format_parse_context. (details)
  14. [flang] Fix typo in FlangConfig.cmake.in. (details)
  15. [libc++][format] Enable format_error on older compilers. (details)
  16. Revert "[AssumptionCache] Avoid dangling llvm.assume calls in the cache" (details)
  17. BPF: Add LLVMAnalysis in CMakefile LINK_COMPONENTS (details)
  18. [InstCombine] add tests for disguised mul ops; NFC (details)
  19. [tests] Precommit tests for D96440 (details)
  20. [clang][Arm] Fix handling of -Wa,-implicit-it= (details)
  21. [lld][WebAssembly] Delay the merging of data section when dynamic linking (details)
  22. [flang] Improve "Error reading module file" error message (details)
  23. AMDGPU: Restrict soft clause bundling at half of the available regs (details)
  24. [dfsan] Add origin chain utils (details)
  25. [flang][fir] Update the kind mapping class. (details)
  26. [CodeGen] Basic block sections should take precendence over splitting. (details)
  27. llvm-dwarfdump: fix the counting when printing DW_OP_entry_value (details)
  28. [CodeGen] Split out cold exception handling pads. (details)
  29. [flang] Don't perform macro replacement unless *.F, *.F90, &c. (details)
  30. Revert "[lldb/test] Automatically find debug servers to test" (details)
  31. [clangd] Retire the cross-file-rename command-line flag. (details)
  32. [flang][fir][NFC] Rename WhereOp to IfOp. (details)
  33. Move implementation of isAssumeLikeIntrinsic into IntrinsicInst (details)
  34. [AMDGPU] Fix promote alloca with double use in a same insn (details)
  35. Encode alignment attribute for `atomicrmw` (details)
  36. Encode alignment attribute for `cmpxchg` (details)
  37. Fix incorrect indentation in LangRef.rst (details)
  38. [CSSPGO] Process functions in a top-down order on a dynamic call graph. (details)
  39. Fix incorrect indentation in LangRef.rst (details)
  40. [OpenMP] Enable omp_get_num_devices() on Windows (details)
  41. [lldb] Disable x86-multithread-write.test with reproducers (details)
  42. NFCI. With the move to the new pass manager by default, sanitize-coverage.c is now passing on ARM. (details)
  43. Undo test changs introduced by D96193. (details)
  44. [OpenMP] libomp: minor changes to improve library performance (details)
  45. Fix errors in distributions (details)
  46. [AArch64] Adding Neon Sm3 & Sm4 Intrinsics (details)
  47. Replace deprecated %T in 2 tests. (details)
  48. [dfsan] Introduce memory mapping for origin tracking (details)
  49. NFC: update clang tests to check ordering and alignment for atomicrmw/cmpxchg. (details)
  50. [RISCV] Initial support for insert/extract subvector (details)
  51. s[mlir] Tighten computation of inferred SubView result type. (details)
  52. [WebAssembly] Use the new crt1-command.o if present. (details)
  53. Remove test code that cause MSAN failure. (details)
  54. [lldb] Add step target to ThreadPlanStepInRange constructor (details)
  55. ObjectFileELF: Test whether reloc_header is non-null instead of asserting. (details)
  56. [flang][fir][NFC] Move BoxType to TableGen type definition (details)
  57. [Sanitizer] Fix sanitizer tests without reducing optimization levels (details)
  58. [NFC] Extract function which registers sanitizer passes (details)
  59. [RISCV] Add a pattern for a scalable vector mask vnot. (details)
  60. [Msan, NewPM] Reduce size of msan binaries (details)
  61. [NFC,memprof] Update test after D96319 (details)
  62. [tests] Autogen a few tests for ease of update (details)
  63. [tests] precommit a tests for D96534 (and other range quality items) (details)
  64. [tests] Autogen update test to remove whitespace diffs (details)
  65. [lld][WebAssembly] Fix for weak undefined functions in -pie mode (details)
  66. [knownbits] Preserve known bits for small shift recurrences (details)
  67. [mlir] detect integer overflow in debug mode (details)
Commit 5beebf9c58be2e4e3db1dacec1d76ee909a138b8 by llvm-dev
[DAG] foldLogicOfSetCCs - Generalize and/or (setcc X, CMax, ne), (setcc X, CMin, ne/eq) fold. NFCI.

Prep work to add support for non-uniform vectors - replace APInt values with using the SDValue ops directly.
The file was modifiedllvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (diff)
Commit 033b1bd185d2ecc27bafbff6e6d95ee80f1701ac by craig.topper
[RISCV] Add support loads, stores, and splats of vXi1 fixed vectors.

This refines how we determine which masks types are legal and adds
support for loads, stores, and all ones/zeros splats.

I left a fixme in store handling where I think we need to zero
extra bits if the type isn't a multiple of a byte. If I remember
right from X86 there was some case we could have a store of a
1, 2, or 4 bit mask and have a scalar zextload that then expected the
bits to be 0. Its tricky to zero the bits with RVV. We need to do
something like round VL up, zero a register, lower the VL back down,
then do a tail undisturbed move into the zero register. Another
option might be to generate a mask of 1/2/4 bits set with a VL of 8
and use that to mask off the bits.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D96468
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td (diff)
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td (diff)
The file was modifiedllvm/lib/Target/RISCV/RISCVSubtarget.cpp (diff)
The file was addedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-splat.ll
The file was addedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-load-store.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.cpp (diff)
Commit 6a7deff58e3f725801f8566ef414af4074bc7a9d by SourabhSingh.Tomar
[flang] Remove `LINK_WITH_FIR` cmake switch

Most components required for this are already there.

Build and Testing clean.
ninja check-flang

Reviewed By: clementval, tskeith

Differential Revision: https://reviews.llvm.org/D96411
The file was modifiedflang/lib/CMakeLists.txt (diff)
The file was modifiedflang/test/CMakeLists.txt (diff)
The file was modifiedflang/tools/CMakeLists.txt (diff)
The file was modifiedflang/include/flang/CMakeLists.txt (diff)
The file was modifiedflang/CMakeLists.txt (diff)
Commit d5387ec2679b5449b81449c5ab3cb0e2fd754010 by flo
[LV] Add tests showing suboptimal vectorization for narrow types.

This patch adds additional test cases showing missing/sub-optimal
vectorization for loops which contain small and wider memory ops on
AArch64.
The file was addedllvm/test/Transforms/LoopVectorize/AArch64/extend-vectorization-factor-for-unprofitable-memops.ll
Commit 88d1724d9b5615fd2e7acf808aac69eeadf7eae7 by adhemerval.zanella
[sanitizer] Fix suffix-log-path_test.c on arm-linux-gnu

The recent suffix-log-path_test.c checks for a full stacktrace and
since on some arm-linux-gnu configuration the slow unwinder is used
on default (when the compiler emits thumb code as default), it
requires -funwind-tables on tests.

It also seems to fix the issues disable by d025df3c1de.

Reviewed By: ostannard

Differential Revision: https://reviews.llvm.org/D96337
The file was modifiedcompiler-rt/test/lsan/TestCases/do_leak_check_override.cpp (diff)
The file was modifiedcompiler-rt/test/lsan/TestCases/disabler.c (diff)
The file was modifiedcompiler-rt/test/lsan/TestCases/ignore_object.c (diff)
The file was modifiedcompiler-rt/test/lsan/TestCases/Linux/use_tls_pthread_specific_dynamic.cpp (diff)
The file was modifiedcompiler-rt/test/lsan/TestCases/Linux/cleanup_in_tsd_destructor.c (diff)
The file was modifiedcompiler-rt/test/lsan/TestCases/use_after_return.cpp (diff)
The file was modifiedcompiler-rt/test/sanitizer_common/CMakeLists.txt (diff)
Commit ed98676fa4833bb80632fc7c9db10c3328d78485 by stilis
Support multi-configuration generators correctly in several config files

Multi-configuration generators (such as Visual Studio and Xcode) allow the specification of a build flavor at build time instead of config time, so the lit configuration files need to support that - and they do for the most part. There are several places that had one of two issues (or both!):

1) Paths had %(build_mode)s set up, but then not configured, resulting in values that would not work correctly e.g. D:/llvm-build/%(build_mode)s/bin/dsymutil.exe
2) Paths did not have %(build_mode)s set up, but instead contained $(Configuration) (which is the value for Visual Studio at configuration time, for Xcode they would have had the equivalent) e.g. "D:/llvm-build/$(Configuration)/lib".

This seems to indicate that we still have a lot of fragility in the configurations, but also that a number of these paths are never used (at least on Windows) since the errors appear to have been there a while.

This patch fixes the configurations and it has been tested with Ninja and Visual Studio to generate the correct paths. We should consider removing some of these settings altogether.

Reviewed By: JDevlieghere, mehdi_amini

Differential Revision: https://reviews.llvm.org/D96427
The file was modifiedmlir/test/Unit/lit.site.cfg.py.in (diff)
The file was modifiedlld/test/lit.site.cfg.py.in (diff)
The file was modifiedlld/test/CMakeLists.txt (diff)
The file was modifiedclang/test/Unit/lit.site.cfg.py.in (diff)
The file was modifiedllvm/test/CMakeLists.txt (diff)
The file was modifiedllvm/test/lit.site.cfg.py.in (diff)
The file was modifiedllvm/cmake/modules/AddLLVM.cmake (diff)
The file was modifiedmlir/examples/standalone/test/lit.site.cfg.py.in (diff)
The file was modifiedllvm/test/Unit/lit.site.cfg.py.in (diff)
The file was modifiedmlir/integration_test/lit.site.cfg.py.in (diff)
The file was modifiedmlir/test/lit.site.cfg.py.in (diff)
The file was modifiedlld/test/Unit/lit.site.cfg.py.in (diff)
The file was modifiedlldb/test/API/lit.site.cfg.py.in (diff)
Commit 18d38b240392ed2cbb15ba0b1f09f484033b67b7 by thakis
[gn build] port ed98676fa483
The file was modifiedllvm/utils/gn/secondary/llvm/test/BUILD.gn (diff)
The file was modifiedllvm/utils/gn/secondary/lld/test/BUILD.gn (diff)
Commit 0557b1bdec6e5e7228292f390a49829efcacd4da by i
[ELF] Resolve defined symbols before undefined symbols

When parsing an object file, LLD interleaves undefined symbol resolution (which
may recursively fetch other lazy objects) with defined symbol resolution.

This may lead to surprising results, e.g. if an object file defines currently
undefined symbols and references another lazy symbol, we may interleave defined
symbols with the lazy fetch, potentially leading to the defined symbols
resolving to different files.

As an example, if both `a.a(a.o)` and `a.a(b.o)` define `foo` (not in COMDAT
group, or in different COMDAT groups) and `__profd_foo` (in COMDAT group
`__profd_foo`).  LLD may resolve `foo` to `a.a(a.o)` and `__profd_foo` to
`b.a(b.o)`, i.e. different files.

```
parse ArchiveFile a.a
  entry fetches a.a(a.o)
  parse ObjectFile a.o
    define entry
    define foo
    reference b
    b fetches a.a(b.o)
    parse ObjectFile b.o
      define prevailing __profd_foo
    define (ignored) non-prevailing __profd_foo
```

Assuming a set of interconnected symbols are defined all or none in several lazy
objects. Arguably making them resolve to the same file is preferable than making
them resolve to different files (some are lazy objects).

The main argument favoring the new behavior is the stability. The relative order
between a defined symbol and an undefined symbol does not change the symbol
resolution behavior.  Only the relative order between two undefined symbols can
affect fetching behaviors.

---

The real world case is reduced from a Fuchsia PGO usage: `a.a(a.o)` has a
constructor within COMDAT group C5 while `a.a(b.o)` has a constructor within
COMDAT group C2. Because they use different group signatures, they are not
de-duplicated. It is not entirely whether Clang behavior is entirely conforming.

LLD selects the PGO counter section (`__profd_*`) from `a.a(b.o)` and the
constructor section from `a.a(a.o)`. The `__profd_*` is a SHF_LINK_ORDER section
linking to its own non-prevailing constructor section, so LLD errors
`sh_link points to discarded section`. This patch fixes the error.

Differential Revision: https://reviews.llvm.org/D95985
The file was modifiedlld/ELF/InputFiles.cpp (diff)
The file was addedlld/test/ELF/interconnected-lazy.s
Commit 5744502a137cbc9f2732e707fde984399b241515 by craig.topper
[TargetLowering][RISCV][AArch64][PowerPC] Enable BuildUDIV/BuildSDIV on illegal types before type legalization if we can find a larger legal type that supports MUL.

If we wait until the type is legalized, we'll lose information
about the orginal type and need to use larger magic constants.
This gets especially bad on RISCV64 where i64 is the only legal
type.

I've limited this to simple scalar types so it only works for
i8/i16/i32 which are most likely to occur. For more odd types
we might want to do a small promotion to a type where MULH is legal
instead.

Unfortunately, this does prevent some urem/srem+seteq matching since
that still require legal types.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D96210
The file was modifiedllvm/test/CodeGen/AArch64/urem-seteq-nonzero.ll (diff)
The file was modifiedllvm/test/CodeGen/RISCV/srem-lkk.ll (diff)
The file was modifiedllvm/test/CodeGen/RISCV/div.ll (diff)
The file was modifiedllvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp (diff)
The file was modifiedllvm/test/CodeGen/AArch64/srem-seteq.ll (diff)
The file was modifiedllvm/test/CodeGen/PowerPC/loop-instr-form-prepare.ll (diff)
The file was modifiedllvm/test/CodeGen/AArch64/urem-seteq.ll (diff)
The file was modifiedllvm/test/CodeGen/RISCV/urem-lkk.ll (diff)
The file was modifiedllvm/lib/Target/BPF/BPFISelLowering.h (diff)
Commit 23db2d363fd3fe851197fc314f0150976e31be5e by jay.foad
[AMDGPU] Better selection of base offset when merging DS reads/writes

When merging a pair of DS reads or writes needs to materialize the base
offset in a vgpr, choose a value that is aligned to as high a power of
two as possible. This maximises the chance that different pairs can use
the same base offset, in which case the base offset registers can be
commoned up by MachineCSE.

Differential Revision: https://reviews.llvm.org/D96421
The file was modifiedllvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/merge-load-store-vreg.mir (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/ds-combine-large-stride.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/fence-lds-read2-write2.ll (diff)
Commit 0f60ed1205351eaedda773c2671ae7d32b9c74ce by david.green
[ARM] Single source vmovnt tests. NFC
The file was modifiedllvm/test/CodeGen/Thumb2/mve-vmovn.ll (diff)
Commit 0dc6122dd31c742894bd16871b227ec9b1f9bf36 by i
[asan][test] Fix Linux/odr-violation.cpp on gcc
The file was modifiedcompiler-rt/test/asan/TestCases/Linux/odr-violation.cpp (diff)
Commit af83e89ae303a2bc54d94164b5ea05fa47a8f9e1 by koraq
[libc++][format] Improve Add basic_format_parse_context.

Add an additional guard to prevent building on older clang versions.

This should fix the build of https://buildkite.com/mlir/mlir-core
The file was modifiedlibcxx/include/format (diff)
Commit 204360fd71d605d04cbe6e6efa3c2a898912c326 by thomasp
[flang] Fix typo in FlangConfig.cmake.in.

`find_package(Flang)` does not work as there is a missing `@` in the
FlangConfig.cmake.in file. This patch fixes the issue.

Reviewed By: thopre

Differential Revision: https://reviews.llvm.org/D96484
The file was modifiedflang/cmake/modules/FlangConfig.cmake.in (diff)
Commit f8772da8cc9a0be65c9ba028c2b5a895c1ed4f91 by koraq
[libc++][format] Enable format_error on older compilers.

It seems like modifying the header doesn't cause libc++ to be rebuild.
So the breakage of the previous commit didn't happen on my system.

This should fix the build of https://buildkite.com/mlir/mlir-core
The file was modifiedlibcxx/include/format (diff)
Commit 606aa622b23855784c5db5b48b1c4800467fd851 by llvm-project
Revert "[AssumptionCache] Avoid dangling llvm.assume calls in the cache"

This reverts commit b7d870eae7fdadcf10d0f177faa7409c2e37d776 and the
subsequent fix "[Polly] Fix build after AssumptionCache change (D96168)"
(commit e6810cab09fcbc87b6e5e4d226de0810e2f2ea38).

It caused indeterminism in the output, such that e.g. the
polly-x86_64-linux buildbot failed accasionally.
The file was modifiedllvm/test/Analysis/AssumptionCache/basic.ll (diff)
The file was modifiedpolly/lib/Analysis/ScopBuilder.cpp (diff)
The file was modifiedllvm/lib/Analysis/AssumptionCache.cpp (diff)
The file was modifiedllvm/lib/Transforms/Utils/CodeExtractor.cpp (diff)
The file was modifiedllvm/lib/Analysis/CodeMetrics.cpp (diff)
The file was modifiedllvm/include/llvm/Analysis/AssumptionCache.h (diff)
The file was modifiedllvm/lib/Transforms/Utils/PredicateInfo.cpp (diff)
The file was modifiedllvm/lib/Analysis/ScalarEvolution.cpp (diff)
The file was modifiedllvm/lib/Transforms/Scalar/AlignmentFromAssumptions.cpp (diff)
Commit 74975d35b47631da0c7911561f16d3ffd1af142a by yhs
BPF: Add LLVMAnalysis in CMakefile LINK_COMPONENTS

buildbot reported a build error like below:
  BPFTargetMachine.cpp:(.text._ZN4llvm19TargetTransformInfo5ModelINS_10BPFTTIImplEED2Ev
    [_ZN4llvm19TargetTransformInfo5ModelINS_10BPFTTIImplEED2Ev]+0x14):
    undefined reference to `llvm::TargetTransformInfo::Concept::~Concept()'
  lib/Target/BPF/CMakeFiles/LLVMBPFCodeGen.dir/BPFTargetMachine.cpp.o:
    In function `llvm::TargetTransformInfo::Model<llvm::BPFTTIImpl>::~Model()':

Commit a260ae716030 ("BPF: Implement TTI.IntImmCost() properly")
added TargetTransformInfo to BPF, which requires LLVMAnalysis
dependence. In certain cmake configurations, lacking explicit
LLVMAnalysis dependency may cause compilation error.
Similar to other targets, this patch added LLVMAnalysis
in CMakefile LINK_COMPONENTS explicitly.
The file was modifiedllvm/lib/Target/BPF/CMakeLists.txt (diff)
Commit 6ef84730157e6beb56c5fbd4b7541dd2f2be72f9 by spatel
[InstCombine] add tests for disguised mul ops; NFC
The file was modifiedllvm/test/Transforms/InstCombine/or-shifted-masks.ll (diff)
Commit 81c51891ade1bf12c2e3fea054c9016a61f81012 by listmail
[tests] Precommit tests for D96440
The file was addedllvm/test/Analysis/ValueTracking/shift-recurrence-knownbits.ll
Commit a680bc3a31d36d321ccf3801bdcff74d58842bfa by ndesaulniers
[clang][Arm] Fix handling of -Wa,-implicit-it=

Similiar to D95872, this flag can be set for the assembler directly.
Move validation code into a reusable helper function.

Link: https://bugs.llvm.org/show_bug.cgi?id=49023
Link: https://github.com/ClangBuiltLinux/linux/issues/1270
Reported-by: Arnd Bergmann <arnd@kernel.org>
Signed-off-by: Nick Desaulniers <ndesaulniers@google.com>

Reviewed By: DavidSpickett

Differential Revision: https://reviews.llvm.org/D96285
The file was modifiedclang/lib/Driver/ToolChains/Clang.cpp (diff)
The file was addedclang/test/Driver/arm-target-as-mimplicit-it.s
Commit 70f3c6e9e6b8a0e5efc7cbf8997df32156ea9536 by sbc
[lld][WebAssembly] Delay the merging of data section when dynamic linking

With dynamic linking we have the current limitation that there can be
only a single active data segment (since we use __memory_base as the
load address and we can't do arithmetic in constant expresions).

This change delays the merging of active segments until a little later
in the linking process which means that the grouping of data by section,
and the magic __start/__end symbols work as expected under dynamic
linking.

Differential Revision: https://reviews.llvm.org/D96453
The file was modifiedlld/test/wasm/data-segments.ll (diff)
The file was modifiedlld/wasm/Symbols.cpp (diff)
The file was modifiedlld/wasm/OutputSegment.h (diff)
The file was modifiedlld/wasm/InputChunks.cpp (diff)
The file was modifiedlld/wasm/Writer.cpp (diff)
The file was modifiedlld/test/wasm/tls-no-shared.s (diff)
The file was modifiedlld/wasm/InputChunks.h (diff)
The file was modifiedlld/wasm/MapFile.cpp (diff)
Commit 0bfa4ac6c6fceffcffb3ae44027859cf6f5e06c0 by pklausler
[flang] Improve "Error reading module file" error message

Instead of using a message attachment with further details,
emit the details as part of a single message.

Differential Revision: https://reviews.llvm.org/D96465
The file was modifiedflang/lib/Semantics/mod-file.cpp (diff)
The file was modifiedflang/test/Semantics/resolve12.f90 (diff)
The file was modifiedflang/test/Semantics/resolve26.f90 (diff)
The file was modifiedflang/test/Flang-Driver/include-module.f90 (diff)
Commit e3c6fa36119ea428b17cef468e4aceee786433bf by Matthew.Arsenault
AMDGPU: Restrict soft clause bundling at half of the available regs

Fixes a testcase that was overcommitting large register tuples to a
bundle, which the register allocator could not possibly satisfy.  This
was producing a bundle which used nearly all of the available SGPRs
with a series of 16-dword loads (not all of which are freely available
to use).

This is a quick hack for some deeper issues with how the clause
bundler tracks register pressure.

Overall the pressure tracking used here doesn't make sense and is too
imprecise for what it needs to avoid the allocator failing. The
pressure estimate does not account for the alignment requirements of
large SGPR tuples, so this was really underestimating the pressure
impact. This also ignores the impact of the extended live range of the
use registers after the bundle is introduced. Additionally, it didn't
account for some wide tuples not being available due to reserved
registers.

This regresses a few cases. These end up introducing more
spilling. This is also a function of the global pressure being used in
the decision to bundle, not the local pressure impact of the bundle
itself.
The file was addedllvm/test/CodeGen/AMDGPU/limit-soft-clause-reg-pressure.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask.ll (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll (diff)
The file was modifiedllvm/lib/Target/AMDGPU/SIFormMemoryClauses.cpp (diff)
The file was modifiedllvm/test/CodeGen/AMDGPU/spill-vgpr-to-agpr.ll (diff)
The file was addedllvm/test/CodeGen/AMDGPU/soft-clause-exceeds-register-budget.ll
Commit 2d9c6e10e92e983fb3ad497f29bea697a94c935a by jianzhouzh
[dfsan] Add origin chain utils

This is a part of https://reviews.llvm.org/D95835.

The design is based on MSan origin chains.

An 4-byte origin is a hash of an origin chain. An origin chain is a
pair of a stack hash id and a hash to its previous origin chain. 0 means
no previous origin chains exist. We limit the length of a chain to be
16. With origin_history_size = 0, the limit is removed.

The change does not have any test cases yet. The following change
will be adding test cases when the APIs are used.

Reviewed-by: morehouse

Differential Revision: https://reviews.llvm.org/D96160
The file was modifiedcompiler-rt/lib/dfsan/dfsan.h (diff)
The file was modifiedcompiler-rt/lib/dfsan/dfsan_flags.inc (diff)
The file was addedcompiler-rt/lib/dfsan/dfsan_origin.h
The file was modifiedcompiler-rt/lib/dfsan/dfsan.cpp (diff)
The file was addedcompiler-rt/lib/dfsan/dfsan_chained_origin_depot.h
The file was modifiedcompiler-rt/lib/dfsan/CMakeLists.txt (diff)
The file was addedcompiler-rt/lib/dfsan/dfsan_chained_origin_depot.cpp
The file was addedcompiler-rt/lib/dfsan/dfsan_flags.h
Commit 4dc87d1010351170d73ebd23869751fe1bd6ac26 by eschweitz
[flang][fir] Update the kind mapping class.

The kind mapper provides a portable mechanism to map Fortran type KIND values
independent of the front-end to their corresponding MLIR and LLVM types.

Differential Revision: https://reviews.llvm.org/D96362
The file was modifiedflang/include/flang/Optimizer/Support/KindMapping.h (diff)
The file was addedflang/unittests/Optimizer/KindMappingTest.cpp
The file was modifiedflang/unittests/Optimizer/CMakeLists.txt (diff)
The file was modifiedflang/lib/Optimizer/Support/KindMapping.cpp (diff)
Commit d079dbc591899159925a1fe10b081fa0f6bb61bd by snehasishk
[CodeGen] Basic block sections should take precendence over splitting.

The use of basic block sections should take precedence over the machine
function splitting pass. Since they use the same underlying mechanism
they are kept exclusive. Updated the tests to check that split machine
functions is overridden by all flavours of basic block sections.

Differential Revision: https://reviews.llvm.org/D96392
The file was modifiedllvm/test/CodeGen/X86/basic-block-sections-labels.ll (diff)
The file was modifiedllvm/test/CodeGen/X86/basic-block-sections.ll (diff)
The file was modifiedllvm/lib/CodeGen/TargetPassConfig.cpp (diff)
The file was modifiedllvm/test/CodeGen/X86/basic-block-sections-list.ll (diff)
Commit 97dbab879700fa51abe5f090ea31bfbed3483701 by Adrian Prantl
llvm-dwarfdump: fix the counting when printing DW_OP_entry_value

The block size is in bytes, and not number of operands.

Differential Revision: https://reviews.llvm.org/D96472
The file was modifiedllvm/lib/DebugInfo/DWARF/DWARFExpression.cpp (diff)
The file was modifiedllvm/test/tools/llvm-dwarfdump/X86/debug_loc_OP_entry_value.s (diff)
Commit 2c7077e67dc77834607c877ad6e8caa6e33ae238 by snehasishk
[CodeGen] Split out cold exception handling pads.

Support for splitting exception handling pads was added in D73739. This
change updates the code to split out exception handling pads if profile
information indicates that they are cold. For a given function with
multiple landind pads, if one of them is hot they are all retained as
part of the hot code section.

Differential Revision: https://reviews.llvm.org/D96372
The file was modifiedllvm/test/CodeGen/X86/machine-function-splitter.ll (diff)
The file was modifiedllvm/lib/CodeGen/MachineFunctionSplitter.cpp (diff)
Commit 8880a63a15a011b3265a184c398f2ff81570cdb6 by pklausler
[flang] Don't perform macro replacement unless *.F, *.F90, &c.

Avoid spurious and confusing macro replacements from things like
-DPIC on Fortran source files whose suffixes indicate that preprocessing
is not expected.

Add gfortran-like "-cpp" and "-nocpp" flags to f18 to force predefinition
of macros independent of the source file suffix.

Differential Revision: https://reviews.llvm.org/D96464
The file was modifiedflang/lib/Parser/preprocessor.h (diff)
The file was modifiedflang/tools/f18/f18.cpp (diff)
The file was modifiedflang/lib/Parser/preprocessor.cpp (diff)
The file was modifiedflang/lib/Parser/parsing.cpp (diff)
Commit 3cad308ce5d9eb2cc52f43ccef68f3d2b12f2a32 by pavel
Revert "[lldb/test] Automatically find debug servers to test"

The commit 7df4eaaa937332c0617aa665080533966e2c98a0 appears to
break the windows bot. Revert while I investigate.
The file was modifiedlldb/utils/lldb-dotest/lldb-dotest.in (diff)
The file was modifiedlldb/test/API/lit.site.cfg.py.in (diff)
The file was modifiedlldb/test/API/commands/platform/sdk/TestPlatformSDK.py (diff)
The file was modifiedlldb/packages/Python/lldbsuite/test/dotest.py (diff)
The file was modifiedlldb/test/API/CMakeLists.txt (diff)
The file was modifiedlldb/packages/Python/lldbsuite/test/dotest_args.py (diff)
The file was modifiedlldb/packages/Python/lldbsuite/test/tools/lldb-server/lldbgdbserverutils.py (diff)
The file was modifiedlldb/utils/lldb-dotest/CMakeLists.txt (diff)
Commit 573348ab9b281221e0e78376c233d1898ed0bf68 by hokein.wu
[clangd] Retire the cross-file-rename command-line flag.

This patch only focuses on the flag. Removing actual single-file mode
(and the flag in RenameOption) will come in a follow-up.

Differential Revision: https://reviews.llvm.org/D96495
The file was modifiedclang-tools-extra/clangd/tool/ClangdMain.cpp (diff)
The file was modifiedclang-tools-extra/clangd/refactor/Rename.h (diff)
The file was modifiedclang-tools-extra/clangd/unittests/RenameTests.cpp (diff)
Commit f47d7c145b89985807c1e84316d091c5711f2e49 by eschweitz
[flang][fir][NFC] Rename WhereOp to IfOp.
The file was modifiedflang/lib/Optimizer/Dialect/FIROps.cpp (diff)
The file was modifiedflang/include/flang/Optimizer/Dialect/FIROps.td (diff)
The file was modifiedflang/lib/Lower/IO.cpp (diff)
Commit 8151c1b44211d5a7154ca860d28a6aed3a4f2715 by Stanislav.Mekhanoshin
Move implementation of isAssumeLikeIntrinsic into IntrinsicInst

This is remove dependency on ValueTracking in the future patch.

Differential Revision: https://reviews.llvm.org/D96079
The file was modifiedllvm/lib/Analysis/ValueTracking.cpp (diff)
The file was modifiedllvm/include/llvm/IR/IntrinsicInst.h (diff)
Commit cb41ee92dab809b3389de286a51127723a35834d by Stanislav.Mekhanoshin
[AMDGPU] Fix promote alloca with double use in a same insn

If we have an instruction where more than one pointer operands
are derived from the same promoted alloca, we are fixing it for
one argument and do not fix a second use considering this user
done.

Fix this by deferring processing of memory intrinsics until all
potential operands are replaced.

Fixes: SWDEV-271358

Differential Revision: https://reviews.llvm.org/D96386
The file was modifiedllvm/test/CodeGen/AMDGPU/promote-alloca-mem-intrinsics.ll (diff)
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp (diff)
Commit d06ab79816785fa362e7d96d7a398bea8064cba7 by jyknight
Encode alignment attribute for `atomicrmw`

This is a follow up patch to D83136 adding the align attribute to `atomicwmw`.

Differential Revision: https://reviews.llvm.org/D83465
The file was modifiedllvm/test/Transforms/GCOVProfiling/atomic-counter.ll (diff)
The file was modifiedllvm/docs/LangRef.rst (diff)
The file was modifiedllvm/lib/Bitcode/Writer/BitcodeWriter.cpp (diff)
The file was modifiedllvm/lib/IR/AsmWriter.cpp (diff)
The file was modifiedllvm/test/Bitcode/compatibility.ll (diff)
The file was modifiedllvm/lib/Bitcode/Reader/BitcodeReader.cpp (diff)
The file was modifiedllvm/lib/AsmParser/LLParser.cpp (diff)
Commit 17517f3178b5cdda832c4e90f618437c13560013 by jyknight
Encode alignment attribute for `cmpxchg`

This is a follow up patch to D83136 adding the align attribute to `cmpxchg`.
See also D83465 for `atomicrmw`.

Differential Revision: https://reviews.llvm.org/D87443
The file was modifiedllvm/docs/LangRef.rst (diff)
The file was modifiedllvm/lib/Bitcode/Reader/BitcodeReader.cpp (diff)
The file was modifiedllvm/lib/AsmParser/LLParser.cpp (diff)
The file was modifiedllvm/lib/Bitcode/Writer/BitcodeWriter.cpp (diff)
The file was modifiedllvm/lib/IR/AsmWriter.cpp (diff)
The file was modifiedllvm/test/Bitcode/compatibility.ll (diff)
Commit ca052adf07f0e5f453555053e0b0172e0b9f7309 by gchatelet
Fix incorrect indentation in LangRef.rst
The file was modifiedllvm/docs/LangRef.rst (diff)
Commit de40f6d6230e2ec1383c52e555876235f9fd0077 by hoy
[CSSPGO] Process functions in a top-down order on a dynamic call graph.

Functions are currently processed by the sample profiler loader in a top-down order defined by the static call graph. The order is being adjusted to be a top-down order based on the input context-sensitive profile. One benefit is that the processing order of caller and callee in one SCC would follow the context order in the profile to favor more inlining. Another benefit is that the processing order of caller and callee through an indirect call (which is not on the static call graph) can be honored which in turn allows for more inlining.

The profile top-down order for SCC is also extended to support non-CS profiles.

Two switches `-mllvm -use-profile-indirect-call-edges` and `-mllvm -use-profile-top-down-order` are being introduced.

Reviewed By: wmi

Differential Revision: https://reviews.llvm.org/D95988
The file was modifiedllvm/include/llvm/Transforms/IPO/SampleContextTracker.h (diff)
The file was addedllvm/test/Transforms/SampleProfile/Inputs/profile-topdown-order.prof
The file was addedllvm/test/Transforms/SampleProfile/profile-topdown-order.ll
The file was modifiedllvm/lib/Transforms/IPO/SampleProfile.cpp (diff)
The file was addedllvm/test/Transforms/SampleProfile/Inputs/profile-context-order.prof
The file was modifiedllvm/lib/Transforms/IPO/SampleContextTracker.cpp (diff)
The file was addedllvm/test/Transforms/SampleProfile/profile-context-order.ll
Commit 8f3518e69bee735cabf234ce5a5e8dce13730ced by gchatelet
Fix incorrect indentation in LangRef.rst
The file was modifiedllvm/docs/LangRef.rst (diff)
Commit ffb21e7f0593fde83568ae364040296fe94cf347 by hansang.bae
[OpenMP] Enable omp_get_num_devices() on Windows

This patch enables omp_get_num_devices() and omp_get_initial_device() on
Windows by providing an alternative to dlsym on Windows, and proposes to
add a new libomptarget entry, __tgt_get_num_devices().

Differential Revision: https://reviews.llvm.org/D96182
The file was modifiedopenmp/runtime/src/kmp_os.h (diff)
The file was modifiedopenmp/runtime/src/kmp_ftn_entry.h (diff)
The file was modifiedopenmp/runtime/src/z_Windows_NT_util.cpp (diff)
The file was modifiedopenmp/runtime/cmake/LibompHandleFlags.cmake (diff)
Commit 876e7714dc73e651c5841af1b38b54fa350b6331 by Jonas Devlieghere
[lldb] Disable x86-multithread-write.test with reproducers

This test is failing on GreenDragon. Disabling it until I have bandwidth
to investigate why the register values are different during replay.
The file was modifiedlldb/test/Shell/Register/x86-multithread-write.test (diff)
Commit 7b4832648a6339c798f1f72bbc88b1ee41e9a338 by douglas.yung
NFCI. With the move to the new pass manager by default, sanitize-coverage.c is now passing on ARM.

This change removes the XFAIL from the original test and duplicates the test into sanitize-coverage-old-pm.c
which uses the old pass manager and has the corresponding XFAIL.

This should fix the XPASS from this and similar runs:
http://lab.llvm.org:8011/#/builders/60/builds/1875
The file was modifiedclang/test/CodeGen/sanitize-coverage.c (diff)
The file was addedclang/test/CodeGen/sanitize-coverage-old-pm.c
Commit 0f848a24e19e9bcba8ac52e74ff364e047a81678 by hoy
Undo test changs introduced by D96193.

Summary:
The test doesn't work on Windows but there seems no good way to disable the test for Windows only so I'm undoing the test changes.
The file was modifiedlld/test/ELF/reproduce-lto.s (diff)
Commit 838dcdb5fc428fd4b1830a1a23bb38c1fb1c8e5a by Andrey.Churbanov
[OpenMP] libomp: minor changes to improve library performance

Three minor changes in this patch:
- added UNLIKELY hint to few rarely executed branches;
- replaced couple of run time checks with debug assertions;
- moved check of presence of ittnotify tool from inside the function call.

Differential Revision: https://reviews.llvm.org/D95816
The file was modifiedopenmp/runtime/src/kmp_itt.h (diff)
The file was modifiedopenmp/runtime/src/kmp_tasking.cpp (diff)
Commit 74916008a87dd2992d12af0b9725cb1804d0c8ba by gchatelet
Fix errors in distributions
The file was modifiedlibc/benchmarks/MemorySizeDistributions.cpp (diff)
Commit 61cca0f2e5bbb6045bb27b822e34cd39c9c1acb1 by pzheng
[AArch64] Adding Neon Sm3 & Sm4 Intrinsics

This adds SM3 and SM4 Intrinsics support for AArch64, specifically:
        vsm3ss1q_u32
        vsm3tt1aq_u32
        vsm3tt1bq_u32
        vsm3tt2aq_u32
        vsm3tt2bq_u32
        vsm3partw1q_u32
        vsm3partw2q_u32
        vsm4eq_u32
        vsm4ekeyq_u32

Reviewed By: labrinea

Differential Revision: https://reviews.llvm.org/D95655
The file was addedclang/test/CodeGen/aarch64-neon-sm4-sm3.c
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrFormats.td (diff)
The file was modifiedclang/lib/CodeGen/CGBuiltin.cpp (diff)
The file was addedclang/test/CodeGen/aarch64-neon-range-checks.c
The file was modifiedclang/include/clang/Basic/arm_neon.td (diff)
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrInfo.td (diff)
The file was modifiedllvm/include/llvm/IR/IntrinsicsAArch64.td (diff)
The file was addedllvm/test/CodeGen/AArch64/neon-sm4-sm3.ll
Commit 60bed4ab57d562d5770cc9c24a8fcb243208f5e5 by abidh
Replace deprecated %T in 2 tests.

In D91442, @MaskRay commented about a failure. This commit does the following to
address his comments:

1. Replace %T with %t as former is deprecated.
2. Add an explicit --sysroot argument in a test.

Some tests were failing when gcc-10-riscv64-linux-gnu is installed on test machine.
This was happening because the test was checking a case when --gcc-toolchain is not
provided. But if --sysroot was also not provided then code could pick a toolchain
installed in /usr. So to make the test more robust, I have provided an explicit --sysroot
argument. Its value has been chosen to match the existing patterns.

Reviewed By: MaskRay

Differential Revision: https://reviews.llvm.org/D93023
The file was modifiedclang/test/Driver/riscv32-toolchain-extra.c (diff)
The file was modifiedclang/test/Driver/riscv64-toolchain-extra.c (diff)
Commit 5ebbc5802ff3248622506b90e93a93d0eb3bfcee by jianzhouzh
[dfsan] Introduce memory mapping for origin tracking

Reviewed-by: morehouse

Differential Revision: https://reviews.llvm.org/D96545
The file was modifiedcompiler-rt/include/sanitizer/dfsan_interface.h (diff)
The file was modifiedcompiler-rt/lib/dfsan/dfsan.cpp (diff)
The file was modifiedcompiler-rt/lib/dfsan/dfsan.h (diff)
The file was modifiedcompiler-rt/lib/dfsan/dfsan_platform.h (diff)
Commit 8043d5a9643b5731454fce91fac0018bfddc96d6 by jyknight
NFC: update clang tests to check ordering and alignment for atomicrmw/cmpxchg.

The ability to specify alignment was recently added, and it's an
important property which we should ensure is set as expected by
Clang. (Especially before making further changes to Clang's code in
this area.) But, because it's on the end of the lines, the existing
tests all ignore it.

Therefore, update all the tests to also verify the expected alignment
for atomicrmw and cmpxchg. While I was in there, I also updated uses
of 'load atomic' and 'store atomic', and added the memory ordering,
where that was missing.
The file was modifiedclang/test/CodeGenObjC/property-atomic-bool.m (diff)
The file was modifiedclang/test/OpenMP/atomic_codegen.cpp (diff)
The file was modifiedclang/test/CodeGen/2010-01-13-MemBarrier.c (diff)
The file was modifiedclang/test/CodeGen/atomic_ops.c (diff)
The file was modifiedclang/test/CodeGenCXX/cxx1z-inline-variables.cpp (diff)
The file was modifiedclang/test/CodeGenCXX/atomicinit.cpp (diff)
The file was modifiedclang/test/OpenMP/atomic_update_codegen.cpp (diff)
The file was modifiedclang/test/CodeGen/code-coverage-tsan.c (diff)
The file was modifiedclang/test/CodeGenCXX/atomic-inline.cpp (diff)
The file was modifiedclang/test/OpenMP/atomic_write_codegen.c (diff)
The file was modifiedclang/test/CodeGenCXX/static-init-pnacl.cpp (diff)
The file was modifiedclang/test/OpenMP/atomic_read_codegen.c (diff)
The file was modifiedclang/test/CodeGen/atomics-inlining.c (diff)
The file was modifiedclang/test/CodeGen/arm-atomics.c (diff)
The file was modifiedclang/test/OpenMP/teams_distribute_simd_reduction_codegen.cpp (diff)
The file was modifiedclang/test/CodeGenCXX/static-initializer-branch-weights.cpp (diff)
The file was modifiedclang/test/CodeGen/2008-03-05-syncPtr.c (diff)
The file was modifiedclang/test/CodeGen/pr45476.cpp (diff)
The file was modifiedclang/test/OpenMP/parallel_for_lastprivate_conditional.cpp (diff)
The file was modifiedclang/test/CodeGen/arm-atomics-m.c (diff)
The file was modifiedclang/test/OpenMP/for_reduction_codegen.cpp (diff)
The file was modifiedclang/test/OpenMP/target_teams_distribute_parallel_for_simd_reduction_codegen.cpp (diff)
The file was modifiedclang/test/CodeGen/arm64-microsoft-intrinsics.c (diff)
The file was modifiedclang/test/CodeGen/Atomics.c (diff)
The file was modifiedclang/test/CodeGen/big-atomic-ops.c (diff)
The file was modifiedclang/test/CodeGenCXX/atomic-align.cpp (diff)
The file was modifiedclang/test/CodeGen/linux-arm-atomic.c (diff)
The file was modifiedclang/test/OpenMP/teams_distribute_reduction_codegen.cpp (diff)
The file was modifiedclang/test/CodeGen/builtins-nvptx.c (diff)
The file was modifiedclang/test/CodeGen/atomic-ops.c (diff)
The file was modifiedclang/test/CodeGen/bittest-intrin.c (diff)
The file was modifiedclang/test/OpenMP/atomic_capture_codegen.cpp (diff)
The file was modifiedclang/test/OpenMP/sections_reduction_codegen.cpp (diff)
The file was modifiedclang/test/OpenMP/requires_relaxed_codegen.cpp (diff)
The file was modifiedclang/test/OpenMP/teams_distribute_parallel_for_reduction_codegen.cpp (diff)
The file was modifiedclang/test/OpenMP/target_teams_distribute_parallel_for_reduction_codegen.cpp (diff)
The file was modifiedclang/test/CodeGen/c11atomics-ios.c (diff)
The file was modifiedclang/test/CodeGen/c11atomics.c (diff)
The file was modifiedclang/test/OpenMP/parallel_reduction_codegen.cpp (diff)
The file was modifiedclang/test/OpenMP/requires_seq_cst_codegen.cpp (diff)
The file was modifiedclang/test/CodeGen/ms-intrinsics-other.c (diff)
The file was modifiedclang/test/OpenMP/target_teams_distribute_reduction_codegen.cpp (diff)
The file was modifiedclang/test/CodeGen/X86/x86-atomic-long_double.c (diff)
The file was modifiedclang/test/CodeGen/ms-volatile.c (diff)
The file was modifiedclang/test/CodeGenCXX/static-init.cpp (diff)
The file was modifiedclang/test/OpenMP/parallel_master_codegen.cpp (diff)
The file was modifiedclang/test/CodeGenCXX/atomic.cpp (diff)
The file was modifiedclang/test/CodeGenCXX/cxx1z-decomposition.cpp (diff)
The file was modifiedclang/test/CodeGen/X86/x86_64-atomic-128.c (diff)
The file was modifiedclang/test/CodeGen/ms-intrinsics.c (diff)
The file was modifiedclang/test/CodeGen/RISCV/riscv-atomics.c (diff)
The file was modifiedclang/test/CodeGen/atomic.c (diff)
The file was modifiedclang/test/OpenMP/teams_distribute_parallel_for_simd_reduction_codegen.cpp (diff)
The file was modifiedclang/test/CodeGen/builtins-nvptx-ptx50.cu (diff)
The file was modifiedclang/test/CodeGenOpenCL/atomic-ops.cl (diff)
The file was modifiedclang/test/OpenMP/requires_acq_rel_codegen.cpp (diff)
The file was modifiedclang/test/OpenMP/target_teams_distribute_simd_reduction_codegen.cpp (diff)
The file was modifiedclang/test/OpenMP/taskloop_with_atomic_codegen.cpp (diff)
Commit 9e62c9146d2c125a1abda594add70ed66008e372 by craig.topper
[RISCV] Initial support for insert/extract subvector

This patch handles cast-like insert_subvector & extract_subvector
in which case:
1. index starts from 0.
2. inserting a fixed-width vector into a scalable vector,
   or extracting a fixed-width vector from a scalable vector.

Reviewed By: craig.topper, frasercrmck

Differential Revision: https://reviews.llvm.org/D96352
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll (diff)
The file was modifiedllvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp (diff)
Commit 5bc4f8846c07bc3b355c8f303416784a10d1a298 by nicolas.vasilache
s[mlir] Tighten computation of inferred SubView result type.

The AffineMap in the MemRef inferred by SubViewOp may have uncompressed symbols which result in type mismatch on otherwise unused symbols. Make the computation of the AffineMap compress those unused symbols which results in better canonical types.
Additionally, improve the error message to report which inferred type was expected.

Differential Revision: https://reviews.llvm.org/D96551
The file was modifiedmlir/include/mlir/IR/AffineExpr.h (diff)
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/Fusion.cpp (diff)
The file was modifiedmlir/lib/Conversion/StandardToLLVM/StandardToLLVM.cpp (diff)
The file was modifiedmlir/lib/Dialect/StandardOps/IR/Ops.cpp (diff)
The file was modifiedmlir/test/IR/invalid-ops.mlir (diff)
The file was modifiedmlir/include/mlir/IR/BuiltinTypes.h (diff)
The file was modifiedmlir/lib/IR/AffineExpr.cpp (diff)
The file was modifiedmlir/test/IR/core-ops.mlir (diff)
The file was modifiedmlir/include/mlir/IR/AffineMap.h (diff)
The file was modifiedmlir/include/mlir/Dialect/StandardOps/IR/Ops.h (diff)
The file was modifiedmlir/lib/IR/AffineMap.cpp (diff)
The file was modifiedmlir/lib/IR/BuiltinTypes.cpp (diff)
Commit f9c05fc391458e455e8e4d4108a7f270f2f7bedc by Dev
[WebAssembly] Use the new crt1-command.o if present.

If crt1-command.o exists in the sysroot, the libc has new-style command
support, so use it.

Differential Revision: https://reviews.llvm.org/D89274
The file was modifiedclang/lib/Driver/ToolChains/WebAssembly.cpp (diff)
Commit 0eed2b1a3cde819430fd37fd0cf1b0f876e67bb9 by hoy
Remove test code that cause MSAN failure.

Summary:
The negative test (with the feature being added disabled) caused MSAN failure and that's the added feature is supposed to fix. Therefore the negative test code is being removed.
The file was modifiedllvm/test/Transforms/SampleProfile/profile-context-order.ll (diff)
Commit a5ab1dc4ad2c02510e363b4dd3c267f9eaf11516 by davelee.com
[lldb] Add step target to ThreadPlanStepInRange constructor

`QueueThreadPlanForStepInRange` accepts a `step_into_target`, but the constructor for
`ThreadPlanStepInRange` does not. Instead, a caller would optionally call
`SetStepInTarget()` in a separate statement.

This change adds `step_into_target` as a constructor argument. This simplifies
construction of `ThreadPlanSP`, by avoiding a subsequent downcast and conditional
assignment. This constructor is already used in downstream repos.

Differential Revision: https://reviews.llvm.org/D96539
The file was modifiedlldb/include/lldb/Target/ThreadPlanStepInRange.h (diff)
The file was modifiedlldb/source/Target/Thread.cpp (diff)
The file was modifiedlldb/source/Plugins/LanguageRuntime/CPlusPlus/CPPLanguageRuntime.cpp (diff)
The file was modifiedlldb/source/Target/ThreadPlanStepInRange.cpp (diff)
Commit c314f5ede8249ef20fff1de45c2c31156b1950d4 by peter
ObjectFileELF: Test whether reloc_header is non-null instead of asserting.

It is possible for the GetSectionHeaderByIndex lookup to fail because
the previous FindSectionContainingFileAddress lookup found a segment
instead of a section. This is possible if the binary does not have
a PLT (which means that lld will in some circumstances set DT_JMPREL
to 0, which is typically an address that is part of the ELF headers
and not in a section) and may also be possible if the section headers
have been stripped. To handle this possibility, replace the assert
with an if.

Differential Revision: https://reviews.llvm.org/D93438
The file was addedlldb/test/Shell/ObjectFile/ELF/null-jmprel.yaml
The file was modifiedlldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp (diff)
Commit a48bee2294b608f5c530f783757692eb2ca44100 by clementval
[flang][fir][NFC] Move BoxType to TableGen type definition

This patch is a follow up of D96422 and move BoxType to TableGen.

Reviewed By: mehdi_amini

Differential Revision: https://reviews.llvm.org/D96476
The file was modifiedflang/lib/Optimizer/Dialect/FIRType.cpp (diff)
The file was modifiedflang/include/flang/Optimizer/Dialect/FIROps.td (diff)
The file was modifiedflang/include/flang/Optimizer/Dialect/FIRTypes.td (diff)
The file was modifiedflang/include/flang/Optimizer/Dialect/FIRType.h (diff)
The file was modifiedflang/include/flang/Optimizer/Dialect/FIROps.h (diff)
Commit 9360f1a1911edee4c6f4c7d070bdaa1ca26016cc by julian.lettner
[Sanitizer] Fix sanitizer tests without reducing optimization levels

As discussed, these tests are compiled with optimization to mimic real
sanitizer usage [1].

Let's mark relevant functions with `noinline` so we can continue to
check against the stack traces in the report.

[1] https://reviews.llvm.org/D96198

This reverts commit 04af72c5423eb5ff7c0deba2d08cb46d583bb9d4.

Differential Revision: https://reviews.llvm.org/D96357
The file was modifiedcompiler-rt/test/tsan/blacklist2.cpp (diff)
The file was modifiedcompiler-rt/test/tsan/free_race.c (diff)
The file was modifiedcompiler-rt/test/tsan/race_on_heap.cpp (diff)
The file was modifiedcompiler-rt/test/ubsan/TestCases/Misc/missing_return.cpp (diff)
The file was modifiedcompiler-rt/test/tsan/longjmp4.cpp (diff)
The file was modifiedcompiler-rt/test/tsan/longjmp3.cpp (diff)
The file was modifiedcompiler-rt/test/tsan/race_top_suppression.cpp (diff)
The file was modifiedcompiler-rt/test/tsan/sleep_sync.cpp (diff)
The file was modifiedcompiler-rt/test/tsan/simple_stack.c (diff)
Commit f2f59d2a060788f17040ad924ee2d11da0e215c8 by Vitaly Buka
[NFC] Extract function which registers sanitizer passes

Reviewed By: aeubanks

Differential Revision: https://reviews.llvm.org/D96481
The file was modifiedclang/lib/CodeGen/BackendUtil.cpp (diff)
Commit 7a7836b4d8463584eb8ee34a16096cc5ef62a8ee by craig.topper
[RISCV] Add a pattern for a scalable vector mask vnot.

We can use a vnand.mm with the same register for both inputs.
This avoids materializing an alls ones constant with vmset.mm.
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td (diff)
The file was modifiedllvm/test/CodeGen/RISCV/rvv/setcc-fp-rv64.ll (diff)
The file was modifiedllvm/test/CodeGen/RISCV/rvv/setcc-fp-rv32.ll (diff)
Commit 686b65f85f22c70e082753cd05e8572d22e3991c by Vitaly Buka
[Msan, NewPM] Reduce size of msan binaries

EarlyCSEPass called after msan redices code size by about 10%.
Similar optimization exists for legacy pass manager in
addGeneralOptsForMemorySanitizer.

Reviewed By: eugenis

Differential Revision: https://reviews.llvm.org/D96406
The file was modifiedclang/lib/CodeGen/BackendUtil.cpp (diff)
The file was modifiedclang/test/Driver/msan.c (diff)
Commit f2133f2e318d8ce87e9972d288485d9bc49fef5c by Vitaly Buka
[NFC,memprof] Update test after D96319
The file was modifiedcompiler-rt/test/memprof/TestCases/test_malloc_load_store.c (diff)
Commit 6538cef317297887a6541c325e3433cdcc91944d by listmail
[tests] Autogen a few tests for ease of update
The file was modifiedllvm/test/Analysis/ScalarEvolution/increasing-or-decreasing-iv.ll (diff)
The file was modifiedllvm/test/Analysis/ScalarEvolution/sext-to-zext.ll (diff)
The file was modifiedllvm/test/Analysis/ScalarEvolution/max-be-count-not-constant.ll (diff)
Commit b911a71427c56e8edde7a8e044f325c6f4de8dd0 by listmail
[tests] precommit a tests for D96534 (and other range quality items)
The file was addedllvm/test/Analysis/ScalarEvolution/ranges.ll
Commit 72fc5b1b8eeca2baffd9568eb296626f0af37966 by listmail
[tests] Autogen update test to remove whitespace diffs
The file was modifiedllvm/test/Analysis/ScalarEvolution/extract-highbits-sameconstmask.ll (diff)
Commit ac2be2b6a366c05c01b8228fd804ba6ed52d320b by sbc
[lld][WebAssembly] Fix for weak undefined functions in -pie mode

This fixes two somewhat related issues.  Firstly we were never
generating imports for weak functions (even with the `import-functions`
policy for undefined symbols).  Adding a direct call to foo in the
`weak-undefined-pic.s` exposed a crash in the linker which this
change fixes.

Secondly we were failing to call `handleWeakUndefines` for the `-pie`
case which is PIC but doesn't set the undefined symbol policy to
`import-functions`.  With this change `-pie` binaries will by default
call `handleWeakUndefines` which generates the undefined stub handlers
for any weakly undefined symbols.

Fixes: https://github.com/emscripten-core/emscripten/issues/13337

Differential Revision: https://reviews.llvm.org/D95914
The file was modifiedlld/test/wasm/weak-undefined-pic.s (diff)
The file was modifiedlld/wasm/Driver.cpp (diff)
The file was modifiedlld/wasm/Writer.cpp (diff)
Commit 8ef4b961a3af6e6839b487ba3962ddad133629fc by listmail
[knownbits] Preserve known bits for small shift recurrences

The motivation for this is that I'm looking at an example that uses shifts as induction variables. There's lots of other omissions, but one of the first I noticed is that we can't compute tight known bits. (This indirectly causes SCEV's range analysis to produce very poor results as well.)

Differential Revision: https://reviews.llvm.org/D96440
The file was modifiedllvm/lib/Analysis/ValueTracking.cpp (diff)
The file was modifiedllvm/test/Analysis/ValueTracking/shift-recurrence-knownbits.ll (diff)
Commit 5f022ad6ed8dc23094bb50f83608d5c786a821a9 by ajcbik
[mlir] detect integer overflow in debug mode

Rationale:
This computation failed ASAN for the following input
(integer overflow during 4032000000000000000 * 100):

  tensor<100x200x300x400x500x600x700x800xf32>

This change adds a simple overflow detection during
debug mode (which we run more regularly than ASAN).
Arguably this is an unrealistic tensor input, but
in the context of sparse tensors, we may start to
see cases like this.

Bug:
https://bugs.llvm.org/show_bug.cgi?id=49136

Reviewed By: mehdi_amini

Differential Revision: https://reviews.llvm.org/D96530
The file was modifiedmlir/lib/IR/BuiltinTypes.cpp (diff)