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Started 3 mo 16 days ago
Took 7 hr 24 min

Build #3973 (Jun 11, 2021 4:01:22 AM)

Changes
  1. Move code for checking loop metadata into Analysis [nfc] (details / githubweb)
  2. Move variable only used inside an assert into the assert. (details / githubweb)
  3. [SCEV] Use mustprogress flag on loops (in addition to function attribute) (details / githubweb)
  4. [ELF][RISCV] Resolve branch relocations referencing undefined weak to current location if not using PLT (details / githubweb)
  5. [ELF] Simplify getAArch64UndefinedRelativeWeakVA. NFC (details / githubweb)
  6. [libc++] Remove unnecessary header in enable_view.h (which caused a cycle) (details / githubweb)
  7. [LI] Add a cover function for checking if a loop is mustprogress [nfc] (details / githubweb)
  8. [ARM] Fix Changed status in MVEGatherScatterLoweringPass. (details / githubweb)
  9. [clang] NRVO: Improvements and handling of more cases. (details / githubweb)
  10. [SimplifyCFG] avoid 'tmp' variables in test file; NFC (details / githubweb)
  11. [LV] Parallel annotated loop does not imply all loads can be hoisted. (details / githubweb)
  12. 2d Arm Neon sdot op, and lowering to the intrinsic. (details / githubweb)
  13. [MLIR] Document that Dialect Conversion traverses in preorder (details / githubweb)
  14. [AArch64][GlobalISel] Legalize scalar G_CTTZ + G_CTTZ_ZERO_UNDEF (details / githubweb)
  15. [libcxx][ranges] removes default_initializable from weakly_incrementable and view (details / githubweb)
  16. Preserve more MD_mem_parallel_loop_access and MD_access_group in SROA (details / githubweb)
  17. [clang] Implement P2266 Simpler implicit move (details / githubweb)
  18. [Profile] Handle invalid profile data (details / githubweb)
  19. [IR] make -warn-frame-size into a module attr (details / githubweb)
  20. [Profile] Remove redundant check (details / githubweb)
  21. LoadStoreVectorizer: support different operand orders in the add sequence match (details / githubweb)
  22. [static initializers] Emit global_ctors and global_dtors in reverse order when .ctors/.dtors are used. (details / githubweb)
  23. [IR] Value: Fix OpCode checks (details / githubweb)
  24. [RISCV] Add test cases that show failure to use some W instructions if they are proceeded by a load. NFC (details / githubweb)
  25. [SDAG] Fix pow2 assumption when splitting vectors (details / githubweb)
  26. [ValueTypes] Define MVTs for v6i32, v6f32, v7i32, v7f32 (details / githubweb)
  27. [AArch64][GlobalISel] Fix incorrectly generating uxtw/sxtw for addressing modes. (details / githubweb)
  28. [mlir][IR] Move MemRefElementTypeInterface to a new BuiltinTypeInterfaces file (details / githubweb)
  29. [mlir] Add new SubElementAttr/SubElementType Interfaces (details / githubweb)
  30. [mlir-ir-printing] Prefix the dump message with the split marker(// -----) (details / githubweb)
  31. [Flang] Compile fix after D99459. (details / githubweb)
  32. [RISCV] Use ComputeNumSignBits/MaskedValueIsZero in RISCVDAGToDAGISel::selectSExti32/selectZExti32. (details / githubweb)
  33. [VectorCombine] Fix alignment in single element store (details / githubweb)

Started by upstream project clang-stage2-Rthinlto_relay build number 5814
originally caused by:

This run spent:

  • 7 hr 18 min waiting;
  • 7 hr 24 min build duration;
  • 14 hr total from scheduled to completion.
Revision: d631fe591d8ff09edb895ef124e8370875d8d523
Repository: https://github.com/llvm/llvm-zorg.git
  • refs/remotes/origin/main
Revision: 2670c7dd5b25e87825edc0aca7729c1d3dba5afc
Repository: https://github.com/llvm/llvm-project.git
  • detached
Test Result (no failures)