|
 | libcxx/utils/ci/macos-ci-setup (diff) |
 | libcxx/utils/ci/secrets.env |
 | libcxx/docs/AddingNewCIJobs.rst (diff) |
Commit
ecb68f1c8b11b54dc8c48af9f5fe28c261090aba
by xingxue[libc++abi] NFC: avoid a -Wunused-parameter warning
Summary: A -Wunused-parameter warning was introduced by patch rG7f0244afa828 [libc++abi] NFC: adding a new parameter base to functions for calculating… (authored by xingxue). The unused parameter base will be used in a follow-on patch D101298. This patch is to avoid the warning before D101298 is landed.
Reviewers: ldionne, sfertile, compnerd, libc++abi
Reviewed by: ldionne
Differential Revision: https://reviews.llvm.org/D104235
|
 | libcxxabi/src/cxa_personality.cpp (diff) |
Commit
e0c382a9d5a0e2689b97186736ebc82e17c5f822
by Piotr Sobczak[AMDGPU] Limit runs of fixLdsBranchVmemWARHazard
The code in fixLdsBranchVmemWARHazard looks for patterns of a vmem/lds access followed by a branch, followed by an lds/vmem access.
The handling of the hazard requires an arbitrary number of instructions to process. In the worst case where a function has a vmem access, but no lds accesses, all instructions are examined only to conclude that the hazard cannot occur.
Add the pre-processing stage which detects if there is both lds and vmem present in the function and only then does the more costly search.
This patch significantly improves compilation time in the cases the hazard cannot happen. In one pathological case I looked at IsHazardInst is needlesly called 88.6 milions times.
The numbers could also be improved by introducing a map around the inner calls to ::getWaitStatesSince in fixLdsBranchVmemWARHazard, but nothing will beat not running fixLdsBranchVmemWARHazard at all in the cases detected by shouldRunLdsBranchVmemWARHazardFixup().
Differential Revision: https://reviews.llvm.org/D104219
|
 | llvm/lib/Target/AMDGPU/GCNHazardRecognizer.h (diff) |
 | llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp (diff) |
Commit
e3bc4dbe8e75faf13798028fcb7710675d8c05ed
by hanchung[mlir][Linalg] Make printer/parser have the same behavior.
The parser of generic op did not recognize the output from mlir-opt when there are multiple outputs. One would wrap the result types with braces, and one would not. The patch makes the behavior the same.
Reviewed By: mravishankar
Differential Revision: https://reviews.llvm.org/D104256
|
 | mlir/lib/Dialect/Linalg/IR/LinalgOps.cpp (diff) |
 | mlir/test/Dialect/Linalg/canonicalize.mlir (diff) |
 | mlir/test/Dialect/Linalg/invalid.mlir (diff) |
 | mlir/test/Dialect/Linalg/roundtrip.mlir (diff) |
 | mlir/test/Dialect/Linalg/vectorization.mlir (diff) |
 | mlir/test/Dialect/Linalg/bufferize.mlir (diff) |
|
 | clang/www/c_status.html (diff) |
Commit
585e65d3307f5f081b32b21421f2a0b84eccd1b5
by lebedev.ri[TLI] SimplifyDemandedVectorElts(): handle SCALAR_TO_VECTOR(EXTRACT_VECTOR_ELT(?, 0))
Iff we have `SCALAR_TO_VECTOR` (and we demand it's only defined 0'th element), and said scalar was produced by `EXTRACT_VECTOR_ELT` from the 0'th element of some vector, then we can just continue traversal into said source vector.
This comes up in X86 vector uniform shift lowering.
Reviewed By: RKSimon
Differential Revision: https://reviews.llvm.org/D104250
|
 | llvm/test/CodeGen/X86/vector-rotate-256.ll (diff) |
 | llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp (diff) |
 | llvm/test/CodeGen/X86/vector-fshl-256.ll (diff) |
 | llvm/test/CodeGen/X86/vector-fshl-rot-512.ll (diff) |
 | llvm/test/CodeGen/X86/vector-fshr-256.ll (diff) |
 | llvm/test/CodeGen/X86/vector-fshr-512.ll (diff) |
 | llvm/test/CodeGen/X86/vector-fshr-rot-256.ll (diff) |
 | llvm/test/CodeGen/X86/vector-fshr-rot-512.ll (diff) |
 | llvm/test/CodeGen/X86/vector-fshl-rot-256.ll (diff) |
 | llvm/test/CodeGen/X86/vector-fshl-512.ll (diff) |
|
 | compiler-rt/include/sanitizer/dfsan_interface.h (diff) |
 | compiler-rt/lib/dfsan/dfsan.cpp (diff) |
 | compiler-rt/lib/dfsan/done_abilist.txt (diff) |
 | compiler-rt/test/dfsan/stack_trace.c |
Commit
03841edde7eee21d1d450041ab9a113a7e1be869
by Adrian PrantlAllow signposts to take advantage of deferred string substitution
One nice feature of the os_signpost API is that format string substitutions happen in the consumer, not the logging application. LLVM's current Signpost class doesn't take advantage of this though and instead always uses a static "Begin/End %s" format string.
This patch uses variadic macros to allow the API to be used as intended. Unfortunately, the primary use-case I had in mind (the LLDB_SCOPED_TIMER() macro) does not get much better from this, because __PRETTY_FUNCTION__ is *not* a macro, but a static string, so signposts created by LLDB_SCOPED_TIMER() still use a static "%s" format string. At least LLDB_SCOPED_TIMERF() works as intended.
This reapplies the previsously reverted patch with additional MachO.h macro #undefs.
Differential Revision: https://reviews.llvm.org/D103575
|
 | llvm/lib/Support/Timer.cpp (diff) |
 | llvm/include/llvm/Support/Signposts.h (diff) |
 | lldb/source/Plugins/ObjectFile/Mach-O/ObjectFileMachO.cpp (diff) |
 | lldb/source/Utility/Timer.cpp (diff) |
 | lldb/include/lldb/Utility/Timer.h (diff) |
 | llvm/lib/Support/Signposts.cpp (diff) |
|
 | llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp (diff) |
 | llvm/test/Instrumentation/HWAddressSanitizer/X86/globals.ll |
 | compiler-rt/test/hwasan/TestCases/global.c (diff) |
|
 | libc/src/math/x86_64/sqrt.cpp |
 | libc/src/math/x86_64/sqrtl.cpp |
 | libc/src/math/x86_64/CMakeLists.txt (diff) |
 | libc/src/math/x86_64/sqrtf.cpp |
|
 | clang/lib/Basic/Targets/Hexagon.cpp (diff) |
 | clang/test/CodeGen/hexagon-inline-asm-reg-names.c |
|
 | lldb/include/lldb/Utility/Timer.h (diff) |
 | lldb/source/Plugins/ObjectFile/Mach-O/ObjectFileMachO.cpp (diff) |
 | lldb/source/Utility/Timer.cpp (diff) |
 | llvm/include/llvm/Support/Signposts.h (diff) |
 | llvm/lib/Support/Timer.cpp (diff) |
 | llvm/lib/Support/Signposts.cpp (diff) |
Commit
1c096bf09ffd3d51665b60942d6bde19e7dbbd5a
by huihuiz[SVE][LSR] Teach LSR to enable simple scaled-index addressing mode generation for SVE.
Currently, Loop strengh reduce is not handling loops with scalable stride very well.
Take loop vectorized with scalable vector type <vscale x 8 x i16> for instance, (refer to test/CodeGen/AArch64/sve-lsr-scaled-index-addressing-mode.ll added).
Memory accesses are incremented by "16*vscale", while induction variable is incremented by "8*vscale". The scaling factor "2" needs to be extracted to build candidate formula i.e., "reg(%in) + 2*reg({0,+,(8 * %vscale)}". So that addrec register reg({0,+,(8*vscale)}) can be reused among Address and ICmpZero LSRUses to enable optimal solution selection.
This patch allow LSR getExactSDiv to recognize special cases like "C1*X*Y /s C2*X*Y", and pull out "C1 /s C2" as scaling factor whenever possible. Without this change, LSR is missing candidate formula with proper scaled factor to leverage target scaled-index addressing mode.
Note: This patch doesn't fully fix AArch64 isLegalAddressingMode for scalable vector. But allow simple valid scale to pass through.
Reviewed By: sdesmalen
Differential Revision: https://reviews.llvm.org/D103939
|
 | llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp (diff) |
 | llvm/test/CodeGen/AArch64/sve-fold-vscale.ll (diff) |
 | llvm/test/CodeGen/AArch64/sve-lsr-scaled-index-addressing-mode.ll |
 | llvm/lib/Target/AArch64/AArch64ISelLowering.cpp (diff) |
Commit
035217ff515b8ecdc871e39fa840f3cba1b9cec7
by Adrian PrantlAllow signposts to take advantage of deferred string substitution
One nice feature of the os_signpost API is that format string substitutions happen in the consumer, not the logging application. LLVM's current Signpost class doesn't take advantage of this though and instead always uses a static "Begin/End %s" format string.
This patch uses variadic macros to allow the API to be used as intended. Unfortunately, the primary use-case I had in mind (the LLDB_SCOPED_TIMER() macro) does not get much better from this, because __PRETTY_FUNCTION__ is *not* a macro, but a static string, so signposts created by LLDB_SCOPED_TIMER() still use a static "%s" format string. At least LLDB_SCOPED_TIMERF() works as intended.
This reapplies the previously reverted patch with additional include order fixes for non-modular builds of LLDB.
Differential Revision: https://reviews.llvm.org/D103575
|
 | lldb/include/lldb/Utility/Timer.h (diff) |
 | lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARFDebugMap.cpp (diff) |
 | lldb/source/Plugins/ObjectFile/Mach-O/ObjectFileMachO.cpp (diff) |
 | llvm/include/llvm/Support/Signposts.h (diff) |
 | llvm/lib/Support/Timer.cpp (diff) |
 | llvm/lib/Support/Signposts.cpp (diff) |
 | lldb/source/Utility/Timer.cpp (diff) |
Commit
6c848c28c2f495f97a8fce879bd0624d61272d24
by jacobhegnaRemove redundant environment variable XLA_FLAGS.
If the flag is not set, the script saved_model_aot_compile.py in tensorflow will default it to the correct value. However, in TF 2.5, the way the value is set in TensorFlowCompile.cmake file triggers a build error.
Reviewed By: mtrofin
Differential Revision: https://reviews.llvm.org/D103972
|
 | llvm/cmake/modules/TensorFlowCompile.cmake (diff) |
Commit
312011899ac3c48a77f4c5a069000f8aa93a8873
by leonardchan[compiler-rt][hwasan] Add newline between record_addr lines on frame record dumps
If SymbolizePC failes, it's possible for the newline to not be emitted.
Differential Revision: https://reviews.llvm.org/D103845
|
 | compiler-rt/lib/hwasan/hwasan_report.cpp (diff) |
Commit
853a614864754cd4b000f03a7ab8fbba103d6177
by silvasean[mlir:OpFormatGen] Add Support for `$_ctxt` in the transformer.
This is useful for "build tuple" type ops. In my case, in npcomp, I have an op:
``` // Result type is `!torch.tuple<!torch.tensor, !torch.tensor>`. torch.prim.TupleConstruct %0, %1 : !torch.tensor, !torch.tensor ```
and the context is required for the `Torch::TupleType::get` call (for the case of an empty tuple).
The handling of these FmtContext's in the code is pretty ad-hoc -- I didn't attempt to rationalize it and just made a targeted fix. As someone unfamiliar with the code I had a hard time seeing how to more broadly fix the situation.
Differential Revision: https://reviews.llvm.org/D104274
|
 | mlir/tools/mlir-tblgen/OpDefinitionsGen.cpp (diff) |
 | mlir/tools/mlir-tblgen/OpFormatGen.cpp (diff) |
 | mlir/test/mlir-tblgen/op-format.mlir (diff) |
 | mlir/test/lib/Dialect/Test/TestOps.td (diff) |
|
 | compiler-rt/lib/sanitizer_common/sanitizer_stacktrace.h (diff) |
 | llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp (diff) |
 | compiler-rt/lib/sanitizer_common/sanitizer_symbolizer_markup.cpp (diff) |
 | compiler-rt/lib/asan/asan_new_delete.cpp (diff) |
 | compiler-rt/lib/asan/asan_rtl.cpp (diff) |
 | compiler-rt/lib/asan/asan_interceptors.cpp (diff) |
 | compiler-rt/lib/interception/interception.h (diff) |
 | clang/lib/Driver/ToolChains/CommonArgs.cpp (diff) |
 | compiler-rt/lib/asan/asan_mapping.h (diff) |
 | compiler-rt/lib/asan/asan_shadow_setup.cpp (diff) |
 | compiler-rt/lib/sanitizer_common/sanitizer_platform_interceptors.h (diff) |
 | compiler-rt/lib/ubsan/ubsan_platform.h (diff) |
 | compiler-rt/lib/sanitizer_common/sanitizer_errno.h (diff) |
 | compiler-rt/lib/sanitizer_common/sanitizer_platform.h (diff) |
 | compiler-rt/lib/asan/asan_mapping_myriad.h (diff) |
 | compiler-rt/lib/asan/asan_internal.h (diff) |
 | compiler-rt/lib/asan/asan_poisoning.cpp (diff) |
 | compiler-rt/lib/asan/asan_malloc_linux.cpp (diff) |
Commit
1c450c3d7ec01d9daaf9f2651da93b01e7790ffd
by lkail[PowerPC] Export 16 byte load-store instructions
Export `lq`, `stq`, `lqarx` and `stqcx.` in preparation for implementing 16-byte lock free atomic operations on AIX. Add a new register class `g8prc` for these instructions, since these instructions require even-odd register pair.
Reviewed By: nemanjai, jsji, #powerpc
Differential Revision: https://reviews.llvm.org/D103010
|
 | llvm/lib/Target/PowerPC/PPCSchedule.td (diff) |
 | llvm/lib/Target/PowerPC/PPCInstrFormats.td (diff) |
 | llvm/lib/Target/PowerPC/PPCInstr64Bit.td (diff) |
 | llvm/lib/Target/PowerPC/PPCRegisterInfo.h (diff) |
 | llvm/lib/Target/PowerPC/PPCInstrInfo.td (diff) |
 | llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp (diff) |
 | llvm/test/MC/Disassembler/PowerPC/ppc64-encoding.txt (diff) |
 | llvm/lib/Target/PowerPC/PPCInstrInfo.h (diff) |
 | llvm/test/MC/PowerPC/ppc64-encoding-bookII.s (diff) |
 | llvm/test/CodeGen/PowerPC/ldst-16-byte.mir |
 | llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp (diff) |
 | llvm/lib/Target/PowerPC/PPCInstrInfo.cpp (diff) |
 | llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-bookII.txt (diff) |
 | llvm/test/MC/PowerPC/ppc64-encoding.s (diff) |
 | llvm/lib/Target/PowerPC/PPCRegisterInfo.td (diff) |
 | llvm/test/CodeGen/PowerPC/ldst-16-byte-asm.mir |
 | llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp (diff) |