Changes

Summary

  1. [libc++] Clean up scripts to setup CI on macOS (details)
  2. [libc++abi] NFC: avoid a -Wunused-parameter warning (details)
  3. [AMDGPU] Limit runs of fixLdsBranchVmemWARHazard (details)
  4. [mlir][Linalg] Make printer/parser have the same behavior. (details)
  5. Adding some of the documents for C11. (details)
  6. [TLI] SimplifyDemandedVectorElts(): handle SCALAR_TO_VECTOR(EXTRACT_VECTOR_ELT(?, 0)) (details)
  7. [dfsan] Add stack-trace printing functions to dfsan interface (details)
  8. Allow signposts to take advantage of deferred string substitution (details)
  9. [HWASan] Enable globals support for LAM. (details)
  10. [libc] Add hardware implementations of x86_64 sqrt functions. (details)
  11. [Hexagon] Add HVX and control register names to Hexagon target (details)
  12. Revert "Allow signposts to take advantage of deferred string substitution" (details)
  13. [SVE][LSR] Teach LSR to enable simple scaled-index addressing mode generation for SVE. (details)
  14. Allow signposts to take advantage of deferred string substitution (details)
  15. Remove redundant environment variable XLA_FLAGS. (details)
  16. [compiler-rt][hwasan] Add newline between record_addr lines on frame record dumps (details)
  17. [mlir:OpFormatGen] Add Support for `$_ctxt` in the transformer. (details)
  18. [NFC][sanitizer] clang-format some code (details)
  19. [PowerPC] Export 16 byte load-store instructions (details)
Commit d9d20802d0ce757d4b33d6bd67d700e3272bc8b6 by Louis Dionne
[libc++] Clean up scripts to setup CI on macOS
The file was removedlibcxx/utils/ci/secrets.env
The file was modifiedlibcxx/docs/AddingNewCIJobs.rst (diff)
The file was modifiedlibcxx/utils/ci/macos-ci-setup (diff)
Commit ecb68f1c8b11b54dc8c48af9f5fe28c261090aba by xingxue
[libc++abi] NFC: avoid a -Wunused-parameter warning

Summary:
A -Wunused-parameter warning was introduced by patch rG7f0244afa828 [libc++abi] NFC: adding a new parameter base to functions for calculating… (authored by xingxue). The unused parameter base will be used in a follow-on patch D101298. This patch is to avoid the warning before D101298 is landed.

Reviewers: ldionne, sfertile, compnerd, libc++abi

Reviewed by: ldionne

Differential Revision: https://reviews.llvm.org/D104235
The file was modifiedlibcxxabi/src/cxa_personality.cpp (diff)
Commit e0c382a9d5a0e2689b97186736ebc82e17c5f822 by Piotr Sobczak
[AMDGPU] Limit runs of fixLdsBranchVmemWARHazard

The code in fixLdsBranchVmemWARHazard looks for patterns of a vmem/lds
access followed by a branch, followed by an lds/vmem access.

The handling of the hazard requires an arbitrary number of instructions
to process. In the worst case where a function has a vmem access, but no lds
accesses, all instructions are examined only to conclude that the hazard
cannot occur.

Add the pre-processing stage which detects if there is both lds and vmem
present in the function and only then does the more costly search.

This patch significantly improves compilation time in the cases the hazard
cannot happen. In one pathological case I looked at IsHazardInst is needlesly
called 88.6 milions times.

The numbers could also be improved by introducing a map around the
inner calls to ::getWaitStatesSince in fixLdsBranchVmemWARHazard, but
nothing will beat not running fixLdsBranchVmemWARHazard at all in the cases
detected by shouldRunLdsBranchVmemWARHazardFixup().

Differential Revision: https://reviews.llvm.org/D104219
The file was modifiedllvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp (diff)
The file was modifiedllvm/lib/Target/AMDGPU/GCNHazardRecognizer.h (diff)
Commit e3bc4dbe8e75faf13798028fcb7710675d8c05ed by hanchung
[mlir][Linalg] Make printer/parser have the same behavior.

The parser of generic op did not recognize the output from mlir-opt when there
are multiple outputs. One would wrap the result types with braces, and one would
not. The patch makes the behavior the same.

Reviewed By: mravishankar

Differential Revision: https://reviews.llvm.org/D104256
The file was modifiedmlir/test/Dialect/Linalg/vectorization.mlir (diff)
The file was modifiedmlir/test/Dialect/Linalg/roundtrip.mlir (diff)
The file was modifiedmlir/test/Dialect/Linalg/bufferize.mlir (diff)
The file was modifiedmlir/test/Dialect/Linalg/canonicalize.mlir (diff)
The file was modifiedmlir/lib/Dialect/Linalg/IR/LinalgOps.cpp (diff)
The file was modifiedmlir/test/Dialect/Linalg/invalid.mlir (diff)
Commit 00dbf8c83218829633b9f2ec1ee94a1f3b8dd29c by aaron
Adding some of the documents for C11.

This is not the complete set of language-related documents for C11, but
is about 75% complete.
The file was modifiedclang/www/c_status.html (diff)
Commit 585e65d3307f5f081b32b21421f2a0b84eccd1b5 by lebedev.ri
[TLI] SimplifyDemandedVectorElts(): handle SCALAR_TO_VECTOR(EXTRACT_VECTOR_ELT(?, 0))

Iff we have `SCALAR_TO_VECTOR` (and we demand it's only defined 0'th element),
and said scalar was produced by `EXTRACT_VECTOR_ELT` from the 0'th element
of some vector, then we can just continue traversal into said source vector.

This comes up in X86 vector uniform shift lowering.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D104250
The file was modifiedllvm/test/CodeGen/X86/vector-fshr-rot-256.ll (diff)
The file was modifiedllvm/test/CodeGen/X86/vector-fshl-256.ll (diff)
The file was modifiedllvm/test/CodeGen/X86/vector-fshr-rot-512.ll (diff)
The file was modifiedllvm/test/CodeGen/X86/vector-fshl-rot-256.ll (diff)
The file was modifiedllvm/test/CodeGen/X86/vector-rotate-256.ll (diff)
The file was modifiedllvm/test/CodeGen/X86/vector-fshr-256.ll (diff)
The file was modifiedllvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp (diff)
The file was modifiedllvm/test/CodeGen/X86/vector-fshl-rot-512.ll (diff)
The file was modifiedllvm/test/CodeGen/X86/vector-fshl-512.ll (diff)
The file was modifiedllvm/test/CodeGen/X86/vector-fshr-512.ll (diff)
Commit 98504959a6f114866cbf523e44d2f45e755626d5 by gbalats
[dfsan] Add stack-trace printing functions to dfsan interface

Reviewed By: stephan.yichao.zhao

Differential Revision: https://reviews.llvm.org/D104165
The file was modifiedcompiler-rt/lib/dfsan/dfsan.cpp (diff)
The file was modifiedcompiler-rt/lib/dfsan/done_abilist.txt (diff)
The file was modifiedcompiler-rt/include/sanitizer/dfsan_interface.h (diff)
The file was addedcompiler-rt/test/dfsan/stack_trace.c
Commit 03841edde7eee21d1d450041ab9a113a7e1be869 by Adrian Prantl
Allow signposts to take advantage of deferred string substitution

One nice feature of the os_signpost API is that format string
substitutions happen in the consumer, not the logging
application. LLVM's current Signpost class doesn't take advantage of
this though and instead always uses a static "Begin/End %s" format
string.

This patch uses variadic macros to allow the API to be used as
intended. Unfortunately, the primary use-case I had in mind (the
LLDB_SCOPED_TIMER() macro) does not get much better from this, because
__PRETTY_FUNCTION__ is *not* a macro, but a static string, so
signposts created by LLDB_SCOPED_TIMER() still use a static "%s"
format string. At least LLDB_SCOPED_TIMERF() works as intended.

This reapplies the previsously reverted patch with additional MachO.h
macro #undefs.

Differential Revision: https://reviews.llvm.org/D103575
The file was modifiedllvm/lib/Support/Timer.cpp (diff)
The file was modifiedllvm/include/llvm/Support/Signposts.h (diff)
The file was modifiedlldb/source/Utility/Timer.cpp (diff)
The file was modifiedlldb/source/Plugins/ObjectFile/Mach-O/ObjectFileMachO.cpp (diff)
The file was modifiedlldb/include/lldb/Utility/Timer.h (diff)
The file was modifiedllvm/lib/Support/Signposts.cpp (diff)
Commit b87894a1d28f3819e38c11ce1fdf05113ac5ca34 by mascasa
[HWASan] Enable globals support for LAM.

Reviewed By: vitalybuka

Differential Revision: https://reviews.llvm.org/D104265
The file was addedllvm/test/Instrumentation/HWAddressSanitizer/X86/globals.ll
The file was modifiedllvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp (diff)
The file was modifiedcompiler-rt/test/hwasan/TestCases/global.c (diff)
Commit a58b2827feceaa27193318a12e3a06893eabdcb6 by sivachandra
[libc] Add hardware implementations of x86_64 sqrt functions.
The file was addedlibc/src/math/x86_64/sqrtl.cpp
The file was modifiedlibc/src/math/x86_64/CMakeLists.txt (diff)
The file was addedlibc/src/math/x86_64/sqrt.cpp
The file was addedlibc/src/math/x86_64/sqrtf.cpp
Commit 0577f4b1789eff410f5b28434a4f7854a50dc639 by kparzysz
[Hexagon] Add HVX and control register names to Hexagon target
The file was addedclang/test/CodeGen/hexagon-inline-asm-reg-names.c
The file was modifiedclang/lib/Basic/Targets/Hexagon.cpp (diff)
Commit 7a7c00761f6294dc21c40cbe1737354e655cda9b by Adrian Prantl
Revert "Allow signposts to take advantage of deferred string substitution"

This reverts commit 03841edde7eee21d1d450041ab9a113a7e1be869.

Unfortunately this still breaks the LLDB standalone bot.
The file was modifiedlldb/source/Utility/Timer.cpp (diff)
The file was modifiedllvm/include/llvm/Support/Signposts.h (diff)
The file was modifiedlldb/include/lldb/Utility/Timer.h (diff)
The file was modifiedlldb/source/Plugins/ObjectFile/Mach-O/ObjectFileMachO.cpp (diff)
The file was modifiedllvm/lib/Support/Timer.cpp (diff)
The file was modifiedllvm/lib/Support/Signposts.cpp (diff)
Commit 1c096bf09ffd3d51665b60942d6bde19e7dbbd5a by huihuiz
[SVE][LSR] Teach LSR to enable simple scaled-index addressing mode generation for SVE.

Currently, Loop strengh reduce is not handling loops with scalable stride very well.

Take loop vectorized with scalable vector type <vscale x 8 x i16> for instance,
(refer to test/CodeGen/AArch64/sve-lsr-scaled-index-addressing-mode.ll added).

Memory accesses are incremented by "16*vscale", while induction variable is incremented
by "8*vscale". The scaling factor "2" needs to be extracted to build candidate formula
i.e., "reg(%in) + 2*reg({0,+,(8 * %vscale)}". So that addrec register reg({0,+,(8*vscale)})
can be reused among Address and ICmpZero LSRUses to enable optimal solution selection.

This patch allow LSR getExactSDiv to recognize special cases like "C1*X*Y /s C2*X*Y",
and pull out "C1 /s C2" as scaling factor whenever possible. Without this change, LSR
is missing candidate formula with proper scaled factor to leverage target scaled-index
addressing mode.

Note: This patch doesn't fully fix AArch64 isLegalAddressingMode for scalable
vector. But allow simple valid scale to pass through.

Reviewed By: sdesmalen

Differential Revision: https://reviews.llvm.org/D103939
The file was modifiedllvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp (diff)
The file was modifiedllvm/test/CodeGen/AArch64/sve-fold-vscale.ll (diff)
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp (diff)
The file was addedllvm/test/CodeGen/AArch64/sve-lsr-scaled-index-addressing-mode.ll
Commit 035217ff515b8ecdc871e39fa840f3cba1b9cec7 by Adrian Prantl
Allow signposts to take advantage of deferred string substitution

One nice feature of the os_signpost API is that format string
substitutions happen in the consumer, not the logging
application. LLVM's current Signpost class doesn't take advantage of
this though and instead always uses a static "Begin/End %s" format
string.

This patch uses variadic macros to allow the API to be used as
intended. Unfortunately, the primary use-case I had in mind (the
LLDB_SCOPED_TIMER() macro) does not get much better from this, because
__PRETTY_FUNCTION__ is *not* a macro, but a static string, so
signposts created by LLDB_SCOPED_TIMER() still use a static "%s"
format string. At least LLDB_SCOPED_TIMERF() works as intended.

This reapplies the previously reverted patch with additional include
order fixes for non-modular builds of LLDB.

Differential Revision: https://reviews.llvm.org/D103575
The file was modifiedlldb/include/lldb/Utility/Timer.h (diff)
The file was modifiedlldb/source/Plugins/ObjectFile/Mach-O/ObjectFileMachO.cpp (diff)
The file was modifiedlldb/source/Utility/Timer.cpp (diff)
The file was modifiedllvm/include/llvm/Support/Signposts.h (diff)
The file was modifiedllvm/lib/Support/Timer.cpp (diff)
The file was modifiedllvm/lib/Support/Signposts.cpp (diff)
The file was modifiedlldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARFDebugMap.cpp (diff)
Commit 6c848c28c2f495f97a8fce879bd0624d61272d24 by jacobhegna
Remove redundant environment variable XLA_FLAGS.

If the flag is not set, the script saved_model_aot_compile.py in tensorflow will
default it to the correct value. However, in TF 2.5, the way the value is set in
TensorFlowCompile.cmake file triggers a build error.

Reviewed By: mtrofin

Differential Revision: https://reviews.llvm.org/D103972
The file was modifiedllvm/cmake/modules/TensorFlowCompile.cmake (diff)
Commit 312011899ac3c48a77f4c5a069000f8aa93a8873 by leonardchan
[compiler-rt][hwasan] Add newline between record_addr lines on frame record dumps

If SymbolizePC failes, it's possible for the newline to not be emitted.

Differential Revision: https://reviews.llvm.org/D103845
The file was modifiedcompiler-rt/lib/hwasan/hwasan_report.cpp (diff)
Commit 853a614864754cd4b000f03a7ab8fbba103d6177 by silvasean
[mlir:OpFormatGen] Add Support for `$_ctxt` in the transformer.

This is useful for "build tuple" type ops. In my case, in npcomp, I have
an op:

```
// Result type is `!torch.tuple<!torch.tensor, !torch.tensor>`.
torch.prim.TupleConstruct %0, %1 : !torch.tensor, !torch.tensor
```

and the context is required for the `Torch::TupleType::get` call (for
the case of an empty tuple).

The handling of these FmtContext's in the code is pretty ad-hoc -- I didn't
attempt to rationalize it and just made a targeted fix. As someone
unfamiliar with the code I had a hard time seeing how to more broadly fix
the situation.

Differential Revision: https://reviews.llvm.org/D104274
The file was modifiedmlir/test/lib/Dialect/Test/TestOps.td (diff)
The file was modifiedmlir/tools/mlir-tblgen/OpDefinitionsGen.cpp (diff)
The file was modifiedmlir/test/mlir-tblgen/op-format.mlir (diff)
The file was modifiedmlir/tools/mlir-tblgen/OpFormatGen.cpp (diff)
Commit b8919fb0eac15d13c5f56d3d30ce378a588dd78c by Vitaly Buka
[NFC][sanitizer] clang-format some code
The file was modifiedcompiler-rt/lib/asan/asan_interceptors.cpp (diff)
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_platform.h (diff)
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_errno.h (diff)
The file was modifiedcompiler-rt/lib/asan/asan_new_delete.cpp (diff)
The file was modifiedcompiler-rt/lib/interception/interception.h (diff)
The file was modifiedcompiler-rt/lib/asan/asan_mapping_myriad.h (diff)
The file was modifiedcompiler-rt/lib/asan/asan_shadow_setup.cpp (diff)
The file was modifiedcompiler-rt/lib/asan/asan_malloc_linux.cpp (diff)
The file was modifiedcompiler-rt/lib/asan/asan_rtl.cpp (diff)
The file was modifiedllvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp (diff)
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_stacktrace.h (diff)
The file was modifiedcompiler-rt/lib/ubsan/ubsan_platform.h (diff)
The file was modifiedcompiler-rt/lib/asan/asan_mapping.h (diff)
The file was modifiedcompiler-rt/lib/asan/asan_internal.h (diff)
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_platform_interceptors.h (diff)
The file was modifiedcompiler-rt/lib/asan/asan_poisoning.cpp (diff)
The file was modifiedclang/lib/Driver/ToolChains/CommonArgs.cpp (diff)
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_symbolizer_markup.cpp (diff)
Commit 1c450c3d7ec01d9daaf9f2651da93b01e7790ffd by lkail
[PowerPC] Export 16 byte load-store instructions

Export `lq`, `stq`, `lqarx` and `stqcx.` in preparation for implementing 16-byte lock free atomic operations on AIX.
Add a new register class `g8prc` for these instructions, since these instructions require even-odd register pair.

Reviewed By: nemanjai, jsji, #powerpc

Differential Revision: https://reviews.llvm.org/D103010
The file was modifiedllvm/test/MC/PowerPC/ppc64-encoding-bookII.s (diff)
The file was addedllvm/test/CodeGen/PowerPC/ldst-16-byte.mir
The file was modifiedllvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp (diff)
The file was modifiedllvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp (diff)
The file was modifiedllvm/lib/Target/PowerPC/PPCRegisterInfo.cpp (diff)
The file was addedllvm/test/CodeGen/PowerPC/ldst-16-byte-asm.mir
The file was modifiedllvm/lib/Target/PowerPC/PPCRegisterInfo.td (diff)
The file was modifiedllvm/test/MC/PowerPC/ppc64-encoding.s (diff)
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrInfo.cpp (diff)
The file was modifiedllvm/lib/Target/PowerPC/PPCInstr64Bit.td (diff)
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrInfo.h (diff)
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrFormats.td (diff)
The file was modifiedllvm/test/MC/Disassembler/PowerPC/ppc64-encoding-bookII.txt (diff)
The file was modifiedllvm/lib/Target/PowerPC/PPCSchedule.td (diff)
The file was modifiedllvm/test/MC/Disassembler/PowerPC/ppc64-encoding.txt (diff)
The file was modifiedllvm/lib/Target/PowerPC/PPCRegisterInfo.h (diff)
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrInfo.td (diff)