SuccessChanges

Changes from Git (git http://labmaster3.local/git/llvm-project.git)

Summary

  1. GlobalISel: Have lowerStore handle some unaligned stores (details)
  2. [DAG] isGuaranteedNotToBeUndefOrPoison - handle ISD::BUILD_VECTOR nodes (details)
  3. [ADT] Remove set_is_strict_subset (NFC) (details)
  4. AMDGPU/GlobalISel: Check some remarks for failed legalizations (details)
  5. GlobalISel: Scalarize unaligned vector stores (details)
  6. [VPlan] Add interleave group printing test. (details)
  7. [ARM] Regenerate Thumb PR35481.ll test. NFC (details)
  8. [ARM] Switch order of creating VADDV and VMLAV. (details)
  9. Fixed syntax error that occured in the patch D104974 (details)
Commit bc2cb91a20641f9685df1f3fb2ac4ea06756a252 by Matthew.Arsenault
GlobalISel: Have lowerStore handle some unaligned stores

This is NFC until some of the AMDGPU legalization rules are ripped
out.
The file was modifiedllvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
Commit 3a7c82efb8db57f0bf1cfbbd681b3905556bd049 by llvm-dev
[DAG] isGuaranteedNotToBeUndefOrPoison - handle ISD::BUILD_VECTOR nodes

If all demanded elements of the BUILD_VECTOR pass a isGuaranteedNotToBeUndefOrPoison check, then we can treat this specific demanded use of the BUILD_VECTOR as guaranteed not to be undef or poison either.

Differential Revision: https://reviews.llvm.org/D107174
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
The file was modifiedllvm/test/CodeGen/X86/freeze-constant-fold.ll
The file was modifiedllvm/test/CodeGen/X86/freeze-legalize.ll
Commit 5f5ce6e9a7eb0f735791662cd49efc2d934796fd by kazu
[ADT] Remove set_is_strict_subset (NFC)

The last use was removed on Mar 13, 2020 in commit
6b57d7f57d2cec7ec717757a6a52f2203d6e9db7.
The file was modifiedllvm/include/llvm/ADT/SetOperations.h
Commit 43c7cb9a3cf528a6e4e81acb6752b273c6e60300 by Matthew.Arsenault
AMDGPU/GlobalISel: Check some remarks for failed legalizations

The load/store tests are giant and have some cases that fail in them,
but it's hard to tell which ones are really failing. Check the remarks
to make it easier to track.
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store-global.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store.mir
Commit ebc17a0d68208a967fe8e13e1874874228dda622 by Matthew.Arsenault
GlobalISel: Scalarize unaligned vector stores

This has the same problems and limitations as the load path.
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll
The file was modifiedllvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store-global.mir
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
Commit c726b627ad0ba29af9e46901f695b2f7fcc2a661 by flo
[VPlan] Add interleave group printing test.
The file was modifiedllvm/test/Transforms/LoopVectorize/vplan-printing.ll
Commit 85d6045b88aee1d7d92eacec0099984911d7202d by david.green
[ARM] Regenerate Thumb PR35481.ll test. NFC
The file was modifiedllvm/test/CodeGen/Thumb/PR35481.ll
Commit 15a1d7e839229f3d9f5fd0a2e1255236a8f3565a by david.green
[ARM] Switch order of creating VADDV and VMLAV.

It can be beneficial to attempt to try the larger VMLAV patterns before
VADDV, in case both may match the same code.
The file was modifiedllvm/lib/Target/ARM/ARMISelLowering.cpp
The file was modifiedllvm/test/CodeGen/Thumb2/mve-vecreduce-mlapred.ll
The file was modifiedllvm/test/CodeGen/Thumb2/mve-vecreduce-mla.ll
Commit ad28ff71647503c0a93f8b23a04844484f26f52b by pyadav2299
Fixed syntax error that occured in the patch D104974
The file was modifiedllvm/docs/GlobalISel/GenericOpcode.rst