FailedChanges

Summary

  1. Revert "[sanitizer] Don't tie builders with particular workers" (details)
Commit b899cd8edcb824c4e4f999ef254209060d1ab646 by Vitaly Buka
Revert "[sanitizer] Don't tie builders with particular workers"

This reverts commit d37259ec73a4341700e981214b9032631adfdda0.
With some changes.
The file was modifiedbuildbot/osuosl/master/config/builders.py (diff)

Summary

  1. [libomptarget][devicertl] Remove branches around setting parallelLevel (details)
  2. [AMDGPU] Handle s_branch to another section. (details)
  3. [libomptarget] Update device pointer only if needed (details)
  4. [MLIR] Fix documentation of the `ExecutionEngine` in the toy tutorial example (details)
  5. [X86][SSE] X86ISD::FSETCC nodes (cmpss/cmpsd) return a 0/-1 allbits signbits result (REAPPLIED) (details)
  6. [libomp] ompd_init(): fix heap-buffer-overflow when constructing libompd.so path (details)
  7. [OpenCL] Add support of __opencl_c_read_write_images feature macro (details)
  8. [InstCombine] Pre-commit ashr(or(neg(x),x),bw-1) --> sext(icmp_ne(x,0)) tests from D105764 (details)
  9. [clang/objc] Optimize getters for non-atomic, copied properties (details)
  10. [InstCombine] Fold lshr/ashr(or(neg(x),x),bw-1) --> zext/sext(icmp_ne(x,0)) (PR50816) (details)
  11. [NFC] Add paranthesis around logical expression to silence -Wlogical-op-parentheses warning. (details)
  12. [OpenMP] Minor improvement in task allocation (details)
  13. [libc++] Generate ABI list for macOS arm64 (details)
  14. [libc++] Target x86_64 only for the backdeployment jobs (details)
  15. [libc++] Workaround non-constexpr std::exchange pre C++20 (details)
  16. Mips: Mark special case calling convention handling as custom (details)
  17. Mips/GlobalISel: Use more standard call lowering infrastructure (details)
  18. GlobalISel: Remove getIntrinsicID utility function (details)
  19. GlobalISel: Use extension instead of merge with undef in common case (details)
  20. AMDGPU: Promote signext/zeroext i16 shader returns (details)
  21. Prepare Compiler-RT for GnuInstallDirs, matching libcxx, document all (details)
  22. [mlir] Handle unused variable when assertions are disabled. (details)
  23. [OpenCL] Add verbosity when checking support of read_write images (details)
  24. [PowerPC][NFC] Power ISA features for Semachecking (details)
  25. [InstCombine] Regenerate select-gep.ll tests (details)
  26. [InstCombine] Add basic (select C, (gep Ptr, Idx), Ptr) tests from PR50183 (details)
  27. [PowerPC] Fix L[D|W]ARX Implementation (details)
  28. [mlir][memref] adjust integration tests to new lowering passes (details)
  29. [llvm] Add enum iteration to Sequence (details)
  30. [RISCV] Support machine constraint "S" (details)
  31. [mlir][Linalg] Properly specify Linalg attribute. (details)
  32. Avoid triggering assert when program calls OSAtomicCompareAndSwapLong (details)
  33. [OpaquePtr] Use AllocaInst::getAllocatedType() (details)
  34. [OpaquePtr] Use GlobalValue::getValueType() more (details)
  35. [OpaquePtr] Get load/store type without PointerType::getElementType() (details)
  36. [OpaquePtr] Use byval type more (details)
  37. Revert "[llvm] Add enum iteration to Sequence" (details)
  38. [RISCV] Prevent use of t0(aka x5) as rs1 for jalr instructions. (details)
  39. [mlir] Add support for tensor.extract to comprehensive bufferization (details)
  40. [NFC] Inline variable to prevent unused variable warning (details)
  41. [ScalarEvolution] Fix overflow when computing max trip counts (details)
  42. AST: correct name decoration for swift async functions on Windows (details)
  43. [llvm-mca] [NFC] Formatting code (details)
  44. [clang] C++98 implicit moves are back with a vengeance (details)
  45. [OpenMP][NFC] Change comment style to eliminate warnings from GCC (details)
  46. [PowerPC] Add FI alignment check if the addressing mode is DS/DQ-Form, emit X-Form if necessary. (details)
  47. [RISCV] Use DIVUW/REMUW/DIVW instructions for i8/i16/i32 udiv/urem/sdiv when LHS is constant. (details)
  48. [libc++] NFC: Add comment for running macOS CI setup script remotely (details)
  49. [OpenMP] Fix one sign-compare warning from GCC (details)
  50. Fix utils/update_cc_test_checks/check-globals.test on stand-alone builds (details)
  51. [libc++] Add a CI job for macOS on arm64 hardware 🥳 (details)
  52. [sanitizer] Fix VSNPrintf %V on Windows (details)
  53. [analyzer][solver][NFC] Introduce ConstraintAssignor (details)
  54. [analyzer][solver][NFC] Refactor how we detect (dis)equalities (details)
  55. [NFC][sanitizer] Remove trailing whitespace (details)
  56. [test] Add a SCEV backedge computation test with an explicit zero stride (details)
  57. [CUDA] Only allow NVIDIA offload-arch during CUDA compilation. (details)
  58. [AArch64][GlobalISel] Legalize store <2 x i16> (details)
  59. [AArch64][GlobalISel] Legalize load <2 x i16> (details)
  60. Revert "[PowerPC][NFC] Power ISA features for Semachecking" (details)
  61. [PowerPC][NFC] Power ISA features for Semachecking (details)
  62. [WebAssembly] Generate checks for simd-load-store-alignment.ll (details)
  63. [InstCombine] Precommit tests for D105088 (NFC) (details)
  64. [Tests] Fix test broken by: 43c7ca8e4963 [AArch64][GlobalISel] Legalize store <2 x i16> (details)
  65. [SCEV] Strengthen inference of RHS > Start in howManyLessThans (details)
  66. Fix cuda-bad-arch.cu test. (details)
  67. [tests] Precommit a test case from D105216 (details)
  68. [gn build] (manually) port 303ddb60a2d2 (details)
  69. [LoopReroll] Add an extra defensive check to avoid SCEV assertion. (details)
  70. [NFC] Use CHECK-LABEL in trip-count-unknown-stride.ll (details)
  71. [mlir][Vector] Remove Vector TupleOp as it is unused (details)
  72. [lld][AMDGPU] Handle R_AMDGPU_REL16 relocation. (details)
  73. [libc++] [test] Add a missing `()` in TestEachIntegralType. (details)
  74. Revert "sanitizer_common: optimize memory drain" (details)
  75. [NFC][sanitizer] clang-format part of D105778 (details)
  76. [docs/llvm-cov] Document -compilation-dir (details)
  77. [libc] Add on float properties for precision floating point numbers in FloatProperties.h (details)
  78. [NFC][sanitizer] Move MemoryMapper out of SizeClassAllocator64 (details)
  79. [libcxx] [docs] Acknowledge that the library is known to work in some configs outside of what's tested in CI (details)
  80. [SCEV] Handle zero stride correctly in howManyLessThans (details)
  81. [sanitizer] Few more NFC changes from D105778 (details)
  82. [libc] Don't pass -fpie/-ffreestanding on Windows (details)
  83. [libc] Capture floating point encoding and arrange it sequentially in memory (details)
  84. [LLD] Adding support for RELA for CG Profile. (details)
  85. [WebAssembly] Run varargs codegen test with non-emscripten triple (details)
  86. Add more types to the LLVM dialect C API (details)
  87. [mlir][sparse] add support for std unary operations (details)
  88. [mlir][Tensor] Implement `reifyReturnTypeShapesPerResultDim` for `tensor.insert_slice`. (details)
  89. [PowerPC] Add PowerPC compare and multiply related builtins and instrinsics for XL compatibility (details)
  90. [NFC][MLIR][std] Clean up ArithmeticCastOps (details)
  91. [NFC][sanitizer] Rename some MemoryMapper members (details)
  92. [NFC][sanitizer] Exctract DrainHalfMax (details)
  93. [ScalarEvolution] Make isKnownNonZero handle more cases. (details)
  94. RegAlloc: Allow targets to split register allocation (details)
  95. [NFC][sanitizer] Don't store region_base_ in MemoryMapper (details)
  96. [NewPM][SimpleLoopUnswitch] Add option to not trivially unswitch (details)
  97. sanitizer_common: optimize memory drain (details)
  98. AMDGPU: Try to fix test failure with EXPENSIVE_CHECKS (details)
  99. [NFC][sanitizer] Move MemoryMapper template parameter (details)
  100. [NFC][sanitizer] Simplify MapPackedCounterArrayBuffer (details)
  101. [AArch64][GlobalISel] Mark v2s64 -> v2p0 G_INTTOPTR as legal (details)
  102. Revert "[NFC][sanitizer] Simplify MapPackedCounterArrayBuffer" (details)
  103. Revert "[SCEV] Handle zero stride correctly in howManyLessThans" (details)
  104. [AArch64] Fix AArch64::dsub's size (details)
  105. [AArch64] rm unused subreg's (details)
  106. [NFC][sanitizer] Simplify MapPackedCounterArrayBuffer (details)
  107. [CSSPGO][llvm-profgen] Allow multiple executable load segments. (details)
  108. [CSSPGO] Do not import pseudo probe desc in thinLTO (details)
  109. [NFC][CSSPGO] Rename the name of an enum value. (details)
  110. Fix test trying to write a spurious output file into the source (details)
  111. [SCEV] Handle zero stride correctly in howManyLessThans (details)
  112. [AbstractAttributor] Fold function calls to `__kmpc_is_spmd_exec_mode` if possible (details)
  113. [CSSPGO][llvm-profgen] Fix a missing initalization (details)
  114. Revert "[CSSPGO][llvm-profgen] Fix a missing initalization" (details)
  115. [CSSPGO][llvm-profgen] Fix a missing initalization (details)
  116. [AIX] Update testcase to use aix triple (details)
  117. [Polly] Fix typo. NFC. (details)
  118. [sanitizer] Convert script to python 3 (details)
  119. Revert "[clang] Refactor AST printing tests to share more infrastructure" (details)
  120. [sanitizer] Upgrade android scripts to python 3 (details)
  121. [sanitizer] Fix type error in python 3 (details)
  122. [RISCV] Support overloading for RVV miscellaneous functions. (details)
  123. Reformulate OrcJIT tutorial doc to make it more clear. (details)
  124. sanitizer_common: add simpler ThreadRegistry ctor (details)
  125. [libcxx] [test] Clarify weak_ptr_ret on Windows, remove a LIBCXX-WINDOWS-FIXME (details)
  126. [RISCV] Pass -u to linker correctly. (details)
  127. [RegisterCoalescer] Resolve conflict based on liveness of subregister (details)
  128. [NFC][AMDGPU] autogenerate kill-infinite-loop.ll checks (details)
  129. [AMDGPU] Don't handle export done when unify exit nodes (details)
  130. [clangd] Add CMake option to (not) link in clang-tidy checks (details)
  131. [AArch64][SME] Add matrix register definitions and parsing support (details)
  132. [AMDGPU] Precommit flat-scratch-init.ll test (details)
  133. [AMDGPU] Init scratch only if necessary (details)
  134. [RISCV] Fix the neutral element in vector 'fadd' reductions (details)
  135. [mlir][SCF] populateSCFStructuralTypeConversionsAndLegality WhileOp support (details)
  136. [InstCombine] Fold (select C, (gep Ptr, Idx), Ptr) -> (gep Ptr, (select C, Idx, 0)) (PR50183) (details)
  137. [DebugInfo] Correctly update dbg.values with duplicated location ops (details)
  138. [NFC][PowerPC] Added test to check regsiter allocation for ACC registers (details)
  139. [gn build] (manually) merge 462d4de35b0c (details)
  140. Revert rGb803294cf78714303db2d3647291a2308347ef23 : "[InstCombine] Fold (select C, (gep Ptr, Idx), Ptr) -> (gep Ptr, (select C, Idx, 0)) (PR50183)" (details)
  141. [gn build] Port c08dabb0f476 (details)
  142. [X86] Implement smarter instruction lowering for FP_TO_UINT from f32/f64 to i32/i64 and vXf32/vXf64 to vXi32 for SSE2 and AVX2 by using the exact semantic of the CVTTPS2SI instruction. (details)
  143. [lldb][docs] Remove mention of subversion. NFC. (details)
  144. [NFC] [Coroutines] Remove unused CoroFree (details)
  145. [InstCombine] Fold (select C, (gep Ptr, Idx), Ptr) -> (gep Ptr, (select C, Idx, 0)) (PR50183) (REAPPLIED) (details)
  146. [RemoveRedundantDebugValues] Add a Pass that removes redundant DBG_VALUEs (details)
  147. [lld][MachO] Code cleanup (details)
  148. [Analyzer][solver] Add dump methods for (dis)equality classes. (details)
  149. [SLP] match logical and/or as reduction candidates (details)
  150. ARM: reuse existing libcall global variable if possible. (details)
  151. [docs] Update CMake cross compiling guide link (details)
  152. [mlir][linalg] Fix typo in ExtractSliceOfPadTensorSwapPattern (details)
  153. [AIX] Enable dollar sign as PC in inlineasm (details)
  154. [flang][OpenMP] Fix semantic check of test case in taskloop simd construct (details)
  155. [Lexer] Fix bug in `makeFileCharRange` called on split tokens. (details)
  156. [runtimes] NFCI: Drop intermediate CMake variable TARGET_TRIPLE (details)
  157. [SLP]Workaround for InsertSubVector cost. (details)
  158. [AMDGPU] Check llc-pipeline.ll with -match-full-lines -strict-whitespace (details)
  159. Combine two diagnostics into one and correct grammar (details)
  160. [CostModel][AArch64] Make loads/stores of <vscale x 1 x eltty> invalid. (details)
  161. GlobalISel: Handle lowering non-power-of-2 extloads (details)
  162. [LV] Print remark when loop cannot be vectorized due to invalid costs. (details)
  163. [InstCombine] add tests for icmp with constant offset and no-wrap flags; NFC (details)
  164. [InstCombine] reorder icmp with offset folds for better results (details)
  165. [ARM] Lower v16i8 -> i64 VMLA reductions. (details)
  166. [ELF] --fortran-common: prefer STB_WEAK to COMMON (details)
  167. [WebAssembly] Remove datalayout strings from llc tests (details)
  168. [runtimes] Inherit the TARGET_TRIPLE that may be set by LLVM (details)
  169. [WebAssembly] Codegen for v128.loadX_lane instructions (details)
  170. [SelectionDAG] Add an overload of getStepVector that assumes step 1. (details)
  171. Demangle: correct swift_async demangling for Microsoft scheme (details)
  172. [Verifier] Improve incompatible attribute type check (details)
  173. Remove uses of deprecated target AllPassesAndDialectsNoRegistration in Bazel (NFC) (details)
  174. [scudo] Don't enabled MTE for small alignment (details)
  175. [ARM] Move add(VMLALVA(A, X, Y), B) to VMLALVA(add(A, B), X, Y) (details)
  176. [NFC][PhaseOrdering] Add test for the lack of CSE after SimplifyCFG (PR51092) (details)
  177. [Attributes] Use single method to fetch type from AttributeSet (NFC) (details)
  178. [NFC] Drop redundant check prefixes in newly added test file (details)
  179. [runtimes] Bring back TARGET_TRIPLE (details)
  180. [Bazel] Uniformly export all MLIR td files (details)
  181. [SLP] Fix case of variable name. NFCI. (details)
  182. [docs] Fix :option:`--file-header` reference in llvm-readelf.rst after D105532 (details)
  183. [SLP][NFC]Fix variables names, NFC. (details)
  184. [AMDGPU] Add TII::isIgnorableUse() to allow VOP rematerialization (details)
  185. [tests] Stablize tests for possible change in deref semantics (details)
  186. [libcxx] [test] Remove a LIBCXX-WINDOWS-FIXME in trivial_abi/unique_ptr_ret (details)
  187. Global variables with strong definitions cannot be freed (details)
  188. [mlir] NFC - Add AffineMap::replace variant with dim/symbol inference (details)
  189. [Support] Get correct number of physical cores on Apple Silicon (details)
  190. [lldb] Always call DestroyImpl from Process::Finalize (details)
  191. [lldb] Make TargetList iterable (NFC) (details)
  192. [asan][clang] Add flag to outline instrumentation (details)
  193. [tests] Stablize tests for possible change in deref semantics (details)
  194. [mlir][affine] Add single result affine.min/max -> affine.apply canonicalization. (details)
  195. [AArch64] Fix selection of G_UNMERGE <2 x s16> (details)
  196. [SimpleLoopUnswitch] Don't non-trivially unswitch loops with catchswitch exits (details)
  197. Precommit test for D106017 (details)
  198. [llvm-strip][WebAssembly] Support strip flags (details)
  199. [Polly] Fix misleading debug message. NFC. (details)
  200. [ARM] Fix RELA relocations for 32bit ARM. (details)
  201. [docs][OpaquePtr] Remove finished task (details)
  202. [clang-format] Make BreakAfterReturnType work with K&R C functions (details)
  203. [libomptarget] Keep the Shadow Pointer Map up-to-date (details)
  204. [Support] Turn on SupportTest for Apple Silicon (details)
  205. [GlobalOpt] Fix a miscompile when evaluating struct initializers. (details)
  206. [WebAssembly] Codegen for v128.storeX_lane instructions (details)
  207. [clang] Refactor AST printing tests to share more infrastructure (details)
  208. [libc++] NFCI: Restore code duplication in wrap_iter, with test. (details)
  209. [AMDGPU] Use update_test_checks.py script for annotate kernel features tests. (details)
  210. libclc: Add -cl-no-stdinc to clang flags on clang >=13 (details)
  211. [OpenCL][NFC] opencl-c.h: reorder atomic operations (details)
  212. [OpenCL] opencl-c.h: CL3.0 generic address space (details)
  213. [PowerPC] Generate inlined quadword lock free atomic operations via AtomicExpand (details)
  214. [gn build] Port b9c3941cd61d (details)
  215. [mlir][linalg][NFC] Factor out tile generation in makeTiledShapes (details)
  216. [mlir][linalg] Add optional output operand to PadTensorOp (details)
  217. [mlir][NFC] Move asOpFoldResult helper functions to StaticValueUtils (details)
  218. [mlir][linalg] Tile PadTensorOp (details)
  219. [mlir][linalg] Fix Windows build (details)
  220. [mlir][linalg] Improve codegen of ExtractSliceOfPadTensorSwapPattern (details)
  221. [mlir][linalg] Improve codegen when tiling PadTensor evenly (details)
  222. [PowerPC][NFC] add testcase for update-form preparation with non-const increment (details)
  223. Defend early against operation created without a registered dialect (details)
  224. [Attributor] AACallEdges, Add a way to ask nonasm unknown callees (details)
  225. Revert "Defend early against operation created without a registered dialect" (details)
  226. [MLIR] [Python] Add `owner` to PyValue and fix its parent reference (details)
  227. Defend early against operation created without a registered dialect (details)
  228. [Coroutines] Run coroutine passes by default (details)
  229. [AMDGPU] Reserve AMDGPU ELF e_flags machine 0x44 (details)
  230. [2/2][RemoveRedundantDebugValues] Add a Pass that removes redundant DBG_VALUEs (details)
  231. [clang][Analyzer] Add symbol uninterestingness to bug report. (details)
  232. [gn build] Port b0d38ad0bc25 (details)
  233. [mlir][crunner] fix bug in memref copy for rank 0 (details)
  234. [llvm][tools] Hide unrelated llvm-bcanalyzer options (details)
  235. Fix undeduced type assert (details)
  236. Fixes memory sanitizer 'use-of-uninitialized-value' diagnostic. (details)
  237. [NFC] [hwasan] Split argument logic into functions. (details)
  238. [AArch64][SME] Add outer product instructions (details)
  239. [Test] We can benefit from pipelining of ymm load/stores (details)
  240. [sanitizer] Fix __sanitizer_kernel_sigset_t endianness issue (details)
  241. [sanitizer] Force TLS allocation on s390 (details)
  242. [TSan] Align thread_registry_placeholder (details)
  243. [TSan] Use zeroext for function parameters (details)
  244. [TSan] Build ignore_lib{0,1,5} tests with -fno-builtin (details)
  245. [TSan] Define PTHREAD_ABI_BASE for SystemZ (details)
  246. [TSan] Define C/C++ address ranges for SystemZ (details)
  247. [TSan] Add SystemZ longjmp support (details)
  248. [TSan] Disable __TSAN_HAS_INT128 on SystemZ (details)
  249. [TSan] Intercept __tls_get_addr_internal and __tls_get_offset on SystemZ (details)
  250. [TSan] Adjust tests for SystemZ (details)
  251. [TSan] Enable SystemZ support (details)
  252. [TSan] Add SystemZ SANITIZER_GO support (details)
  253. [AMDGPU] Use isMetaInstruction for instruction size (details)
  254. [AArch64][GlobalISel] Optimise lowering for some vector types for min/max (details)
  255. [mlir][nvvm]: Add math::Exp2Op lowering to NVVM. (details)
  256. [MIPS] Refresh ashr test checks. NFCI. (details)
  257. [InstCombine] Strip inbounds from (select C, (gep Ptr, Idx), Ptr) -> (gep Ptr, (select C, Idx, 0)) fold (details)
  258. [NVPTX] Add selp.f32 checks to select(cond,fpbinop(),fpbinop()) tests (details)
  259. [VP][NFC] Correct formatting in unit test (details)
  260. [runtimes] Serialize all Lit params instead of passing them to add_lit_testsuite (details)
  261. [libc++] Implement views::all_t and ranges::viewable_range (details)
  262. Reapply "[DebugInfo] Enable variadic debug value salvaging" (details)
  263. [libc++] Mark failing rel_ops test as XFAIL in back-deployment (details)
  264. [mlir][linalg] Improve implementation of hoist padding. (details)
  265. [LV] Fix determinism for failing scalable-call.ll test. (details)
  266. [TTI] Consistently make getMinVectorRegisterBitWidth() methods const. NFCI. (details)
  267. [mlir][rocdl] Add math::Exp2Op lowering to ROCDL (details)
  268. [SimplifyCFG] Rerun PHI deduplication after common code sinkinkg (PR51092) (details)
  269. Fix documentation; NFC (details)
  270. MachO: don't emit L... private symbols in do_not_dead_strip sections. (details)
  271. [ARM] Expand types handled in VQDMULH recognition (details)
  272. [docs] More CMAKE variable documentation (details)
  273. MachO: fix Clang test broken by dropping private labels in LLVM. (details)
  274. [OpenCL] Add support of __opencl_c_program_scope_global_variables feature macro (details)
  275. Revert "[LV] Print remark when loop cannot be vectorized due to invalid costs." (details)
  276. [Analyzer][solver] Remove unused functions (details)
  277. [NVPTX] Tweak fast-math tests to avoid select(binop(x,y),binop(x,z)) fold (details)
  278. [mlir][sparse] replace linalg.copy with memref.copy (details)
  279. [DAG] Fold select(cond,binop(x,y),binop(x,z)) -> binop(x,select(cond,y,z)) (details)
  280. Revert "[AbstractAttributor] Fold function calls to `__kmpc_is_spmd_exec_mode` if possible" (details)
  281. [PowerPC] Add PowerPC rotate related builtins and emit target independent code for XL compatibility (details)
  282. tsan: make obtaining current PC faster (details)
  283. [AsmParser] Unify parsing of attributes (details)
  284. [LV] Enable vectorization of multiple exit loops w/computable exit counts (details)
  285. [Bazel] Update for 01bdb0f75efb (details)
  286. [InstCombine] Look through invariant group intrinsics when removing malloc (details)
  287. [LangRef] Add elementtype attribute (details)
  288. [IR] Add elementtype attribute (details)
  289. [libc++] Add a CMake target to re-generate files and revamp CONTRIBUTING.rst (details)
  290. [mlir][sparse] remove linalg-to-loops from integration tests (details)
  291. Enable Flang by default in the test-release.sh script (details)
  292. [flang][driver] Randomise the names of the unparsed files (details)
  293. [mlir][sparse] add shift ops support (details)
  294. [test] Avoid llvm-nm one-dash long options (details)
  295. [llvm-nm] Remove one-dash long options except -arch (details)
  296. [AMDGPU] Refine -O0 and -O1 passes. (details)
  297. [lld-macho] Add LTO cache support (details)
  298. [WebAssembly] Fixed LLD generation of 64-bit __wasm_apply_data_relocs (details)
  299. [GlobalISel] Fix infinite loop in reassociationCanBreakAddressingModePattern (details)
  300. Revert "[SLP]Workaround for InsertSubVector cost." (details)
  301. [llvm-exegesis] Fix missing-headers build errors. (details)
  302. [test] Avoid llvm-readelf/llvm-readobj one-dash long options and deprecated aliases (e.g. --file-headers) (details)
  303. [libc++] NFC: Reindent the run-buildbot script (details)
  304. [SCEV] Fix unsound reasoning in howManyLessThans (details)
  305. tsan: strip top inlined internal frames (details)
  306. [InstCombine] Add 3-operand gep test with different ptr and same indices (details)
  307. Fix "unknown pragma 'GCC'" MSVC warning. NFCI. (details)
  308. [PowerPC] Fix popcntb XL Compat Builtin for 32bit (details)
  309. [ARM][LowOverheadLoops] Make some stack spills valid for tail predication (details)
  310. [InstCombine] Add select(cond,gep(gep(x,y),z),gep(x,y)) tests from PR51069 (details)
  311. [Verifier] Use isIntrinsic() (NFC) (details)
  312. [ELF][test] Rework non-preemptible ifunc tests (details)
  313. [ELF] Don't define __rela_iplt_start for -pie/-shared (details)
  314. [libc++/abi] Fix broken Lit feature no-noexcept-function-type (details)
  315. [unittest] Exercise SCEV's udiv and udiv ceiling routines (details)
  316. tsan: lock ScopedErrorReportLock around fork (details)
  317. [M68k][GloballSel] LegalizerInfo implementation (details)
  318. [NVPTX, CUDA] Add .and.popc variant of the b1 MMA instruction. (details)
  319. [mlir][sparse] add int64 storage type to sparse tensor runtime support library (details)
  320. [Driver] Fix compiler-rt lookup for x32 (details)
  321. utils: fix broken assertion in revert_checker (details)
  322. [ObjCARC] Use objc_msgSend instead of llvm.objc.msgSend in tests (details)
  323. [libc] Relocate the closing directive of #ifdef (details)
  324. [libcxx] [test] Fix mismatches between aligned operator new and std::free (details)
  325. [runtimes] Don't try passing --target flags to GCC (details)
  326. [AIX][XCOFF][Bug-Fixed] parse the parameter type of the traceback table (details)
  327. [AArch64][GlobalISel] Clamp <n x p0> vecs when legalizing G_EXTRACT_VECTOR_ELT (details)
  328. [mlir] Enable cleanup of single iteration reduction loops being sibling-fused maximally (details)
  329. [PowerPC][NFC] Add the missing 'REQUIRES: powerpc-registered-target.' in the builtins' front end test cases for XL compatibility (details)
  330. [Verifier] Extend address taken check for unknown intrinsics (details)
  331. [SLP] avoid leaking poison in reduction of safe boolean logic ops (details)
  332. [X86] Fix handling of maskmovdqu in X32 (details)
  333. [DependenceAnalysis] Guard analysis using getPointerBase(). (details)
  334. [LLDB][GUI] Add Process Attach form (details)
  335. [libc] Fix typos in x86_64/FEnv.h (details)
  336. GlobalISel: Introduce GenericMachineInstr classes and derivatives for idiomatic LLVM RTTI. (details)
  337. [AbstractAttributor] Fold function calls to `__kmpc_is_spmd_exec_mode` if possible (details)
  338. [PowerPC] Add PowerPC population count, reversed load and store related builtins and instrinsics for XL compatibility (details)
  339. [NFC][hwasan] Remove default arguments in internal class (details)
  340. [lldb] Add AllocateMemory/DeallocateMemory to the SBProcess API (details)
  341. GlobalISel: Track argument pointeriness with arg flags (details)
  342. AMDGPU/GlobalISel: Fix incorrect memory types in test (details)
  343. GlobalISel: Surface offsets parameter from ComputeValueVTs (details)
  344. Revert "tsan: make obtaining current PC faster" (details)
  345. [asan] Slightly modified the documentation. (details)
  346. [lld-macho] Use intermediate arrays to store opcodes (details)
  347. [mlir][spirv] Add support for GLSL FMix (details)
  348. [test] Use double pound to denote comments. (details)
  349. [Frontend] Only compile modules if not already finalized (details)
  350. [libc++] Add a job running GCC with C++11 (details)
  351. [NFC][OpenMP][Offloading] Replaced explicit parallel level computation with function `__kmpc_parallel_level` (details)
  352. [gn build] port 766a08df12c1 (details)
  353. [gn build] Port 766a08df12c1 (details)
  354. [MLIR] [Python ODS] Use @builtins.property for cases where 'property' is already defined (details)
  355. Use ManagedStatic and lazy initialization of cl::opt in libSupport to make it free of global initializer (details)
  356. Revert "Use ManagedStatic and lazy initialization of cl::opt in libSupport to make it free of global initializer" (details)
  357. [Attributor] Add support for compound assignment for ChangeStatus (details)
  358. [lld-macho] Optimize bind opcodes with multiple passes (details)
  359. [TableGen] Allow isAllocatable inheritence from any superclass (details)
  360. [analyzer] Model comparision methods of std::unique_ptr (details)
  361. [LSR] Handle case 1*reg => reg. PR50918 (details)
  362. Fix typo in test (details)
  363. [profile] Decommit memory after counter relocation (details)
  364. [debugserver] Un-conditionalize code guarded by macOS 10.10 checks (details)
  365. Fix mismatch between the provisioning of asyncExecutors and the actual thread count currently in the context (NFC) (details)
  366. Use ManagedStatic and lazy initialization of cl::opt in libSupport to make it free of global initializer (details)
  367. [analyzer] Handle << operator for std::unique_ptr (details)
  368. [llvm-mca][JSON] Store extra information about driver flags used for the simulation (details)
  369. [llvm][tools] Hide unrelated llvm-cfi-verify options (details)
  370. Revert "[llvm][tools] Hide unrelated llvm-cfi-verify options" (details)
  371. Revert "Use ManagedStatic and lazy initialization of cl::opt in libSupport to make it free of global initializer" (details)
  372. Use ManagedStatic and lazy initialization of cl::opt in libSupport to make it free of global initializer (details)
  373. Reformat files. (details)
  374. [analyzer] Do not assume that all pointers have the same bitwidth as void* (details)
  375. [llvm][tools] Hide unrelated llvm-cfi-verify options (details)
  376. [MLIR][NFC] Improve doc comment and delete stale comment (details)
  377. [RISCV] Lower more BUILD_VECTOR sequences to RVV's VID (details)
  378. Reland "[LV] Print remark when loop cannot be vectorized due to invalid costs." (details)
  379. [lldb][AArch64] Refactor memory tag range handling (details)
  380. [AArch64][SME] Add load and store instructions (details)
  381. [LV] Avoid scalable vectorization for loops containing alloca (details)
  382. [AArch64] Update Cortex-A55 SchedModel to improve LDP scheduling (details)
  383. [mlir] add an interface to support custom types in LLVM dialect pointers (details)
  384. Use update_test_checks.py to auto-generate check lines (details)
  385. [mlir] Move linalg::Expand/CollapseShapeOp to memref dialect. (details)
  386. [PowerPC][AIX] Add warning when alignment is incompatible with XL (details)
  387. [AMDGPU][MC] Added missing isCall/isBranch flags (details)
  388. SubstTemplateTypeParmType can contain an 'auto' type in their replacement type (details)
  389. [SLP] add tests for poison-safe bool logic reductions; NFC (details)
  390. [InstrRef][FastISel] Support emitting DBG_INSTR_REF from fast-isel (details)
  391. AMDGPU/GlobalISel: Redo kernel argument load handling (details)
  392. AMDGPU/GlobalISel: Preserve more memory types (details)
  393. GlobalISel: Remove dead function (details)
  394. [mlir] replace llvm.mlir.cast with unrealized_conversion_cast (details)
  395. [mlir] add missing build dependency (details)
  396. [lldb][AArch64] Add tag packing and repetition memory tag manager (details)
  397. Revert "[RISCV] Lower more BUILD_VECTOR sequences to RVV's VID" (details)
  398. [PowerPC] Update Refactored Load/Store Implementation, XForm VSX Patterns, and Tests (details)
  399. [runtimes] Simplify how we set the target triple (details)
  400. [PowerPC] Updated the error message of MASSV pass to mention vectorization (details)
  401. [Bazel] Delete deprecated gentbl rule (details)
  402. [mlir] Remove unused functions in LinalgOps.cpp (details)
  403. [libc++] CI: Setup BuildKite agents through launchd (details)
  404. AArch64/GlobalISel: Update tests to use correct memory types (details)
  405. GlobalISel: Preserve memory type for memset expansion (details)
  406. Mips/GlobalISel: Use LLT form of getMachineMemOperand (details)
  407. [libc++] ci: Create ~/Library/LaunchAgents if it does not exist yet (details)
  408. [LoopInterchange] Check lcssa phis in the inner latch in scenarios of multi-level nested loops (details)
  409. [flang][driver] Fix output filename generation in `flang` (details)
  410. [libcxx][modularisation] adds several headers to the module map (details)
  411. [NFC] Fix typo intrinisic (details)
  412. [Verifier] Require same signature for intrinsic calls (details)
  413. [RISCV] Add curly braces around a case body that declares variables. NFC (details)
  414. [RISCV] Teach constant materialization that it can use zext.w at the end with Zba to reduce number of instructions. (details)
  415. [MachineVerifier] Diagnose invalid INSERT_SUBREGs (details)
  416. [DAG] SelectionDAG::MaskedElementsAreZero - assert we're calling with a vector. NFCI. (details)
  417. [X86] Regenerate twoaddr-lea.ll test checks. (details)
  418. Revert "[MachineVerifier] Diagnose invalid INSERT_SUBREGs" (details)
  419. [ELF][test] Avoid llvm-readelf/llvm-readobj one-dash long options (details)
  420. [SCEV] Add tests for known negative strides in trip count logic (details)
  421. [X86FixupLEAs] Try again to transform the sequence LEA/SUB to SUB/SUB (details)
  422. [test] Extend negative stride backedge tests to cover signed comparisons (details)
  423. sanitizer_common: add Semaphore (details)
  424. [docs] Update llvm-readelf supported options after D105532 (details)
  425. [RISCV] Refactor where in the multiclass hierarchy we add commutable VFMADD/VFMACC instructions. NFC (details)
  426. [RISCV] Use tail agnostic policy for fixed vector vwmacc(u). (details)
  427. [RISCV] Rename the fixed vector vwmacc tests to have the 'm' in their filenames. NFC (details)
  428. [Clang] Add an empty builtins.h file. (details)
  429. [mlir][sparse] minor cleanup of Merger (details)
  430. [tests] Precommit test for D104140 (details)
  431. [compiler-rt] change write order of frexpl & frexpf so it doesn't corrupt stack ids (details)
  432. sanitizer_common: link Synchronization.lib on Windows (details)
  433. [OpenMP] Rework OpenMP remarks (details)
  434. [OpenMP] Add IDs to OpenMP remarks (details)
  435. [OpenMP] Add remark documentation to the OpenMP webpage (details)
  436. [OpenMP][NFC] Update the comment header for optimizations. (details)
  437. [PowerPC] Implement XL compact math builtins (details)
  438. [X86][SSE] combineX86ShufflesRecursively - bail if constant folding fails due to oneuse limits. (details)
  439. [ARM] Extra MLA vecreduce tests. NFC (details)
  440. [test] Avoid llvm-readelf/llvm-readobj one-dash long options (details)
  441. [llvm-readelf/llvm-readobj] Remove one-dash long options (details)
  442. Add a scalar argument case for the Fortran spread intrinsic unit test. (details)
  443. [RISCV] Compose vector subregs hierarchically (details)
  444. [gn build] (semi-manually) port 6a4054ef060b (details)
  445. [PATCH] D105827: [SLP]Workaround for InsertSubVector cost. (details)
  446. [libcxx] [test] Fix experimental/memory.resource.adaptor.mem/db_deallocate on Windows (details)
  447. [NFC][compiler-rt][test] pass through MallocNanoZone to iossim env (details)
  448. [COFF][test] Fix llvm-readobj tests (details)
  449. [GlobalISel] Fix non-pow-2 legalization of s56 stores. (details)
  450. [gn build] Port 0bf4b81d57b0 (details)
  451. [SLP]Improve calculations of the cost for reused/reordered scalars. (details)
  452. [Bazel] Use bazel_skylib paths for paths munging (details)
  453. [Bazel] Make gentbl_test compatible with coverage (details)
  454. [Bazel] Add examples to bazelignore (details)
  455. Add `lli` as dependency of MLIR integration tests (details)
  456. [PowerPC] Implement intrinsics for mtfsf[i] (details)
  457. ThinLTO: Fix inline assembly references to static functions with CFI (details)
  458. Revert "ThinLTO: Fix inline assembly references to static functions with CFI" (details)
  459. [ARM] Fix for matching reductions that are both sext and zext. (details)
  460. Build libSupport with -Werror=global-constructors (NFC) (details)
  461. [sanitizer] Fix test build on Windows (details)
  462. [Bazel] Delete blank line to make buildifier happy (details)
  463. [libcxx][modules] protects users from relying on libc++ detail headers (1/n) (details)
  464. Add a mutex to guard access to the ThreadPlanStack class (details)
  465. Revert "Build libSupport with -Werror=global-constructors (NFC)" (details)
  466. [lit] Add --xfail-not/LIT_XFAIL_NOT (details)
  467. [ScalarEvolution] Fix overflow in computeBECount. (details)
  468. [CSSPGO] Turn on unique linkage name by default for pseudo probe. (details)
  469. [trace][intel pt] Implement the Intel PT cursor (details)
  470. [NFC][compiler-rt][test] when using ptrauth, strip before checking if poisoned (details)
  471. AMDGPU/GlobalISel: Fix some incorrect memory types in tests (details)
  472. AMDGPU/GlobalISel: Add a few tests for struct arguments (details)
  473. Mips/GlobalISel: Remove leftover dead code (details)
  474. [CSSPGO] Turn on iterative-BFI for CSSPGO (details)
  475. [Analysis] Remove isJoinDivergent (NFC) (details)
  476. [AMDGPU] Tidy SReg/SGPR definitions using template class (details)
  477. [ORC] Remove LLVM-side MachO Platform runtime support. (details)
  478. [RISCV] Make VLEN no greater than 65536 (details)
  479. [mlir][vector] Refactor TransferReadToVectorLoadLowering (details)
  480. [mlir][vector] Remove vector.transfer_read/write to LLVM lowering (details)
  481. [ORC] Fix typo in declaration (details)
  482. [OpenMP] Codegen aggregate for outlined function captures (details)
  483. [sanitizers] Fix building on case sensitive mingw platforms (details)
  484. [RISCV] Manually emit the best shift for VSCALE lowering to improve codegen. (details)
Commit b6b53ffef4414ed62701a63ad28e70cfd9d26191 by jonathanchesterfield
[libomptarget][devicertl] Remove branches around setting parallelLevel

Simplifies control flow to allow store/load forwarding

This change folds two basic blocks into one, leaving a single store to parallelLevel.
This is a step towards spmd kernels with sufficiently aggressive inlining folding
the loads from parallelLevel and thus discarding the nested parallel handling
when it is unused.

Transform:
```
int threadId = GetThreadIdInBlock();
if (threadId == 0) {
  parallelLevel[0] = expr;
} else if (GetLaneId() == 0) {
  parallelLevel[GetWarpId()] = expr;
}
// =>
if (GetLaneId() == 0) {
  parallelLevel[GetWarpId()] = expr;
}
// because
unsigned GetLaneId() { return GetThreadIdInBlock() & (WARPSIZE - 1);}
// so whenever threadId == 0, GetLaneId() is also 0.
```

That replaces a store in two distinct basic blocks with as single store.

A more aggressive follow up is possible if the threads in the warp/wave
race to write the same value to the same address. This is not done as
part of this change.

```
if (GetLaneId() == 0) {
  parallelLevel[GetWarpId()] = expr;
}
// =>
parallelLevel[GetWarpId()] = expr;
// because
unsigned GetWarpId() { return GetThreadIdInBlock() / WARPSIZE; }
// so GetWarpId will index the same element for every thread in the warp
// and, because expr is lane-invariant in this case, every lane stores the
// same value to this unique address
```

Reviewed By: tianshilei1992

Differential Revision: https://reviews.llvm.org/D105699
The file was modifiedopenmp/libomptarget/deviceRTLs/common/src/omptarget.cu
Commit b205f2bb8938447638e9ddc4ee1f6b82caeb1ad3 by abidh
[AMDGPU] Handle s_branch to another section.

Currently, if target of s_branch instruction is in another section, it will fail with the error of undefined label.  Although in this case, the label is not undefined but present in another section. This patch tries to handle this issue. So while handling fixup_si_sopp_br fixup in getRelocType, if the target label is undefined we issue an error as before. If it is defined, a new relocation type R_AMDGPU_REL16 is returned.

This issue has been reported in https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100181 and https://bugs.llvm.org/show_bug.cgi?id=45887. Before https://reviews.llvm.org/D79943, we used to get an crash for this scenario. The crash is fixed now but the we still get an undefined label error.  Jumps to other section can arise with hold/cold splitting.

A patch to handle the relocation in lld will follow shortly.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D105760
The file was modifiedllvm/test/tools/llvm-readobj/ELF/reloc-types-elf-amdgpu.test
The file was modifiedllvm/docs/AMDGPUUsage.rst
The file was modifiedllvm/include/llvm/BinaryFormat/ELFRelocs/AMDGPU.def
The file was modifiedllvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUELFObjectWriter.cpp
The file was modifiedllvm/test/MC/AMDGPU/reloc.s
Commit bb0166dc72791e2cefdb0c8dc9e495ea0555357b by georgios.rokos
[libomptarget] Update device pointer only if needed

Currently, libomptarget will always perform a host-to-device memory transfer in
order to update the device pointer of a PTR_AND_OBJ entry. This is not always
necessary because the device pointer may have been set to the correct pointee
address already, so we can eliminate the redundant memory transfer.
The file was modifiedopenmp/libomptarget/src/omptarget.cpp
The file was addedopenmp/libomptarget/test/mapping/device_ptr_update.c
Commit 9c90725eaee5a00e5dd450e51c4070afd7081472 by frgossen
[MLIR] Fix documentation of the `ExecutionEngine` in the toy tutorial example

Differential Revision: https://reviews.llvm.org/D105813
The file was modifiedmlir/docs/Tutorials/Toy/Ch-6.md
Commit 3cee36c5acdb292c331818c553bfb8e5abbdb95e by llvm-dev
[X86][SSE] X86ISD::FSETCC nodes (cmpss/cmpsd) return a 0/-1 allbits signbits result (REAPPLIED)

Annoyingly, i686 cmpsd handling still fails to remove the unnecessary neg(and(x,1))

Reapplied rGe4aa6ad13216 with fix for intrinsic variants of the opcode which uses a vector return type
The file was modifiedllvm/test/CodeGen/X86/known-signbits-vector.ll
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
Commit 4709d9d5be79835a5a8751dba83e9150dbce9e6e by lebedev.ri
[libomp] ompd_init(): fix heap-buffer-overflow when constructing libompd.so path

There is no guarantee that the space allocated in `libname`
is enough to accomodate the whole `dl_info.dli_fname`,
because it could e.g. have an suffix  - `.5`,
and that highlights another problem - what it should do about suffxies,
and should it do anything to resolve the symlinks before changing the filename?

```
$ LD_LIBRARY_PATH="$LD_LIBRARY_PATH:/usr/local/lib"  ./src/utilities/rstest/rstest -c /tmp/f49137920.NEF
dl_info.dli_fname "/usr/local/lib/libomp.so.5"
strlen(dl_info.dli_fname) 26
lib_path_length 14
lib_path_length + 12 26
=================================================================
==30949==ERROR: AddressSanitizer: heap-buffer-overflow on address 0x60300000002a at pc 0x000000548648 bp 0x7ffdfa0aa780 sp 0x7ffdfa0a9f40
WRITE of size 27 at 0x60300000002a thread T0
    #0 0x548647 in strcpy (/home/lebedevri/rawspeed/build-Clang-SANITIZE/src/utilities/rstest/rstest+0x548647)
    #1 0x7fb9e3e3d234 in ompd_init() /repositories/llvm-project/openmp/runtime/src/ompd-specific.cpp:102:5
    #2 0x7fb9e3dcb446 in __kmp_do_serial_initialize() /repositories/llvm-project/openmp/runtime/src/kmp_runtime.cpp:6742:3
    #3 0x7fb9e3dcb40b in __kmp_get_global_thread_id_reg /repositories/llvm-project/openmp/runtime/src/kmp_runtime.cpp:251:7
    #4 0x59e035 in main /home/lebedevri/rawspeed/build-Clang-SANITIZE/../src/utilities/rstest/rstest.cpp:491
    #5 0x7fb9e3762d09 in __libc_start_main csu/../csu/libc-start.c:308:16
    #6 0x4df449 in _start (/home/lebedevri/rawspeed/build-Clang-SANITIZE/src/utilities/rstest/rstest+0x4df449)

0x60300000002a is located 0 bytes to the right of 26-byte region [0x603000000010,0x60300000002a)
allocated by thread T0 here:
    #0 0x55cc5d in malloc (/home/lebedevri/rawspeed/build-Clang-SANITIZE/src/utilities/rstest/rstest+0x55cc5d)
    #1 0x7fb9e3e3d224 in ompd_init() /repositories/llvm-project/openmp/runtime/src/ompd-specific.cpp:101:17
    #2 0x7fb9e3762d09 in __libc_start_main csu/../csu/libc-start.c:308:16

SUMMARY: AddressSanitizer: heap-buffer-overflow (/home/lebedevri/rawspeed/build-Clang-SANITIZE/src/utilities/rstest/rstest+0x548647) in strcpy
Shadow bytes around the buggy address:
  0x0c067fff7fb0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
  0x0c067fff7fc0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
  0x0c067fff7fd0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
  0x0c067fff7fe0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
  0x0c067fff7ff0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
=>0x0c067fff8000: fa fa 00 00 00[02]fa fa fa fa fa fa fa fa fa fa
  0x0c067fff8010: fa fa fa fa fa fa fa fa fa fa fa fa fa fa fa fa
  0x0c067fff8020: fa fa fa fa fa fa fa fa fa fa fa fa fa fa fa fa
  0x0c067fff8030: fa fa fa fa fa fa fa fa fa fa fa fa fa fa fa fa
  0x0c067fff8040: fa fa fa fa fa fa fa fa fa fa fa fa fa fa fa fa
  0x0c067fff8050: fa fa fa fa fa fa fa fa fa fa fa fa fa fa fa fa
Shadow byte legend (one shadow byte represents 8 application bytes):
  Addressable:           00
  Partially addressable: 01 02 03 04 05 06 07
  Heap left redzone:       fa
  Freed heap region:       fd
  Stack left redzone:      f1
  Stack mid redzone:       f2
  Stack right redzone:     f3
  Stack after return:      f5
  Stack use after scope:   f8
  Global redzone:          f9
  Global init order:       f6
  Poisoned by user:        f7
  Container overflow:      fc
  Array cookie:            ac
  Intra object redzone:    bb
  ASan internal:           fe
  Left alloca redzone:     ca
  Right alloca redzone:    cb
==30949==ABORTING
Aborted
```
The file was modifiedopenmp/runtime/src/ompd-specific.cpp
Commit ab76101f40f80bbec82073fc5bfddd7203e63a52 by anton.zabaznov
[OpenCL] Add support of __opencl_c_read_write_images feature macro

This feature requires support of __opencl_c_images, so diagnostics for that is provided as well

Reviewed By: Anastasia

Differential Revision: https://reviews.llvm.org/D104915
The file was modifiedclang/include/clang/Basic/DiagnosticCommonKinds.td
The file was modifiedclang/include/clang/Basic/DiagnosticSemaKinds.td
The file was modifiedclang/include/clang/Basic/OpenCLOptions.h
The file was modifiedclang/lib/Sema/SemaDeclAttr.cpp
The file was modifiedclang/lib/Basic/OpenCLOptions.cpp
The file was modifiedclang/test/Misc/opencl-c-3.0.incorrect_options.cl
The file was modifiedclang/test/SemaOpenCL/unsupported-image.cl
The file was modifiedclang/lib/Basic/Targets.cpp
The file was modifiedclang/test/SemaOpenCL/access-qualifier.cl
Commit c99e17fef5f34ac536192fa7b915641f1962c7b9 by llvm-dev
[InstCombine] Pre-commit ashr(or(neg(x),x),bw-1) --> sext(icmp_ne(x,0)) tests from D105764

Added 'thwart complexity-based canonicalization' hacks and the lshr(or(neg(x),x),bw-1) --> zext(icmp_ne(x,0)) variants suggested by Sanjay.
The file was addedllvm/test/Transforms/InstCombine/sub-lshr-or-to-icmp-select.ll
The file was modifiedllvm/test/Transforms/InstCombine/sub-ashr-or-to-icmp-select.ll
Commit 45ffe6341d9642487785b0d0028166e6fbdbe5d7 by thakis
[clang/objc] Optimize getters for non-atomic, copied properties

Properties that were declared `@property(copy, nonatomic) id foo` make an
unnecessary call to objc_get_property().  This call can be replaced with a
direct access to the backing variable identical to how a `@property(nonatomic)
id foo` would do it.

This reduces codegen by 4 bytes (x86_64/arm64) and removes a cross linkage unit
function call per property declared as copy/nonatomic.

Differential Revision: https://reviews.llvm.org/D105311
The file was modifiedclang/test/CodeGenObjC/arc-blocks.m
The file was modifiedclang/lib/CodeGen/CGObjC.cpp
Commit b2f6cf14798ac738bc2c9b35bd83171e0771b7a3 by llvm-dev
[InstCombine] Fold lshr/ashr(or(neg(x),x),bw-1) --> zext/sext(icmp_ne(x,0)) (PR50816)

Handle the missing fold reported in PR50816, which is a variant of the existing ashr(sub_nsw(X,Y),bw-1) --> sext(icmp_sgt(X,Y)) fold.

We also handle the lshr(or(neg(x),x),bw-1) --> zext(icmp_ne(x,0)) equivalent - https://alive2.llvm.org/ce/z/SnZmSj

We still allow multi uses of the neg(x) - as this is likely to let us further simplify other uses of the neg - but not multi uses of the or() which would increase instruction count.

Differential Revision: https://reviews.llvm.org/D105764
The file was modifiedllvm/test/Transforms/InstCombine/sub-ashr-or-to-icmp-select.ll
The file was modifiedllvm/test/Transforms/InstCombine/sub-lshr-or-to-icmp-select.ll
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineShifts.cpp
Commit e9533b84920798cf9b35d26586a61bad0a1f9825 by alexfh
[NFC] Add paranthesis around logical expression to silence -Wlogical-op-parentheses warning.

Reviewed By: alexfh

Differential Revision: https://reviews.llvm.org/D105890
The file was modifiedclang/lib/Sema/SemaDeclAttr.cpp
Commit db635a28e65fa168536a100542d250f0b13c7039 by hansang.bae
[OpenMP] Minor improvement in task allocation

This patch includes a few changes to improve task allocation
performance slightly. These changes are enough to restore performance
drop observed after introducing hidden helper.

Differential Revision: https://reviews.llvm.org/D105715
The file was modifiedopenmp/runtime/src/kmp_tasking.cpp
Commit 2a9366c0e53593b2be2b91b4a37019ca8cae4557 by Louis Dionne
[libc++] Generate ABI list for macOS arm64
The file was addedlibcxx/lib/abi/arm64-apple-darwin.libcxxabi.v1.stable.exceptions.no_new_in_libcxx.abilist
Commit c5ad8bb8d41018ba58490873e95cc841d9276702 by Louis Dionne
[libc++] Target x86_64 only for the backdeployment jobs

Differential Revision: https://reviews.llvm.org/D105846
The file was modifiedlibcxx/utils/ci/buildkite-pipeline.yml
Commit 0da95a5cf2691c8e01ae02f108487c397ab7e0ce by Louis Dionne
[libc++] Workaround non-constexpr std::exchange pre C++20

std::exchange is only constexpr in C++20 and later. We were using it
in a constructor marked unconditionally constexpr, which caused issues
when building with -std=c++17.

The weird part is that the issue only showed up when building on the
arm64 macs, but that must be caused by the specific version of Clang
used on those. Since the code is clearly wrong and the fix is obvious,
I'm not going to investigate this further.
The file was modifiedlibcxx/test/std/utilities/optional/optional.object/optional.object.ctor/explicit_optional_U.pass.cpp
Commit 6a3904f16e8e2095082f71e862a33266e10fa871 by Matthew.Arsenault
Mips: Mark special case calling convention handling as custom

The number of registers used for passing f64 in some cases is context
dependent, and thus getNumRegistersForCallingConv is sometimes
inaccurate. For f64, it reports 1 but is sometimes split into 2 32-bit
registers.

For GlobalISel, the generic argument assignment code expects
getNumRegistersForCallingConv to return an accurate answer. Switch to
marking these arguments as custom so we can deal with this case as a
custom assignment rather.

This temporarily breaks a few globalisel tests which are fixed by a
future change to use more of the generic infrastructure.
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/irtranslator/float_args.ll
The file was modifiedllvm/lib/Target/Mips/MipsISelLowering.cpp
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/float_args.ll
Commit 121541fdcd5c9760ff242451d2b682c45a2a54df by Matthew.Arsenault
Mips/GlobalISel: Use more standard call lowering infrastructure

This also fixes some missing implicit uses on call instructions, adds
missing G_ASSERT_SEXT/ZEXT annotations, and some missing outgoing
sext/zexts. This also fixes not respecting tablegen requested type
promotions.

This starts treating f64 passed in i32 GPRs as a type of custom
assignment, which restores some previously XFAILed tests. This is due
to getNumRegistersForCallingConv returns a static value, but in this
case it is context dependent on other arguments.

Most of the ugliness is reproducing a hack CC_MipsO32 uses in
SelectionDAG. CC_MipsO32 depends on a bunch of vectors populated from
the original IR argument types in MipsCCState. The way this ends up
working in GlobalISel is it only ends up inspecting the most recently
added vector element. I'm pretty sure there are cleaner ways to do
this, but this seemed easier than fixing up the current DAG
handling. This is another case where it would be easier of the
CCAssignFns were passed the original type instead of only the
pre-legalized ones.

There's still a lot of junk here that shouldn't be necessary. This
also likely breaks big endian handling, but it wasn't complete/tested
anyway since the IRTranslator gives up on big endian targets.
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/CallLowering.h
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/irtranslator/float_args.ll
The file was modifiedllvm/lib/Target/Mips/MipsCCState.cpp
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/irtranslator/extend_args.ll
The file was modifiedllvm/lib/Target/Mips/MipsCallLowering.cpp
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/llvm-ir/float_args.ll
The file was modifiedllvm/lib/Target/Mips/MipsCallLowering.h
The file was modifiedllvm/lib/Target/ARM/ARMCallLowering.cpp
The file was modifiedllvm/lib/Target/Mips/MipsCCState.h
Commit 77a608d9de472766fcab51412100764e534ceaf9 by Matthew.Arsenault
GlobalISel: Remove getIntrinsicID utility function

This is redundant with a method directly on MachineInstr
The file was modifiedllvm/lib/CodeGen/GlobalISel/Utils.cpp
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/Utils.h
Commit 222fde1eec341a47f571a8afdf90e83c3a830c5b by Matthew.Arsenault
GlobalISel: Use extension instead of merge with undef in common case

This fixes not respecting signext/zeroext in these cases. In the
anyext case, this avoids a larger merge with undef and should be a
better canonical form.

This should also handle this if a merge is needed, but I'm not aware
of a case where that can happen. In a future change this will also
allow AMDGPU to drop some custom code without introducing regressions.
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll
The file was modifiedllvm/lib/CodeGen/GlobalISel/CallLowering.cpp
Commit fb44c3223e0c36e969762dd182b4992061b455d3 by Matthew.Arsenault
AMDGPU: Promote signext/zeroext i16 shader returns

This makes them consistent with all the other return convention
handling. If we don't do this, we lose the sext/zext flag if treated
as a full assignment, which complicates a future GlobalISel patch.
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUCallingConv.td
Commit 1e03c37b97b6176a60404d84665c40321f4e33a4 by John.Ericson
Prepare Compiler-RT for GnuInstallDirs, matching libcxx, document all

This is a second attempt at D101497, which landed as
9a9bc76c0eb72f0f2732c729a460abbd5239c2e3 but had to be reverted in
8cf7ddbdd4e5af966a369e170c73250f2e3920e7.

This issue was that in the case that `COMPILER_RT_INSTALL_PATH` is
empty, expressions like "${COMPILER_RT_INSTALL_PATH}/bin" evaluated to
"/bin" not "bin" as intended and as was originally.

One solution is to make `COMPILER_RT_INSTALL_PATH` always non-empty,
defaulting it to `CMAKE_INSTALL_PREFIX`. D99636 adopted that approach.
But, I think it is more ergonomic to allow those project-specific paths
to be relative the global ones. Also, making install paths absolute by
default inhibits the proper behavior of functions like
`GNUInstallDirs_get_absolute_install_dir` which make relative install
paths absolute in a more complicated way.

Given all this, I will define a function like the one asked for in
https://gitlab.kitware.com/cmake/cmake/-/issues/19568 (and needed for a
similar use-case).

---

Original message:

Instead of using `COMPILER_RT_INSTALL_PATH` through the CMake for
complier-rt, just use it to define variables for the subdirs which
themselves are used.

This preserves compatibility, but later on we might consider getting rid
of `COMPILER_RT_INSTALL_PATH` and just changing the defaults for the
subdir variables directly.

---

There was a seaming bug where the (non-Apple) per-target libdir was
`${target}` not `lib/${target}`. I suspect that has to do with the docs
on `COMPILER_RT_INSTALL_PATH` saying was the library dir when that's no
longer true, so I just went ahead and fixed it, allowing me to define
fewer and more sensible variables.

That last part should be the only behavior changes; everything else
should be a pure refactoring.

---

I added some documentation of these variables too. In particular, I
wanted to highlight the gotcha where `-DSomeCachePath=...` without the
`:PATH` will lead CMake to make the path absolute. See [1] for
discussion of the problem, and [2] for the brief official documentation
they added as a result.

[1]: https://cmake.org/pipermail/cmake/2015-March/060204.html

[2]: https://cmake.org/cmake/help/latest/manual/cmake.1.html#options

In 38b2dec37ee735d5409148e71ecba278caf0f969 the problem was somewhat
misidentified and so `:STRING` was used, but `:PATH` is better as it
sets the correct type from the get-go.

---

D99484 is the main thrust of the `GnuInstallDirs` work. Once this lands,
it should be feasible to follow both of these up with a simple patch for
compiler-rt analogous to the one for libcxx.

Reviewed By: phosek, #libc_abi, #libunwind

Differential Revision: https://reviews.llvm.org/D105765
The file was modifiedlibcxx/CMakeLists.txt
The file was modifiedlibcxx/docs/BuildingLibcxx.rst
The file was modifiedclang/runtime/CMakeLists.txt
The file was modifiedcompiler-rt/include/CMakeLists.txt
The file was modifiedlibunwind/CMakeLists.txt
The file was modifiedcompiler-rt/cmake/base-config-ix.cmake
The file was modifiedcompiler-rt/cmake/Modules/CompilerRTUtils.cmake
The file was modifiedlibunwind/docs/BuildingLibunwind.rst
The file was modifiedcompiler-rt/lib/dfsan/CMakeLists.txt
The file was modifiedcompiler-rt/cmake/Modules/AddCompilerRT.cmake
The file was addedcompiler-rt/docs/BuildingCompilerRT.rst
The file was modifiedlibcxxabi/CMakeLists.txt
The file was modifiedcompiler-rt/cmake/Modules/CompilerRTDarwinUtils.cmake
Commit 32627f4ab4b717dc1932141db99605b723037bf8 by tpopp
[mlir] Handle unused variable when assertions are disabled.
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/ComprehensiveBufferize.cpp
Commit 03d8fed34951bc6e92b36615ec3afe6f36d10de6 by anton.zabaznov
[OpenCL] Add verbosity when checking support of read_write images

Parenthesis were fixed incorrectly by D105890

Reviewed By: Anastasia

Differential Revision: https://reviews.llvm.org/D105892
The file was modifiedclang/lib/Sema/SemaDeclAttr.cpp
Commit 10e0cdfc6526578c8892d895c0448e77cb9ba876 by wei.huang
[PowerPC][NFC] Power ISA features for Semachecking

[NFC] This patch adds features for pwr7, pwr8, and pwr9 that can be
used for semachecking builtin functions that are only valid for certain
versions of ppc.

Reviewed By: nemanjai, #powerpc
Authored By: Quinn Pham <Quinn.Pham@ibm.com>

Differential revision: https://reviews.llvm.org/D105501
The file was modifiedclang/lib/Basic/Targets/PPC.h
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrInfo.td
The file was modifiedclang/lib/Sema/SemaChecking.cpp
The file was modifiedllvm/lib/Target/PowerPC/PPCSubtarget.h
The file was modifiedclang/lib/Basic/Targets/PPC.cpp
The file was modifiedclang/include/clang/Basic/DiagnosticSemaKinds.td
The file was modifiedllvm/lib/Target/PowerPC/PPC.td
The file was modifiedllvm/lib/Target/PowerPC/PPCSubtarget.cpp
Commit 1bfec34ac3e71ae3e65d5132fb475b6f8cc0bafe by llvm-dev
[InstCombine] Regenerate select-gep.ll tests
The file was modifiedllvm/test/Transforms/InstCombine/select-gep.ll
Commit 4975837f1480621d9428a4be468831d07b2201de by llvm-dev
[InstCombine] Add basic (select C, (gep Ptr, Idx), Ptr) tests from PR50183
The file was modifiedllvm/test/Transforms/InstCombine/select-gep.ll
Commit f1aca5ac96ebd0beadfa68a474c5947d3bc8c109 by albionapc
[PowerPC] Fix L[D|W]ARX Implementation

LDARX and LWARX sometimes gets optimized out by the compiler
when it is critical to the correctness of the code. This inline asm generation
ensures that it preserved.

Differential Revision: https://reviews.llvm.org/D105754
The file was modifiedclang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond-64bit-only.c
The file was modifiedllvm/lib/Target/PowerPC/PPCInstr64Bit.td
The file was modifiedllvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond.ll
The file was modifiedclang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c
The file was modifiedllvm/include/llvm/IR/IntrinsicsPowerPC.td
The file was modifiedllvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond-64bit-only.ll
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrInfo.td
The file was modifiedclang/lib/CodeGen/CGBuiltin.cpp
Commit 7039dfc6dd157a26de2f5a6fd15662510a1dd119 by ajcbik
[mlir][memref] adjust integration tests to new lowering passes

these tests run under the emulator and thus were overlooked

Reviewed By: ftynse

Differential Revision: https://reviews.llvm.org/D105855
The file was modifiedmlir/test/Integration/Dialect/Vector/CPU/AMX/test-mulf.mlir
The file was modifiedmlir/test/Integration/Dialect/Vector/CPU/AMX/test-muli.mlir
The file was modifiedmlir/test/Integration/Dialect/Vector/CPU/X86Vector/test-sparse-dot-product.mlir
The file was modifiedmlir/test/Integration/Dialect/Vector/CPU/AMX/test-tilezero-block.mlir
The file was modifiedmlir/test/Integration/Dialect/Vector/CPU/AMX/test-tilezero.mlir
The file was modifiedmlir/test/Integration/Dialect/Vector/CPU/AMX/test-muli-ext.mlir
Commit a006af5d6ec6280034ae4249f6d2266d726ccef4 by gchatelet
[llvm] Add enum iteration to Sequence

This patch allows iterating typed enum via the ADT/Sequence utility.

Differential Revision: https://reviews.llvm.org/D103900
The file was modifiedllvm/unittests/IR/ConstantRangeTest.cpp
The file was modifiedllvm/tools/llvm-exegesis/lib/X86/Target.cpp
The file was modifiedllvm/unittests/CodeGen/ScalableVectorMVTsTest.cpp
The file was modifiedllvm/include/llvm/ADT/Sequence.h
The file was modifiedmlir/lib/Dialect/Linalg/IR/LinalgOps.cpp
The file was modifiedllvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
The file was modifiedllvm/unittests/ADT/SequenceTest.cpp
The file was modifiedllvm/include/llvm/Support/MachineValueType.h
The file was modifiedllvm/tools/llvm-reduce/deltas/ReduceAttributes.cpp
Commit 3d89fb4d13bc3af1c3643a310b90fce51a649119 by i
[RISCV] Support machine constraint "S"

Similar to D46745, "S" represents an absolute symbolic operand, which
can be used to specify the access models, e.g.

  extern int var;
  void *addr_via_asm() {
    void *ret;
    asm("lui %0, %%hi(%1)\naddi %0,%0,%%lo(%1)" : "=r"(ret) : "S"(&var));
    return ret;
  }

'S' is documented in trunk GCC: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101275

Reviewed By: luismarques

Differential Revision: https://reviews.llvm.org/D105254
The file was addedllvm/test/CodeGen/RISCV/inline-asm-S-constraint.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.cpp
The file was modifiedclang/test/CodeGen/RISCV/riscv-inline-asm.c
The file was modifiedclang/lib/Basic/Targets/RISCV.cpp
Commit 68ae8bacfce3b9bd73fefb0d28efd461e1588586 by nicolas.vasilache
[mlir][Linalg] Properly specify Linalg attribute.

This fixes undefined reference introduced by https://reviews.llvm.org/D105859

Differential Revision: https://reviews.llvm.org/D105897
The file was modifiedmlir/lib/Dialect/Linalg/IR/LinalgTypes.cpp
The file was modifiedmlir/include/mlir/Dialect/Linalg/IR/LinalgBase.td
Commit 1893b630fec06947b4f59e43c00db4d787f39262 by julian.lettner
Avoid triggering assert when program calls OSAtomicCompareAndSwapLong

A previous change brought the new, relaxed implementation of "on failure
memory ordering" for synchronization primitives in LLVM over to TSan
land [1].  It included the following assert:
```
// 31.7.2.18: "The failure argument shall not be memory_order_release
// nor memory_order_acq_rel". LLVM (2021-05) fallbacks to Monotonic
// (mo_relaxed) when those are used.
CHECK(IsLoadOrder(fmo));

static bool IsLoadOrder(morder mo) {
  return mo == mo_relaxed || mo == mo_consume
      || mo == mo_acquire || mo == mo_seq_cst;
}
```

A previous workaround for a false positive when using an old Darwin
synchronization API assumed this failure mode to be unused and passed a
dummy value [2].  We update this value to `mo_relaxed` which is also the
value used by the actual implementation to avoid triggering the assert.

[1] https://reviews.llvm.org/D99434
[2] https://reviews.llvm.org/D21733

rdar://78122243

Differential Revision: https://reviews.llvm.org/D105844
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_interceptors_mac.cpp
Commit b25aca503d296eeeb2a174d8fb97637de74b8653 by aeubanks
[OpaquePtr] Use AllocaInst::getAllocatedType()
The file was modifiedllvm/lib/Target/NVPTX/NVPTXLowerAlloca.cpp
Commit 693bc04bf615b63b0070c7d1ad15257a7ce31a20 by aeubanks
[OpaquePtr] Use GlobalValue::getValueType() more
The file was modifiedllvm/lib/Transforms/IPO/MergeFunctions.cpp
The file was modifiedllvm/lib/Transforms/Coroutines/Coroutines.cpp
The file was modifiedllvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
The file was modifiedllvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
Commit 113a80797731b1d7cb20d8b42238908efc9e4f48 by aeubanks
[OpaquePtr] Get load/store type without PointerType::getElementType()
The file was modifiedllvm/lib/Transforms/Scalar/LoopLoadElimination.cpp
Commit ab5693aa4ac45fed0fa4c9106f0eef6d409b6c3e by aeubanks
[OpaquePtr] Use byval type more
The file was modifiedllvm/lib/Transforms/Coroutines/CoroFrame.cpp
The file was modifiedllvm/lib/Transforms/Scalar/MemCpyOptimizer.cpp
The file was modifiedllvm/lib/Transforms/IPO/ArgumentPromotion.cpp
Commit 2c47b8847ec75c25187e9819abd85cc9e908d742 by gchatelet
Revert "[llvm] Add enum iteration to Sequence"

This reverts commit a006af5d6ec6280034ae4249f6d2266d726ccef4.
The file was modifiedllvm/include/llvm/ADT/Sequence.h
The file was modifiedmlir/lib/Dialect/Linalg/IR/LinalgOps.cpp
The file was modifiedllvm/unittests/ADT/SequenceTest.cpp
The file was modifiedllvm/tools/llvm-reduce/deltas/ReduceAttributes.cpp
The file was modifiedllvm/unittests/CodeGen/ScalableVectorMVTsTest.cpp
The file was modifiedllvm/tools/llvm-exegesis/lib/X86/Target.cpp
The file was modifiedllvm/unittests/IR/ConstantRangeTest.cpp
The file was modifiedllvm/include/llvm/Support/MachineValueType.h
The file was modifiedllvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
Commit 46e89708170c40e8cf0305b6de048ca879f43aab by craig.topper
[RISCV] Prevent use of t0(aka x5) as rs1 for jalr instructions.

Some microarchitectures treat rs1=x1/x5 on jalr as a hint to pop
the return-address stack. We should avoid using x5 on jalr
instructions since we aren't using x5 as an alternate link register.

Differential Revision: https://reviews.llvm.org/D105875
The file was modifiedllvm/test/CodeGen/RISCV/tail-calls.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVRegisterInfo.td
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfo.td
The file was modifiedllvm/test/CodeGen/RISCV/calls.ll
Commit ae4cea38f18e32d4a106871d751af380032e16fe by thomasraoux
[mlir] Add support for tensor.extract to comprehensive bufferization

Differential Revision: https://reviews.llvm.org/D105870
The file was modifiedmlir/test/Dialect/Linalg/comprehensive-module-bufferize.mlir
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/ComprehensiveBufferize.cpp
Commit 489742991f7dc4c621264d223e8973ff876e9080 by aeubanks
[NFC] Inline variable to prevent unused variable warning
The file was modifiedllvm/lib/Transforms/Scalar/LoopLoadElimination.cpp
Commit e4b43973fbd41aee3b8197cf250e9fb9ac40f986 by listmail
[ScalarEvolution] Fix overflow when computing max trip counts

This is split from D105216 to reduce patch complexity.  Original code by Eli with very minor modification by me.

The primary point of this patch is to add the getUDivCeilSCEV routine.  I included the two callers with constant arguments as we know those must constant fold even without any of the fancy inference logic.
The file was modifiedllvm/lib/Analysis/ScalarEvolution.cpp
The file was modifiedllvm/include/llvm/Analysis/ScalarEvolution.h
Commit 7a20670d168af31ef77209f43ca0622800ce513a by Saleem Abdulrasool
AST: correct name decoration for swift async functions on Windows

The name decoration scheme on Windows does not have a vendor namespace,
and the decoration scheme is not shared ownership - it is controlled by
Microsoft.  `T` is a reserved identifier for an unknown calling
convention.  The `W` identifier has been discussed with Microsoft
offline and is reserved as `Swift_3` as the identifier for the swift
async calling convention.  Adjust the name decoration accordingly.
The file was modifiedclang/lib/AST/MicrosoftMangle.cpp
Commit 14f77576c9c4f502267a92992abe3bdcbeb96b2c by marcos.horro
[llvm-mca] [NFC] Formatting code

Applied clang-format to all files. Discarded BottleneckAnalysis.h
80-column width violation since it contains an example of report.
Caught some typos and minor style details.

Reviewed By: andreadb

Differential Revision: https://reviews.llvm.org/D105900
The file was modifiedllvm/tools/llvm-mca/Views/SummaryView.h
The file was modifiedllvm/tools/llvm-mca/Views/SummaryView.cpp
The file was modifiedllvm/tools/llvm-mca/PipelinePrinter.cpp
The file was modifiedllvm/tools/llvm-mca/Views/InstructionView.h
The file was modifiedllvm/tools/llvm-mca/llvm-mca.cpp
The file was modifiedllvm/tools/llvm-mca/Views/InstructionView.cpp
The file was modifiedllvm/tools/llvm-mca/Views/BottleneckAnalysis.cpp
The file was modifiedllvm/tools/llvm-mca/Views/BottleneckAnalysis.h
The file was modifiedllvm/tools/llvm-mca/Views/RetireControlUnitStatistics.cpp
The file was modifiedllvm/tools/llvm-mca/Views/TimelineView.h
The file was modifiedllvm/tools/llvm-mca/Views/RegisterFileStatistics.cpp
The file was modifiedllvm/tools/llvm-mca/Views/DispatchStatistics.cpp
The file was modifiedllvm/tools/llvm-mca/Views/View.h
Commit 03282f2fe14e9dd61aaeeda3785f56c7ccb4f3c9 by mizvekov
[clang] C++98 implicit moves are back with a vengeance

After taking C++98 implicit moves out in D104500,
we put it back in, but now in a new form which preserves
compatibility with pure C++98 programs, while at the same time
giving almost all the goodies from P1825.

* We use the exact same rules as C++20 with regards to which
  id-expressions are move eligible. The previous
  incarnation would only benefit from the proper subset which is
  copy ellidable. This means we can implicit move, in addition:
  * Parameters.
  * RValue references.
  * Exception variables.
  * Variables with higher-than-natural required alignment.
  * Objects with different type from the function return type.
* We preserve the two-overload resolution, with one small tweak to the
  first one: If we either pick a (possibly converting) constructor which
  does not take an rvalue reference, or a user conversion operator which
  is not ref-qualified, we abort into the second overload resolution.

This gives C++98 almost all the implicit move patterns which we had created test
cases for, while at the same time preserving the meaning of these
three patterns, which are found in pure C++98 programs:
* Classes with both const and non-const copy constructors, but no move
  constructors, continue to have their non-const copy constructor
  selected.
* We continue to reject as ambiguous the following pattern:
```
struct A { A(B &); };
struct B { operator A(); };
A foo(B x) { return x; }
```
* We continue to pick the copy constructor in the following pattern:
```
class AutoPtrRef { };
struct AutoPtr {
  AutoPtr(AutoPtr &);
  AutoPtr();

  AutoPtr(AutoPtrRef);
  operator AutoPtrRef();
};
AutoPtr test_auto_ptr() {
  AutoPtr p;
  return p;
}
```

Signed-off-by: Matheus Izvekov <mizvekov@gmail.com>

Reviewed By: Quuxplusone

Differential Revision: https://reviews.llvm.org/D105756
The file was modifiedclang/test/SemaCXX/conversion-function.cpp
The file was modifiedclang/test/SemaObjCXX/block-capture.mm
The file was modifiedclang/test/CXX/class/class.init/class.copy.elision/p3.cpp
The file was modifiedclang/lib/Sema/SemaStmt.cpp
Commit 405eefe46497bde580c28ce2d2b79f0e96f2a1d0 by jonathan.l.peyton
[OpenMP][NFC] Change comment style to eliminate warnings from GCC

Standalone build for OpenMP runtime using GCC is giving -Wcomment
warnings where a backslash newline is encountered in the // style
comment. This switches the // style for /* style to silence the
warnings.
The file was modifiedopenmp/runtime/src/kmp_os.h
Commit b5f4ac4c11b041ab9dfed42a7133d1eca6536aaa by amy.kwan1
[PowerPC] Add FI alignment check if the addressing mode is DS/DQ-Form, emit X-Form if necessary.

This patch adds a function that checks whether or not the frame index
is aligned when the computed addressing mode is an aligned D-Form (DS, or DQ-Form).
If the frame index appears to be unaligned, within these two modes, reset
the mode to X-Form in order to fall back to selection X-Form loads.

A test case is added to ensure that the test emits X-Form loads and not DQ-Form
loads since the frame index is not aligned within the test case.

Differential Revision: https://reviews.llvm.org/D105661
The file was addedllvm/test/CodeGen/PowerPC/unaligned-dqform-ld.ll
The file was modifiedllvm/lib/Target/PowerPC/PPCISelLowering.cpp
Commit 1e670dc7d78427156c252317b3571576d465043f by craig.topper
[RISCV] Use DIVUW/REMUW/DIVW instructions for i8/i16/i32 udiv/urem/sdiv when LHS is constant.

We don't really have optimizations for division with a constant
LHS. If we don't use a W instruction we end up needing to sign
or zero extend the RHS to use the 64-bit instruction.

I had to sign_extend i32 constants on the LHS instead of using
any_extend which becomes zero_extend. If we don't do this, constants
that were originally negative become harder to materialize. I think
this problem exists for more of our W instruction cases. For example
(i32 (shl -1, X)), but we don't have lit tests. I'll work on that
as a follow up.

I also left a FIXME for enabling W instruction for RHS constants
under -Oz.

Reviewed By: luismarques

Differential Revision: https://reviews.llvm.org/D105769
The file was modifiedllvm/test/CodeGen/RISCV/rem.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.cpp
The file was modifiedllvm/test/CodeGen/RISCV/div.ll
Commit 04942a7ffc716d2f782402089201cadfbbbb2a04 by Louis Dionne
[libc++] NFC: Add comment for running macOS CI setup script remotely
The file was modifiedlibcxx/utils/ci/macos-ci-setup
Commit 424f14f0d2e98b83a41bdc7408f15d28aaa4cbd0 by jonathan.l.peyton
[OpenMP] Fix one sign-compare warning from GCC
The file was modifiedopenmp/runtime/src/kmp_runtime.cpp
Commit 303ddb60a2d28fb7603266d8977f69ac77b194dd by tstellar
Fix utils/update_cc_test_checks/check-globals.test on stand-alone builds

We want to use LLVM_EXTERNAL_LIT if defined for the %lit substitution.

Reviewed By: jdenny

Differential Revision: https://reviews.llvm.org/D105873
The file was modifiedclang/test/lit.site.cfg.py.in
The file was modifiedclang/test/utils/update_cc_test_checks/lit.local.cfg
The file was modifiedclang/test/CMakeLists.txt
Commit 2a399e60b6ea74aca47881b48414a5198a868cc3 by Louis Dionne
[libc++] Add a CI job for macOS on arm64 hardware 🥳

Differential Revision: https://reviews.llvm.org/D105848
The file was modifiedlibcxx/utils/ci/buildkite-pipeline.yml
The file was modifiedlibcxxabi/test/thread_local_destruction_order.pass.cpp
Commit 2bc07083a258fdbbafc9c0381e936f441f93af70 by Vitaly Buka
[sanitizer] Fix VSNPrintf %V on Windows
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_printf.cpp
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_common.h
The file was modifiedcompiler-rt/lib/sanitizer_common/tests/sanitizer_printf_test.cpp
Commit f26deb4e6ba7e00c57b4be888c4d20c95a881154 by vsavchenko
[analyzer][solver][NFC] Introduce ConstraintAssignor

The new component is a symmetric response to SymbolicRangeInferrer.
While the latter is the unified component, which answers all the
questions what does the solver knows about a particular symbolic
expression, assignor associates new constraints (aka "assumes")
with symbolic expressions and can imply additional knowledge that
the solver can extract and use later on.

- Why do we need it and why is SymbolicRangeInferrer not enough?

As it is noted before, the inferrer only helps us to get the most
precise range information based on the existing knowledge and on the
mathematical foundations of different operations that symbolic
expressions actually represent.  It doesn't introduce new constraints.

The assignor, on the other hand, can impose constraints on other
symbols using the same domain knowledge.

- But for some expressions, SymbolicRangeInferrer looks into constraints
  for similar expressions, why can't we do that for all the cases?

That's correct!  But in order to do something like this, we should
have a finite number of possible "similar expressions".

Let's say we are asked about `$a - $b` and we know something about
`$b - $a`.  The inferrer can invert this expression and check
constraints for `$b - $a`.  This is simple!
But let's say we are asked about `$a` and we know that `$a * $b != 0`.
In this situation, we can imply that `$a != 0`, but the inferrer shouldn't
try every possible symbolic expression `X` to check if `$a * X` or
`X * $a` is constrained to non-zero.

With the assignor mechanism, we can catch this implication right at
the moment we associate `$a * $b` with non-zero range, and set similar
constraints for `$a` and `$b` as well.

Differential Revision: https://reviews.llvm.org/D105692
The file was modifiedclang/lib/StaticAnalyzer/Core/RangeConstraintManager.cpp
Commit 60bd8cbc0c84a41146b1ad6c832fa75f48cd2568 by vsavchenko
[analyzer][solver][NFC] Refactor how we detect (dis)equalities

This patch simplifies the way we deal with (dis)equalities.
Due to the symmetry between constraint handler and range inferrer,
we can have very similar implementations of logic handling
questions about (dis)equality and assumptions involving (dis)equality.

It also helps us to remove one more visitor, and removes uncertainty
that we got all the right places to put `trackNE` and `trackEQ`.

Differential Revision: https://reviews.llvm.org/D105693
The file was modifiedclang/test/Analysis/equality_tracking.c
The file was modifiedclang/lib/StaticAnalyzer/Core/RangeConstraintManager.cpp
Commit ce25eb0b71bfcd104afd300c2eb2fb5982f827e8 by Vitaly Buka
[NFC][sanitizer] Remove trailing whitespace
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_common.h
Commit 6245252d4c8c7c9b1be5b9e6a876be9776c000e4 by listmail
[test] Add a SCEV backedge computation test with an explicit zero stride
The file was modifiedllvm/test/Analysis/ScalarEvolution/trip-count-unknown-stride.ll
Commit 01d3a3dcabaf862581b1d1aee604fcee6a18b240 by tra
[CUDA] Only allow NVIDIA offload-arch during CUDA compilation.

Otherwise, if someone specifies a valid AMD arch, we may end up triggering an
assertion on unexpected arch later on.

Differential Revision: https://reviews.llvm.org/D105295
The file was modifiedclang/test/Driver/cuda-bad-arch.cu
The file was modifiedclang/lib/Driver/Driver.cpp
Commit 43c7ca8e4963beb2e5a57639f20b8f43608296d7 by jonathan_roelofs
[AArch64][GlobalISel] Legalize store <2 x i16>

Differential revision: https://reviews.llvm.org/D105912
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir
Commit eba638dbbb77ca2a446fd76b4f52ad85640da4f9 by jonathan_roelofs
[AArch64][GlobalISel] Legalize load <2 x i16>

Differential revision: https://reviews.llvm.org/D105913
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
Commit e4585d3f4e1f076ff12db65259924492f5912b19 by wei.huang
Revert "[PowerPC][NFC] Power ISA features for Semachecking"

This reverts commit 10e0cdfc6526578c8892d895c0448e77cb9ba876.
The file was modifiedclang/lib/Basic/Targets/PPC.cpp
The file was modifiedclang/lib/Basic/Targets/PPC.h
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrInfo.td
The file was modifiedllvm/lib/Target/PowerPC/PPCSubtarget.cpp
The file was modifiedllvm/lib/Target/PowerPC/PPCSubtarget.h
The file was modifiedclang/lib/Sema/SemaChecking.cpp
The file was modifiedclang/include/clang/Basic/DiagnosticSemaKinds.td
The file was modifiedllvm/lib/Target/PowerPC/PPC.td
Commit 781929b4236bc34681fb0783cf7b6021109fe28b by wei.huang
[PowerPC][NFC] Power ISA features for Semachecking

[NFC] This patch adds features for pwr7, pwr8, and pwr9 that can be
used for semachecking builtin functions that are only valid for certain
versions of ppc.

Reviewed By: nemanjai, #powerpc
Authored By: Quinn Pham <Quinn.Pham@ibm.com>

Differential revision: https://reviews.llvm.org/D105501
The file was modifiedclang/lib/Basic/Targets/PPC.h
The file was modifiedclang/lib/Sema/SemaChecking.cpp
The file was modifiedllvm/lib/Target/PowerPC/PPC.td
The file was modifiedllvm/lib/Target/PowerPC/PPCSubtarget.cpp
The file was addedclang/test/Driver/ppc-isa-features.cpp
The file was modifiedclang/lib/Basic/Targets/PPC.cpp
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrInfo.td
The file was modifiedllvm/lib/Target/PowerPC/PPCSubtarget.h
The file was modifiedclang/include/clang/Basic/DiagnosticSemaKinds.td
Commit 308d38128333af65455e8343a620b40a099e896a by tlively
[WebAssembly] Generate checks for simd-load-store-alignment.ll

This will make it easier to update these tests as we add support for generating
more SIMD loads and stores with custom alignments.

Differential Revision: https://reviews.llvm.org/D105862
The file was modifiedllvm/test/CodeGen/WebAssembly/simd-load-store-alignment.ll
Commit e56b2e57067652710418973e11bb9b118f37b177 by nikita.ppv
[InstCombine] Precommit tests for D105088 (NFC)

Add tests for D105088, as well as an option to disable the
(generally) unsound inttoptr of ptrtoint optimization.

Differential Revision: https://reviews.llvm.org/D105771
The file was modifiedllvm/lib/IR/Instructions.cpp
The file was addedllvm/test/Transforms/InstCombine/ptr-int-ptr-icmp.ll
Commit 3e5cff19fdae2515f87c08dc8b0e483751165153 by jonathan_roelofs
[Tests] Fix test broken by: 43c7ca8e4963 [AArch64][GlobalISel] Legalize store <2 x i16>
The file was modifiedllvm/test/CodeGen/AArch64/arm64-rev.ll
Commit 087310c71e5c1c70818ac62acd781860d59a6ce7 by listmail
[SCEV] Strengthen inference of RHS > Start in howManyLessThans

Split off from D105216 to simplify review.  Rewritten with a lambda to be easier to follow.  Comments clarified.

Sorry for no test case, this is tricky to exercise with the current structure of the code.  It's about to be hit more frequently in a follow up patch, and the change itself is simple.
The file was modifiedllvm/lib/Analysis/ScalarEvolution.cpp
Commit 25629bb45f0a4b8c8e99dbde4f4a7e3d980b9fd7 by tra
Fix cuda-bad-arch.cu test.

Tests for correctness of HIP architecture need `- xhip`
The file was modifiedclang/test/Driver/cuda-flush-denormals-to-zero.cu
The file was modifiedclang/test/Driver/cuda-bad-arch.cu
The file was modifiedclang/test/Driver/cuda-arch-translation.cu
Commit 5ca9cf0e6b15647a4f6959c1fc1c23b9f6cb0cba by listmail
[tests] Precommit a test case from D105216
The file was modifiedllvm/test/Analysis/ScalarEvolution/trip-count-unknown-stride.ll
Commit 3ea8860afb302f628703a57226e5466091b2c418 by thakis
[gn build] (manually) port 303ddb60a2d2
The file was modifiedllvm/utils/gn/secondary/clang/test/BUILD.gn
Commit 5d1ba534043707a7b41542e9d1e514483f88503a by efriedma
[LoopReroll] Add an extra defensive check to avoid SCEV assertion.

Make sure getMinusSCEV() didn't return a pointer.  The following check
would never succeed if it was a pointer, anyway, but calling
getMulExpr() on a pointer SCEV now asserts.
The file was modifiedllvm/test/Transforms/LoopReroll/basic.ll
The file was modifiedllvm/lib/Transforms/Scalar/LoopRerollPass.cpp
Commit b28c465e4902f579799bc94512197c04a5ad4a29 by efriedma
[NFC] Use CHECK-LABEL in trip-count-unknown-stride.ll
The file was modifiedllvm/test/Analysis/ScalarEvolution/trip-count-unknown-stride.ll
Commit 6296e109728d58805004739530b8f265c6a130b9 by thomasraoux
[mlir][Vector] Remove Vector TupleOp as it is unused

TupleOp is not used anymore after recent refactoring.

Differential Revision: https://reviews.llvm.org/D105924
The file was modifiedmlir/include/mlir/Dialect/Vector/VectorOps.td
The file was modifiedmlir/lib/Dialect/Vector/VectorOps.cpp
Commit fb9c5c3dce27b352534641dbb6e3cb8c05da7bc9 by abidh
[lld][AMDGPU] Handle R_AMDGPU_REL16 relocation.

This patch is a followup patch to https://reviews.llvm.org/D105760 which adds this relocation. This handles the relocation in lld.

The s_branch family of instruction does the following:
PC = PC + signext(simm * 4) + 4

so we we do the opposite on the target address before writing it in the instruction stream.

Reviewed By: MaskRay

Differential Revision: https://reviews.llvm.org/D105761
The file was addedlld/test/ELF/amdgpu-relocs2.s
The file was modifiedlld/ELF/Arch/AMDGPU.cpp
Commit 7efe3887858fe77da5c6687e3ac9ed9b00f9ed4e by arthur.j.odwyer
[libc++] [test] Add a missing `()` in TestEachIntegralType.
The file was modifiedlibcxx/test/support/atomic_helpers.h
Commit ba8dcaef0d79ae0174cdcea6d6f62015266c1d40 by Vitaly Buka
Revert "sanitizer_common: optimize memory drain"

Breaks https://lab.llvm.org/buildbot/#/builders/anitizer-windows

This reverts commit d89d3dfae17d7795dc1ef013db66272020de1959.
The file was modifiedcompiler-rt/lib/sanitizer_common/tests/sanitizer_allocator_test.cpp
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_allocator_local_cache.h
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_allocator_primary64.h
Commit d558bfaf8e1e8e7814053abc406cdaaed00cf784 by Vitaly Buka
[NFC][sanitizer] clang-format part of D105778
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_allocator_local_cache.h
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_allocator_primary64.h
The file was modifiedcompiler-rt/lib/sanitizer_common/tests/sanitizer_allocator_test.cpp
Commit 5105a77035d080a5f14668b136c8def52b182ce2 by Vedant Kumar
[docs/llvm-cov] Document -compilation-dir

Document the `-compilation-dir` option added in D100232.

Differential Revision: https://reviews.llvm.org/D105826
The file was modifiedllvm/docs/CommandGuide/llvm-cov.rst
Commit d12a7f142e2430f4983c668d910897db8cc2afc7 by hedingarcia
[libc] Add on float properties for precision floating point numbers in FloatProperties.h

Defined constant that express the number of bits for exponent in single and double precision. Added bit masks values and other properties for quad precision floating point numbers that specifically targets architectures defined in PlatfromDefs.h. The exponentWidth values were added to be used in LongDoubleBitsX86.h where the implementation to set the exponent component uses this and the bitWidth value. The need occurred because of the 80-bit quad precision implementation.

Reviewed By: aeubanks

Differential Revision: https://reviews.llvm.org/D105153
The file was modifiedlibc/utils/FPUtil/FloatProperties.h
Commit 9f1f666b30c03376d3816f7b2d18c93073517330 by Vitaly Buka
[NFC][sanitizer] Move MemoryMapper out of SizeClassAllocator64

Part of D105778
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_allocator_primary64.h
Commit 1c69005c2e11414669ac8ba094a9b059920936db by martin
[libcxx] [docs] Acknowledge that the library is known to work in some configs outside of what's tested in CI

Differential Revision: https://reviews.llvm.org/D105888
The file was modifiedlibcxx/docs/index.rst
Commit 4df591b5c960affd1612e330d0c9cd3076c18053 by listmail
[SCEV] Handle zero stride correctly in howManyLessThans

This is split from D105216, but the code is hoisted much earlier into the path where we can actually get a zero stride flowing through. Some fairly simple proofs handle the cases which show up in practice. The only test changes are the cases where we really do need a non-zero divider to produce the right result.

Differential Revision: https://reviews.llvm.org/D105921
The file was modifiedllvm/test/Analysis/ScalarEvolution/trip-count-unknown-stride.ll
The file was modifiedllvm/lib/Analysis/ScalarEvolution.cpp
Commit f990da59c5df840526baeb70bc5b5594fb5599ed by Vitaly Buka
[sanitizer] Few more NFC changes from D105778
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_allocator_primary64.h
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_allocator_local_cache.h
Commit a16071e409a55cfc83e59eb738fd6144207dd5d1 by caitlyncano
[libc] Don't pass -fpie/-ffreestanding on Windows

The current compile options function hardcodes the -fpie and
-ffreestanding flags, which don't exist on Windows. This patch sets the
compilation flags conditionally based on the OS specifics.

Reviewed By: sivachandra, aeubanks

Differential Revision: https://reviews.llvm.org/D105643
The file was modifiedlibc/cmake/modules/LLVMLibCObjectRules.cmake
Commit a5a337e55ed2e265358ac0a2ce6db1af2dd69e07 by hedingarcia
[libc] Capture floating point encoding and arrange it sequentially in memory

Redefined FPBits.h and LongDoubleBitsX86 so its implementation works for the Windows
and Linux platform while maintaining a packed memory alignment of the precision floating
point numbers. For its size in memory to be the same as the data type of the float point number.
This change was necessary because the previous attribute((packed)) specification in the struct was not working
for Windows like it was for Linux and consequently static_asserts in the FPBits.h file were failing.

Reviewed By: aeubanks, sivachandra

Differential Revision: https://reviews.llvm.org/D105561
The file was modifiedlibc/utils/FPUtil/NearestIntegerOperations.h
The file was modifiedlibc/test/src/math/LdExpTest.h
The file was modifiedlibc/utils/FPUtil/Hypot.h
The file was modifiedlibc/utils/FPUtil/LongDoubleBitsX86.h
The file was modifiedlibc/utils/FPUtil/NextAfterLongDoubleX86.h
The file was modifiedlibc/utils/FPUtil/DivisionAndRemainderOperations.h
The file was modifiedlibc/utils/FPUtil/SqrtLongDoubleX86.h
The file was modifiedlibc/utils/FPUtil/generic/FMA.h
The file was modifiedlibc/utils/FPUtil/BasicOperations.h
The file was modifiedlibc/utils/FPUtil/NormalFloat.h
The file was modifiedlibc/utils/FPUtil/Sqrt.h
The file was modifiedlibc/test/src/math/NextAfterTest.h
The file was modifiedlibc/test/src/math/RoundToIntegerTest.h
The file was modifiedlibc/utils/FPUtil/FPBits.h
The file was modifiedlibc/utils/FPUtil/ManipulationFunctions.h
The file was modifiedlibc/test/src/math/SqrtTest.h
The file was modifiedlibc/utils/FPUtil/TestHelpers.cpp
Commit 24129fbc9aa006badc2e6e8432980cb94aba090c by ayermolo
[LLD] Adding support for RELA for CG Profile.

This is a follow up to https://reviews.llvm.org/D104080, and https://github.com/llvm/llvm-project/commit/ca3bdb57fa1ac98b711a735de048c12b5fdd8086#diff-e64a48fabe31db213a631fdc5f2acb51bdddf3f16a8fb2928784f4c579229585. The implementation of  call graph profile was changed from a black box section to relocation approach. This was done to be compatible with post processing tools like strip/objcopy, and llvm equivalent. When they are invoked on object file before the final linking step with this new approach the symbol indices correctness is preserved.

The GNU binutils tools change the REL section to RELA section, unlike llvm tools. For example when strip -S is run on the ELF object files, as an intermediate step before linking. To preserve compatibility this patch extends implementation in LLD and ELFDumper to support both REL and RELA sections for call graph profile.

Reviewed By: MaskRay, jhenderson

Differential Revision: https://reviews.llvm.org/D105217
The file was addedlld/test/ELF/cgprofile-rela.test
The file was modifiedllvm/tools/llvm-readobj/ELFDumper.cpp
The file was modifiedlld/ELF/Driver.cpp
The file was modifiedlld/ELF/InputFiles.h
The file was modifiedlld/ELF/InputFiles.cpp
The file was modifiedllvm/test/tools/llvm-readobj/ELF/call-graph-profile.test
Commit d4e2693a679927a62dd738dd3bba24863dcd290a by dschuff
[WebAssembly] Run varargs codegen test with non-emscripten triple

This is a followup from D105749 to cover both triples in the case
where they differ.
The file was modifiedllvm/test/CodeGen/WebAssembly/varargs.ll
Commit 8a2720d81e159fc71550b10b4c34f1de912d5880 by jpienaar
Add more types to the LLVM dialect C API

This includes:
- void type
- array types
- function types
- literal (unnamed) struct types

Reviewed By: jpienaar, ftynse

Differential Revision: https://reviews.llvm.org/D105908
The file was modifiedmlir/include/mlir-c/Dialect/LLVM.h
The file was modifiedmlir/lib/CAPI/Dialect/LLVM.cpp
The file was modifiedmlir/test/CAPI/llvm.c
Commit 123e8dfcf86a74eb7ba08f33681df581d1be9dbd by ajcbik
[mlir][sparse] add support for std unary operations

Adds zero-preserving unary operators from std. Also adds xor.
Performs minor refactoring to remove "zero" node, and pushed
the irregular logic for negi (not support in std) into one place.

Reviewed By: gussmith23

Differential Revision: https://reviews.llvm.org/D105928
The file was modifiedmlir/include/mlir/Dialect/SparseTensor/Utils/Merger.h
The file was modifiedmlir/test/Dialect/SparseTensor/sparse_fp_ops.mlir
The file was modifiedmlir/lib/Dialect/SparseTensor/Transforms/Sparsification.cpp
The file was modifiedmlir/lib/Dialect/SparseTensor/Utils/Merger.cpp
The file was modifiedmlir/unittests/Dialect/SparseTensor/MergerTest.cpp
The file was modifiedmlir/test/Dialect/SparseTensor/sparse_int_ops.mlir
Commit f2b5e438aa3620cd60d115cad8dcb39cc417c8a8 by ravishankarm
[mlir][Tensor] Implement `reifyReturnTypeShapesPerResultDim` for `tensor.insert_slice`.

Differential Revision: https://reviews.llvm.org/D105852
The file was modifiedmlir/include/mlir/Dialect/Tensor/IR/Tensor.h
The file was addedmlir/test/Dialect/Tensor/resolve-shaped-type-result-dims.mlir
The file was modifiedmlir/lib/Dialect/Tensor/IR/TensorOps.cpp
The file was modifiedmlir/include/mlir/Dialect/Tensor/IR/TensorOps.td
The file was modifiedmlir/lib/Dialect/Tensor/IR/CMakeLists.txt
The file was modifiedutils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Commit 18c19414eb70578d4c487d6f4b0f438aead71d6a by wei.huang
[PowerPC] Add PowerPC compare and multiply related builtins and instrinsics for XL compatibility

This patch is in a series of patches to provide builtins for compatibility
with the XL compiler. This patch adds the builtins and instrisics for compare
and multiply related operations.

Reviewed By: nemanjai, #powerpc

Differential revision: https://reviews.llvm.org/D102875
The file was addedllvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-compare-64bit-only.ll
The file was addedclang/test/CodeGen/builtins-ppc-xlcompat-multiply-64bit-only.c
The file was addedllvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-compare.ll
The file was addedclang/test/CodeGen/builtins-ppc-xlcompat-pwr9-error.c
The file was modifiedllvm/include/llvm/IR/IntrinsicsPowerPC.td
The file was modifiedllvm/lib/Target/PowerPC/PPCInstr64Bit.td
The file was addedllvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-multiply-64bit-only.ll
The file was modifiedclang/include/clang/Basic/BuiltinsPPC.def
The file was modifiedclang/lib/Sema/SemaChecking.cpp
The file was addedclang/test/CodeGen/builtins-ppc-xlcompat-multiply.c
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrInfo.td
The file was addedllvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-multiply.ll
The file was addedclang/test/CodeGen/builtins-ppc-xlcompat-pwr9-64bit.c
The file was addedclang/test/CodeGen/builtins-ppc-xlcompat-pwr9.c
The file was modifiedclang/lib/Basic/Targets/PPC.cpp
Commit 9955c652eafdcb5f1d16ee3db857f03ee7e5cfbc by gcmn
[NFC][MLIR][std] Clean up ArithmeticCastOps

The documentation on these was out of sync with the implementation. Also
the declaration of inputs was repeated when it is already part of the
ArithmeticCastOp definition.

Reviewed By: rriddle

Differential Revision: https://reviews.llvm.org/D105934
The file was modifiedmlir/include/mlir/Dialect/StandardOps/IR/Ops.td
Commit 5df99954392e3a4448e4ff43d4cf644bc06bfa92 by Vitaly Buka
[NFC][sanitizer] Rename some MemoryMapper members

Part of D105778
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_allocator_primary64.h
Commit afa3fedcda98db4d47694ed596270a5396074224 by Vitaly Buka
[NFC][sanitizer] Exctract DrainHalfMax

Part of D105778
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_allocator_local_cache.h
Commit bb8c7a980fe487eb322d38641db9145a6b6cb1d4 by efriedma
[ScalarEvolution] Make isKnownNonZero handle more cases.

Using an unsigned range instead of signed ranges is a bit more precise.

Differential Revision: https://reviews.llvm.org/D105941
The file was modifiedllvm/test/Analysis/ScalarEvolution/trip-count9.ll
The file was modifiedllvm/lib/Analysis/ScalarEvolution.cpp
Commit eebe841a47cbbd55bdcc32da943c92d18f88a5b8 by Matthew.Arsenault
RegAlloc: Allow targets to split register allocation

AMDGPU normally spills SGPRs to VGPRs. Previously, since all register
classes are handled at the same time, this was problematic. We don't
know ahead of time how many registers will be needed to be reserved to
handle the spilling. If no VGPRs were left for spilling, we would have
to try to spill to memory. If the spilled SGPRs were required for exec
mask manipulation, it is highly problematic because the lanes active
at the point of spill are not necessarily the same as at the restore
point.

Avoid this problem by fully allocating SGPRs in a separate regalloc
run from VGPRs. This way we know the exact number of VGPRs needed, and
can reserve them for a second run.  This fixes the most serious
issues, but it is still possible using inline asm to make all VGPRs
unavailable. Start erroring in the case where we ever would require
memory for an SGPR spill.

This is implemented by giving each regalloc pass a callback which
reports if a register class should be handled or not. A few passes
need some small changes to deal with leftover virtual registers.

In the AMDGPU implementation, a new pass is introduced to take the
place of PrologEpilogInserter for SGPR spills emitted during the first
run.

One disadvantage of this is currently StackSlotColoring is no longer
used for SGPR spills. It would need to be run again, which will
require more work.

Error if the standard -regalloc option is used. Introduce new separate
-sgpr-regalloc and -vgpr-regalloc flags, so the two runs can be
controlled individually. PBQB is not currently supported, so this also
prevents using the unhandled allocator.
The file was addedllvm/include/llvm/CodeGen/RegAllocCommon.h
The file was modifiedllvm/include/llvm/CodeGen/Passes.h
The file was modifiedllvm/lib/Target/AMDGPU/SIFrameLowering.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/pei-build-spill.mir
The file was addedllvm/test/CodeGen/AMDGPU/sgpr-spill-no-vgprs.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/extractelement-stack-lower.ll
The file was modifiedllvm/lib/CodeGen/RegAllocBase.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/virtregrewrite-undef-identity-copy.mir
The file was modifiedllvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/alloc-aligned-tuples-gfx908.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/sibling-call.ll
The file was modifiedllvm/lib/CodeGen/RegAllocFast.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/indirect-call.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/mul24-pass-ordering.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/spill-empty-live-interval.mir
The file was modifiedllvm/lib/CodeGen/RegAllocBase.h
The file was modifiedllvm/test/CodeGen/AMDGPU/attr-amdgpu-flat-work-group-size-vgpr-limit.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/spill_more_than_wavesize_csr_sgprs.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/alloc-aligned-tuples-gfx90a.mir
The file was modifiedllvm/lib/CodeGen/RegAllocGreedy.cpp
The file was addedllvm/test/CodeGen/AMDGPU/sgpr-regalloc-flags.ll
The file was modifiedllvm/lib/CodeGen/TargetPassConfig.cpp
The file was modifiedllvm/lib/CodeGen/RegAllocBasic.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/gfx-callable-preserved-registers.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/llc-pipeline.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/unstructured-cfg-def-use-issue.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/remat-vop.mir
The file was modifiedllvm/test/CodeGen/AMDGPU/agpr-csr.ll
The file was modifiedllvm/include/llvm/CodeGen/RegAllocRegistry.h
The file was modifiedllvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll
The file was modifiedllvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/sgpr-spill-wrong-stack-id.mir
The file was modifiedllvm/lib/CodeGen/LiveIntervals.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/stack-slot-color-sgpr-vgpr-spills.mir
The file was modifiedllvm/lib/Target/AMDGPU/SIRegisterInfo.h
The file was modifiedllvm/test/CodeGen/AMDGPU/vgpr-tuple-allocation.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/callee-frame-setup.ll
The file was modifiedllvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
Commit 99aebb62fb4f2a39c7f03579facf3a1e176b245d by Vitaly Buka
[NFC][sanitizer] Don't store region_base_ in MemoryMapper

Part of D105778
The file was modifiedcompiler-rt/lib/sanitizer_common/tests/sanitizer_allocator_test.cpp
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_allocator_primary64.h
Commit 0024ec59a0f3deb206a21567ac2ebe0fc097ea9d by aeubanks
[NewPM][SimpleLoopUnswitch] Add option to not trivially unswitch

To help with debugging non-trivial unswitching issues.

Don't care about the legacy pass, nobody is using it.

If a pass's string params are empty (e.g. "simple-loop-unswitch"), don't
default to the empty constructor for the pass params. We should still
let the parser take care of it in case the parser has its own defaults.

Reviewed By: asbirlea

Differential Revision: https://reviews.llvm.org/D105933
The file was modifiedllvm/lib/Passes/PassRegistry.def
The file was modifiedllvm/lib/Transforms/Scalar/SimpleLoopUnswitch.cpp
The file was modifiedllvm/include/llvm/Transforms/Scalar/SimpleLoopUnswitch.h
The file was modifiedllvm/lib/Passes/PassBuilder.cpp
The file was addedllvm/test/Transforms/SimpleLoopUnswitch/options.ll
The file was modifiedllvm/test/Other/print-passes.ll
Commit 832ba20710ee09b00161ea72cf80c9af800fda63 by Vitaly Buka
sanitizer_common: optimize memory drain

Currently we allocate MemoryMapper per size class.
MemoryMapper mmap's and munmap's internal buffer.
This results in 50 mmap/munmap calls under the global
allocator mutex. Reuse MemoryMapper and the buffer
for all size classes. This radically reduces number of
mmap/munmap calls. Smaller size classes tend to have
more objects allocated, so it's highly likely that
the buffer allocated for the first size class will
be enough for all subsequent size classes.

Reviewed By: melver

Differential Revision: https://reviews.llvm.org/D105778
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_allocator_local_cache.h
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_allocator_primary64.h
Commit 3191ac27e396dbd141243b8ca6cf5660c10ddf5c by Matthew.Arsenault
AMDGPU: Try to fix test failure with EXPENSIVE_CHECKS

The machine verifier is enabled by default for EXPENSIVE_CHECKS, so
the pass runs of it would pollute the output here.
The file was modifiedllvm/test/CodeGen/AMDGPU/sgpr-regalloc-flags.ll
Commit 7140382b17df7c33145cc6e9a2df7e84a2259444 by Vitaly Buka
[NFC][sanitizer] Move MemoryMapper template parameter
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_allocator_primary64.h
The file was modifiedcompiler-rt/lib/sanitizer_common/tests/sanitizer_allocator_test.cpp
Commit 8725b382b0a5ea375252d966bafbace62a21e93b by Vitaly Buka
[NFC][sanitizer] Simplify MapPackedCounterArrayBuffer
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_allocator_primary64.h
The file was modifiedcompiler-rt/lib/sanitizer_common/tests/sanitizer_allocator_test.cpp
Commit 5bd7cc4f42488129adb135539c64bb3933d5da4c by Jessica Paquette
[AArch64][GlobalISel] Mark v2s64 -> v2p0 G_INTTOPTR as legal

Allow

```
%x:_<2 x p0> = G_INTTOPTR %y:_<2 x s64>
```

This shows up when building clang for AArch64 with GlobalISel.

Also show that we can select it.

This should match SDAG's behaviour: https://godbolt.org/z/33oqYoaYv

Differential Revision: https://reviews.llvm.org/D105944
The file was addedllvm/test/CodeGen/AArch64/GlobalISel/legalize-inttoptr.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/select-int-ptr-casts.mir
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
Commit ed430023e864c3b3ff7f47d5740e5380828c26f6 by Vitaly Buka
Revert "[NFC][sanitizer] Simplify MapPackedCounterArrayBuffer"

Does not compile.

This reverts commit 8725b382b0a5ea375252d966bafbace62a21e93b.
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_allocator_primary64.h
The file was modifiedcompiler-rt/lib/sanitizer_common/tests/sanitizer_allocator_test.cpp
Commit 5738819679fd3bb08c4848129b27c63690d937a5 by aeubanks
Revert "[SCEV] Handle zero stride correctly in howManyLessThans"

This reverts commit 4df591b5c960affd1612e330d0c9cd3076c18053.

Causes crashes, see comments on D105921.
The file was modifiedllvm/lib/Analysis/ScalarEvolution.cpp
The file was modifiedllvm/test/Analysis/ScalarEvolution/trip-count-unknown-stride.ll
Commit 6377388c32ffc1f5c054a813d0bc81ac118108af by jonathan_roelofs
[AArch64] Fix AArch64::dsub's size
The file was modifiedllvm/lib/Target/AArch64/AArch64RegisterInfo.td
Commit 87c6bf92a9c7722b18643ea73f76623f2463c5bb by jonathan_roelofs
[AArch64] rm unused subreg's
The file was modifiedllvm/lib/Target/AArch64/AArch64RegisterInfo.td
Commit 35ce66330a2686878ea0a1da93e0a94961933006 by Vitaly Buka
[NFC][sanitizer] Simplify MapPackedCounterArrayBuffer
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_allocator_primary64.h
The file was modifiedcompiler-rt/lib/sanitizer_common/tests/sanitizer_allocator_test.cpp
Commit 071203845887a2ff0347747bd5864f8738d17eef by hoy
[CSSPGO][llvm-profgen] Allow multiple executable load segments.

The linker or post-link optimizer can create an ELF image with multiple executable segments each of which will be loaded separately at run time. This breaks the assumption of llvm-profgen that currently only supports one base load address. What it ends up with is that the subsequent mmap events will be treated as an overwrite of the first mmap event which will in turn screw up address mapping. While it is non-trivial to support multiple separate load addresses and given that on x64 those segments will always be loaded at consecutive addresses (though via separate mmap
sys calls), I'm adding an error checking logic to bail out if that's violated and keep using a single load address which is the address of the first executable segment.

Also changing the disassembly output from printing section offset to printing the virtual address instead, which matches the behavior of objdump.

Differential Revision: https://reviews.llvm.org/D103178
The file was modifiedllvm/tools/llvm-profgen/ProfiledBinary.cpp
The file was modifiedllvm/tools/llvm-profgen/PerfReader.h
The file was addedllvm/test/tools/llvm-profgen/Inputs/multi-load-segs.perfscript
The file was modifiedllvm/tools/llvm-profgen/PerfReader.cpp
The file was modifiedllvm/test/tools/llvm-profgen/mmapEvent.test
The file was addedllvm/test/tools/llvm-profgen/Inputs/symbolize.perfbin
The file was modifiedllvm/tools/llvm-profgen/ProfiledBinary.h
The file was addedllvm/test/tools/llvm-profgen/Inputs/symbolize.ll
The file was removedllvm/test/tools/llvm-profgen/disassemble.s
The file was removedllvm/test/tools/llvm-profgen/symbolize.ll
The file was addedllvm/test/tools/llvm-profgen/symbolize.test
The file was addedllvm/test/tools/llvm-profgen/multi-load-segs.test
The file was addedllvm/test/tools/llvm-profgen/Inputs/multi-load-segs.perfbin
The file was addedllvm/test/tools/llvm-profgen/disassemble.test
Commit 74b99b5c2eacbdef15b99b3e0a8073598f985bb4 by hoy
[CSSPGO] Do not import pseudo probe desc in thinLTO

Previously we reliedy on pseudo probe descriptors to look up precomputed GUID during probe emission for inlined probes. Since we are moving to always using unique linkage names, GUID for functions can be computed in place from dwarf names. This eliminates the need of importing pseudo probe descs in thinlto, since those descs should be emitted by the original modules.

This significantly reduces thinlto memory footprint in some extreme case where the number of imported modules for a single module is massive.

Test Plan:

Reviewed By: wenlei

Differential Revision: https://reviews.llvm.org/D105248
The file was modifiedllvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
The file was modifiedllvm/lib/Linker/IRMover.cpp
The file was addedllvm/test/ThinLTO/X86/pseudo-probe-desc-import.ll
The file was addedllvm/test/ThinLTO/X86/Inputs/pseudo-probe-desc-import.ll
The file was modifiedllvm/lib/CodeGen/AsmPrinter/PseudoProbePrinter.cpp
The file was modifiedllvm/lib/CodeGen/AsmPrinter/PseudoProbePrinter.h
Commit cda2394d9768f97cbacbbf8a5c6288c1015b981a by hoy
[NFC][CSSPGO] Rename the name of an enum value.
The file was modifiedllvm/tools/llvm-profgen/PerfReader.cpp
Commit 8a0f1163d02c77c6e764929b66c26ba196cfc549 by richard
Fix test trying to write a spurious output file into the source
directory.

This causes test failures if the source directory is read-only.
The file was modifiedclang/test/CodeGen/builtins-ppc-xlcompat-pwr9.c
The file was modifiedclang/test/CodeGen/builtins-ppc-xlcompat-pwr9-64bit.c
Commit 205ed009a44c2b04a15aea039d8947e74856f158 by efriedma
[SCEV] Handle zero stride correctly in howManyLessThans

This is split from D105216, but the code is hoisted much earlier into
the path where we can actually get a zero stride flowing through. Some
fairly simple proofs handle the cases which show up in practice. The
only test changes are the cases where we really do need a non-zero
divider to produce the right result.

Recommitting with isLoopInvariant() check.

Differential Revision: https://reviews.llvm.org/D105921
The file was modifiedllvm/lib/Analysis/ScalarEvolution.cpp
The file was modifiedllvm/test/Analysis/ScalarEvolution/trip-count-unknown-stride.ll
Commit 1100e4aafea233bc8bbc307c5758a7d287ad3bae by tianshilei1992
[AbstractAttributor] Fold function calls to `__kmpc_is_spmd_exec_mode` if possible

In the device runtime there are many function calls to `__kmpc_is_spmd_exec_mode`
to query the execution mode of current kernels. In many cases, user programs
only contain target region executing in one mode. As a consequence, those runtime
function calls will only return one value. If we can get rid of these function
calls during compliation, it can potentially improve performance.

In this patch, we use `AAKernelInfo` to analyze kernel execution. Basically, for
each kernel (device) function `F`, we collect all kernel entries `K` that can
reach `F`. A new AA, `AAFoldRuntimeCall`, is created for each call site. In each
iteration, it will check all reaching kernel entries, and update the folded value
accordingly.

In the future we will support more function.

Reviewed By: jdoerfert

Differential Revision: https://reviews.llvm.org/D105787
The file was modifiedllvm/lib/Transforms/IPO/OpenMPOpt.cpp
The file was addedllvm/test/Transforms/OpenMP/is_spmd_exec_mode_fold.ll
The file was modifiedllvm/test/Transforms/OpenMP/custom_state_machines.ll
Commit fef5f4456abcb1ea052206db6c232468d70b07f2 by hoy
[CSSPGO][llvm-profgen] Fix a missing initalization

Fixing a missing initalization that accidentaly caused by https://reviews.llvm.org/D103178 .
The file was modifiedllvm/tools/llvm-profgen/ProfiledBinary.h
Commit 597e9c61cee39071141f3c8f31f47561d2844196 by hoy
Revert "[CSSPGO][llvm-profgen] Fix a missing initalization"

This reverts commit fef5f4456abcb1ea052206db6c232468d70b07f2.
The file was modifiedllvm/tools/llvm-profgen/ProfiledBinary.h
Commit 6b04ecaab355f0dfce8a980cb67a39662759734c by hoy
[CSSPGO][llvm-profgen] Fix a missing initalization

Fixing a missing initalization that accidentaly caused by https://reviews.llvm.org/D103178 .
The file was modifiedllvm/tools/llvm-profgen/ProfiledBinary.h
Commit 64785ac12ef8b94fe7281e2cbe2db68d64d55e4c by Jinsong Ji
[AIX] Update testcase to use aix triple

We have implemented the basic MCAsmParser now, we can use the triple
directly now.
The file was modifiedllvm/test/MC/PowerPC/modern-aix-as.s
Commit d5c0b0102a25c27f41137588422d368eb42d971e by llvm-project
[Polly] Fix typo. NFC.

Thanks to Mugerwa Martin for reporting.
The file was modifiedpolly/docs/Architecture.rst
Commit ba127a45701b5fa870a1df6b1fb09a351ad14051 by Vitaly Buka
[sanitizer] Convert script to python 3
The file was modifiedcompiler-rt/test/sanitizer_common/android_commands/android_compile.py
Commit 40ce58d0ca10a1195da82895749b67f30f000243 by david.green
Revert "[clang] Refactor AST printing tests to share more infrastructure"

This reverts commit 20176bc7dd3f431db4c3d59b51a9f53d52190c82 as some
versions of GCC do not seem to handle the new code very well. They
complain about:

/tmp/ccqUQZyw.s: Assembler messages:
/tmp/ccqUQZyw.s:1151: Error: symbol `_ZNSt14_Function_base13_Base_managerIN5clangUlPKNS1_4StmtEE2_EE10_M_managerERSt9_Any_dataRKS7_St18_Manager_operation' is already defined
/tmp/ccqUQZyw.s:11963: Error: symbol `_ZNSt17_Function_handlerIFbPKN5clang4StmtEENS0_UlS3_E2_EE9_M_invokeERKSt9_Any_dataOS3_' is already defined

This seems like it is some GCC issue, but multiple buildbots (and my
local machine) are all failing because of it.
The file was modifiedclang/unittests/AST/ASTPrint.h
The file was modifiedclang/unittests/AST/DeclPrinterTest.cpp
The file was modifiedclang/unittests/AST/NamedDeclPrinterTest.cpp
The file was modifiedclang/unittests/AST/StmtPrinterTest.cpp
Commit 94210b12d1d6454c6de8ca4c83a82a1148b5cd1a by Vitaly Buka
[sanitizer] Upgrade android scripts to python 3
The file was modifiedcompiler-rt/test/sanitizer_common/android_commands/android_common.py
The file was modifiedcompiler-rt/test/sanitizer_common/android_commands/android_run.py
Commit 16f8207de377a055b7b75a3003d82059ca63992d by Vitaly Buka
[sanitizer] Fix type error in python 3
The file was modifiedcompiler-rt/test/sanitizer_common/android_commands/android_run.py
Commit 08cf69c31f849310ec45945d18f0feef4ea8f2e6 by zakk.chen
[RISCV] Support overloading for RVV miscellaneous functions.

Based on this update to the intrinsic doc
https://github.com/riscv/rvv-intrinsic-doc/pull/103

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D105611
The file was addedclang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vset.c
The file was addedclang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlmul.c
The file was modifiedclang/include/clang/Basic/riscv_vector.td
The file was addedclang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vget.c
The file was modifiedclang/utils/TableGen/RISCVVEmitter.cpp
The file was addedclang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vreinterpret.c
Commit 8ae31b08d9da5f42dd149eb48ef3e3baae2d1b07 by joker.eph
Reformulate OrcJIT tutorial doc to make it more clear.

Fixed a minor writing error. The text was hard to understand.

Reviewed By: mehdi_amini

Differential Revision: https://reviews.llvm.org/D105899
The file was modifiedllvm/docs/tutorial/BuildingAJIT2.rst
Commit dfd9808b6cea59ff075498ee7e6e57f2b5b3a798 by Vitaly Buka
sanitizer_common: add simpler ThreadRegistry ctor

Currently ThreadRegistry is overcomplicated because of tsan,
it needs tid quarantine and reuse counters. Other sanitizers
don't need that. It also seems that no other sanitizer now
needs max number of threads. Asan used to need 2^24 limit,
but it does not seem to be needed now. Other sanitizers blindly
copy-pasted that without reasons. Lsan also uses quarantine,
but I don't see why that may be potentially needed.

Add a ThreadRegistry ctor that does not require any sizes
and use it in all sanitizers except for tsan.
In preparation for new tsan runtime, which won't need
any of these parameters as well.

Reviewed By: vitalybuka

Differential Revision: https://reviews.llvm.org/D105713
The file was modifiedcompiler-rt/lib/asan/asan_thread.cpp
The file was modifiedcompiler-rt/lib/memprof/memprof_thread.cpp
The file was modifiedcompiler-rt/lib/asan/asan_thread.h
The file was modifiedcompiler-rt/lib/sanitizer_common/tests/sanitizer_thread_registry_test.cpp
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_thread_registry.h
The file was modifiedcompiler-rt/lib/memprof/memprof_thread.h
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_thread_registry.cpp
The file was modifiedcompiler-rt/lib/lsan/lsan_thread.cpp
Commit 2c425c17e678c522d8f4961e9ad94ad718a7cba0 by martin
[libcxx] [test] Clarify weak_ptr_ret on Windows, remove a LIBCXX-WINDOWS-FIXME

On Windows, structs with a destructor are always returned indirectly;
add this to the list of known exceptions in the test where the class
isn't returned in registers as expected.

Differential Revision: https://reviews.llvm.org/D105906
The file was modifiedlibcxx/test/libcxx/memory/trivial_abi/weak_ptr_ret.pass.cpp
Commit 5635d2a56dab6dc64d3a3f185d68f676b81dc736 by kito.cheng
[RISCV] Pass -u to linker correctly.

`-u` is a linker option used to pretend a symbol is undefined,
this option are common used for forcing archive member extraction.

This option should pass to `ld`, and many other toolchain in Clang
like `tools::gnutools` has pass that too.

Reviewed By: MaskRay

Differential Revision: https://reviews.llvm.org/D105091
The file was modifiedclang/lib/Driver/ToolChains/RISCVToolchain.cpp
The file was modifiedclang/test/Driver/riscv-args.c
Commit 40e3df2a1b229096b899443abf0d95784d7a4bea by ruiling.song
[RegisterCoalescer] Resolve conflict based on liveness of subregister

Currently we are resolving lane/subregister conflict by visiting
instructions sequentially in current block to see whether there is any
use of the tainted lanes. To save compile time, we are not doing further
check in successor blocks. This sounds reasonable without subgregister liveness.

But since we have added subregister liveness tracking capability to
register coalescer, we can easily determine whether we have subregister
liveness conflict by checking subranges. This would help coalescing more
COPYs for target that enables subregister liveness tracking.

Reviewed by: arsenm, qcolombet

Differential Revision: https://reviews.llvm.org/D104509
The file was modifiedllvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/wwm-reserved-spill.ll
The file was modifiedllvm/lib/CodeGen/RegisterCoalescer.cpp
The file was addedllvm/test/CodeGen/AMDGPU/regcoalescer-resolve-lane-conflict-by-subranges.mir
Commit 1d9585c8c1ce5c6b9d2e16ba476294b0ee8d9edb by ruiling.song
[NFC][AMDGPU] autogenerate kill-infinite-loop.ll checks

This would help us to track the assembly changes to these tests.

Reviewed by: foad

Differential Revision: https://reviews.llvm.org/D105609
The file was modifiedllvm/test/CodeGen/AMDGPU/kill-infinite-loop.ll
Commit d9b9fdd91bb49292cf7c01bb72ece7e9d9f2e9ac by ruiling.song
[AMDGPU] Don't handle export done when unify exit nodes

This patch aims to revert the changes introduced by D70781 D71192 D76364

D70781 was introduced to fix hardware hang where we do not insert exp-
null-done for a kill inside infinit loop. At that time we have not added
exp-null-done for kill early termination, but I believe as for now, we will
always add the exp-null-done for early termination case in LaterBranchLowering.

D71192 was introduced to handle the only_kill case, which is also been
handled by the kill early termination work.

D76364 was used to fix a regression by D71192, where we cleared the done
bit of the export in the existing program and not let the normal return
block branching to the new unified return block.

With this change, we just trust frontends have setup exp-done correctly
which is true for all existing frontends. The backend only inserts
exp-null-done for the kill cases which is handled in SILateBranchLowering.cpp.

Reviewed by: critson

Differential Revision: https://reviews.llvm.org/D105610
The file was modifiedllvm/test/CodeGen/AMDGPU/kill-infinite-loop.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/update-phi.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/multi-divergent-exit-region.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUUnifyDivergentExitNodes.cpp
Commit 462d4de35b0c9ef7157e49e147fc448a40c829b1 by sam.mccall
[clangd] Add CMake option to (not) link in clang-tidy checks

This reduces the size of the dependency graph and makes incremental
development a little more pleasant (less rebuilding).

This introduces a bit of complexity/fragility as some tests verify
clang-tidy behavior. I attempted to isolate these and build/run as much
of the tests as possible in both configs to prevent rot.

Expectation is that (some) developers will use this locally, but
buildbots etc will keep testing clang-tidy.

Fixes https://github.com/clangd/clangd/issues/233

Differential Revision: https://reviews.llvm.org/D105679
The file was modifiedclang-tools-extra/clangd/Features.cpp
The file was modifiedclang-tools-extra/clangd/test/lit.site.cfg.py.in
The file was modifiedclang-tools-extra/clangd/test/lit.cfg.py
The file was modifiedclang-tools-extra/clangd/Features.inc.in
The file was modifiedclang-tools-extra/clangd/unittests/DiagnosticsTests.cpp
The file was removedclang-tools-extra/clangd/test/diagnostics.test
The file was modifiedclang-tools-extra/clangd/ParsedAST.cpp
The file was addedclang-tools-extra/clangd/test/diagnostics-tidy.test
The file was modifiedclang-tools-extra/clangd/unittests/ConfigCompileTests.cpp
The file was modifiedclang-tools-extra/clangd/CMakeLists.txt
Commit c08dabb0f476e7ff3df70d379f3507707acbac4e by cullen.rhodes
[AArch64][SME] Add matrix register definitions and parsing support

SME introduces the ZA array, a new piece of architectural register state
consisting of a matrix of [SVLb x SVLb] bytes, where SVL is the
implementation defined Streaming SVE vector length and SVLb is the
number of 8-bit elements in a vector of SVL bits.

SME instructions consist of three types of matrix operands:

  * Tiles: a ZA tile is a square, two-dimensional sub-array of elements
  within the ZA array. These tiles make up the larger accumulator array
  and the granularity varies based on the element size, i.e.
    - ZAQ0..ZAQ15 (smallest tile granule)
    - ZAD0..ZAD7
    - ZAS0..ZAS3
    - ZAH0..ZAH1
    or ZAB0       (largest tile granule, single tile)
  * Tile vectors: similar to regular tiles, but have an extra 'h' or 'v'
  to tell how the vector at [reg+offset] is layed out in the tile,
  horizontally or vertically. E.g. za1h.h or za15v.q, which corresponds
  to vectors in registers ZAH1 and ZAQ15, respectively.
  * Accumulator matrix: this is the entire accumulator array ZA.

This patch adds the register classes and related operands and parsing
for SME instructions operating on the accumulator array.

The ADDHA and ADDVA instructions which operate on tiles are also added
in this patch to make some use of the code added, later patches will
make use of the other operands introduced here.

The reference can be found here:
https://developer.arm.com/documentation/ddi0602/2021-06

Co-authored by: Sander de Smalen (@sdesmalen)

Reviewed By: david-arm

Differential Revision: https://reviews.llvm.org/D105570
The file was modifiedllvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
The file was modifiedllvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
The file was addedllvm/test/MC/AArch64/SME/addha-u32.s
The file was addedllvm/test/MC/AArch64/SME/addva-u64.s
The file was addedllvm/test/MC/AArch64/SME/addha-u64.s
The file was modifiedllvm/unittests/Target/AArch64/CMakeLists.txt
The file was modifiedllvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.h
The file was addedllvm/lib/Target/AArch64/SMEInstrFormats.td
The file was addedllvm/test/MC/AArch64/SME/addva-diagnostics.s
The file was modifiedllvm/lib/Target/AArch64/AArch64RegisterInfo.td
The file was addedllvm/unittests/Target/AArch64/MatrixRegisterAliasing.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrInfo.td
The file was addedllvm/test/MC/AArch64/SME/addha-diagnostics.s
The file was addedllvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
The file was addedllvm/test/MC/AArch64/SME/addva-u32.s
The file was modifiedllvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
Commit a12e551882b68fe36856b0e66a5699fcf124aac5 by sebastian.neubauer
[AMDGPU] Precommit flat-scratch-init.ll test
The file was addedllvm/test/CodeGen/AMDGPU/flat-scratch-init.ll
Commit 4359b870b187dca39573728002ce6bc0ffd4d469 by sebastian.neubauer
[AMDGPU] Init scratch only if necessary

If no scratch or flat instructions are used, we do not need to
initialize the flat scratch hardware register.

Differential Revision: https://reviews.llvm.org/D105920
The file was modifiedllvm/test/CodeGen/AMDGPU/cc-update.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/flat-scratch-init.ll
The file was modifiedllvm/lib/Target/AMDGPU/SIFrameLowering.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/spill-offset-calculation.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/memory_clause.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/local-stack-alloc-block-sp-reference.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch-init.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll
The file was modifiedllvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/large-alloca-compute.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/stack-realign-kernel.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/dynamic-alloca-uniform.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/non-entry-alloca.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/non-entry-alloca.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/call-constant.ll
Commit 03a4702c884a0498db902aff34ebb19c48b4696b by fraser
[RISCV] Fix the neutral element in vector 'fadd' reductions

Using positive zero as the neutral element in 'fadd' reductions, while
it generates better code, is incorrect. The correct neutral element is
negative zero: 0.0 + -0.0 = 0.0, whereas -0.0 + -0.0 = -0.0.

There are perhaps more optimal lowerings of negative zero avoiding
constant-pool loads which could be left as future work.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D105902
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vreductions-fp-sdnode.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.cpp
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll
Commit a36e9ee09d2ea46d752b6eea30168ec1fe73d17f by ivan.butygin
[mlir][SCF] populateSCFStructuralTypeConversionsAndLegality WhileOp support

Differential Revision: https://reviews.llvm.org/D105923
The file was modifiedmlir/test/Dialect/SCF/bufferize.mlir
The file was modifiedmlir/lib/Dialect/SCF/Transforms/StructuralTypeConversions.cpp
Commit b803294cf78714303db2d3647291a2308347ef23 by llvm-dev
[InstCombine] Fold (select C, (gep Ptr, Idx), Ptr) -> (gep Ptr, (select C, Idx, 0)) (PR50183)

As discussed on PR50183, we already fold to prefer 'select-of-idx' vs 'select-of-gep':

define <4 x i32>* @select0a(<4 x i32>* %a0, i64 %a1, i1 %a2, i64 %a3) {
  %gep0 = getelementptr inbounds <4 x i32>, <4 x i32>* %a0, i64 %a1
  %gep1 = getelementptr inbounds <4 x i32>, <4 x i32>* %a0, i64 %a3
  %sel = select i1 %a2, <4 x i32>* %gep0, <4 x i32>* %gep1
  ret <4 x i32>* %sel
}
-->
define <4 x i32>* @select1a(<4 x i32>* %a0, i64 %a1, i1 %a2, i64 %a3) {
  %sel = select i1 %a2, i64 %a1, i64 %a3
  %gep = getelementptr inbounds <4 x i32>, <4 x i32>* %a0, i64 %sel
  ret <4 x i32>* %gep
}

This patch adds basic handling for the 'fallthrough' cases where the gep idx == 0 has been folded away to the base address:

define <4 x i32>* @select0(<4 x i32>* %a0, i64 %a1, i1 %a2) {
  %gep = getelementptr inbounds <4 x i32>, <4 x i32>* %a0, i64 %a1
  %sel = select i1 %a2, <4 x i32>* %a0, <4 x i32>* %gep
  ret <4 x i32>* %sel
}
-->
define <4 x i32>* @select1(<4 x i32>* %a0, i64 %a1, i1 %a2) {
  %sel = select i1 %a2, i64 0, i64 %a1
  %gep = getelementptr inbounds <4 x i32>, <4 x i32>* %a0, i64 %sel
  ret <4 x i32>* %gep
}

Differential Revision: https://reviews.llvm.org/D105901
The file was modifiedllvm/test/Transforms/InstCombine/select-gep.ll
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
Commit 810e4c3c66ed69ba82af687fc2a184bae874ca08 by stephen.tozer
[DebugInfo] Correctly update dbg.values with duplicated location ops

This patch fixes code that incorrectly handled dbg.values with duplicate
location operands, i.e. !DIArgList(i32 %a, i32 %a). The errors in
question were caused by either applying an update to dbg.value multiple
times when the update is only valid once, or by updating the
DIExpression for only the first instance of a value that appears
multiple times.

Differential Revision: https://reviews.llvm.org/D105831
The file was modifiedllvm/test/CodeGen/AArch64/stack-tagging-dbg.ll
The file was modifiedllvm/test/Instrumentation/HWAddressSanitizer/alloca.ll
The file was modifiedllvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp
The file was modifiedllvm/lib/Transforms/Utils/Local.cpp
The file was addedllvm/test/DebugInfo/salvage-duplicate-values.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64StackTagging.cpp
Commit cf0aa0b66ccec87b0ac14f632998074e507be950 by stefanp
[NFC][PowerPC] Added test to check regsiter allocation for ACC registers

ACC regsiters are a combination of 4 consecutive vector regsiters and therefore
somtimes require special treatment for register allocation. This patch only
adds a test.
The file was addedllvm/test/CodeGen/PowerPC/ppc64-acc-regalloc.ll
Commit aff09545779a5346984e3c0d4f0d887185cb662d by thakis
[gn build] (manually) merge 462d4de35b0c
The file was modifiedllvm/utils/gn/secondary/clang-tools-extra/clangd/test/BUILD.gn
The file was modifiedllvm/utils/gn/secondary/clang-tools-extra/clangd/BUILD.gn
Commit 0722f3d0fad16d2427acf66a591bf3597fd0e0d8 by llvm-dev
Revert rGb803294cf78714303db2d3647291a2308347ef23 : "[InstCombine] Fold (select C, (gep Ptr, Idx), Ptr) -> (gep Ptr, (select C, Idx, 0)) (PR50183)"

Missed some BPF test changes that need addressing
The file was modifiedllvm/test/Transforms/InstCombine/select-gep.ll
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
Commit 90e7f5d25902fe7d7a8eac1b6050f6a3f8c0919e by llvmgnsyncbot
[gn build] Port c08dabb0f476
The file was modifiedllvm/utils/gn/secondary/llvm/unittests/Target/AArch64/BUILD.gn
Commit ee71c1bbccb19ed7a30b9aaf112a2c6ac2987193 by llvm-dev
[X86] Implement smarter instruction lowering for FP_TO_UINT from f32/f64 to i32/i64 and vXf32/vXf64 to vXi32 for SSE2 and AVX2 by using the exact semantic of the CVTTPS2SI instruction.

We know that "CVTTPS2SI" returns 0x80000000 for out of range inputs (and for FP_TO_UINT, negative float values are undefined). We can use this to make unsigned conversions from vXf32 to vXi32 more efficient, particularly on targets without blend using the following logic:

small := CVTTPS2SI(x);
fp_to_ui(x) := small | (CVTTPS2SI(x - 2^31) & ARITHMETIC_RIGHT_SHIFT(small, 31))

Even on targets where "PBLENDVPS"/"PBLENDVB" exists, it is often a latency 2, low throughput instruction so this logic is applied there too (in particular for AVX2 also). It furthermore gets rid of one high latency floating point comparison in the previous lowering.

@TomHender checked the correctness of this for all possible floats between -1 and 2^32 (both ends excluded).

Original Patch by @TomHender (Tom Hender)

Differential Revision: https://reviews.llvm.org/D89697
The file was modifiedllvm/test/CodeGen/X86/concat-cast.ll
The file was modifiedllvm/test/CodeGen/X86/vec_cast3.ll
The file was modifiedllvm/test/CodeGen/X86/half.ll
The file was modifiedllvm/lib/Target/X86/X86TargetTransformInfo.cpp
The file was modifiedllvm/test/CodeGen/X86/fptoui-sat-scalar.ll
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/fptoui.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/fptoui.ll
The file was modifiedllvm/test/CodeGen/X86/vec_fp_to_int.ll
The file was modifiedllvm/test/CodeGen/X86/ftrunc.ll
The file was modifiedllvm/test/CodeGen/X86/scalar-fp-to-i32.ll
The file was modifiedllvm/test/CodeGen/X86/scalar-fp-to-i64.ll
Commit f7d931ac373fc23f5f4493300ecf7f3fe08b9d67 by david.spickett
[lldb][docs] Remove mention of subversion. NFC.

Reviewed By: DavidSpickett

Differential Revision: https://reviews.llvm.org/D103744
The file was modifiedlldb/docs/resources/build.rst
Commit 12d04ce9569edec68220888e02aab4fc25e55e01 by yedeng.yd
[NFC] [Coroutines] Remove unused CoroFree
The file was modifiedllvm/lib/Transforms/Coroutines/CoroElide.cpp
Commit d561b6fbdbe6d1da05fd92003a4ac1e37bf4b8bc by llvm-dev
[InstCombine] Fold (select C, (gep Ptr, Idx), Ptr) -> (gep Ptr, (select C, Idx, 0)) (PR50183) (REAPPLIED)

As discussed on PR50183, we already fold to prefer 'select-of-idx' vs 'select-of-gep':

define <4 x i32>* @select0a(<4 x i32>* %a0, i64 %a1, i1 %a2, i64 %a3) {
  %gep0 = getelementptr inbounds <4 x i32>, <4 x i32>* %a0, i64 %a1
  %gep1 = getelementptr inbounds <4 x i32>, <4 x i32>* %a0, i64 %a3
  %sel = select i1 %a2, <4 x i32>* %gep0, <4 x i32>* %gep1
  ret <4 x i32>* %sel
}
-->
define <4 x i32>* @select1a(<4 x i32>* %a0, i64 %a1, i1 %a2, i64 %a3) {
  %sel = select i1 %a2, i64 %a1, i64 %a3
  %gep = getelementptr inbounds <4 x i32>, <4 x i32>* %a0, i64 %sel
  ret <4 x i32>* %gep
}

This patch adds basic handling for the 'fallthrough' cases where the gep idx == 0 has been folded away to the base address:

define <4 x i32>* @select0(<4 x i32>* %a0, i64 %a1, i1 %a2) {
  %gep = getelementptr inbounds <4 x i32>, <4 x i32>* %a0, i64 %a1
  %sel = select i1 %a2, <4 x i32>* %a0, <4 x i32>* %gep
  ret <4 x i32>* %sel
}
-->
define <4 x i32>* @select1(<4 x i32>* %a0, i64 %a1, i1 %a2) {
  %sel = select i1 %a2, i64 0, i64 %a1
  %gep = getelementptr inbounds <4 x i32>, <4 x i32>* %a0, i64 %sel
  ret <4 x i32>* %gep
}

Reapplied with a fix for the bpf "-bpf-disable-avoid-speculation" tests

Differential Revision: https://reviews.llvm.org/D105901
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
The file was modifiedllvm/test/Transforms/InstCombine/select-gep.ll
The file was modifiedllvm/test/CodeGen/BPF/adjust-opt-speculative1.ll
The file was modifiedllvm/test/CodeGen/BPF/adjust-opt-speculative2.ll
Commit df686842bc522b74755e8acbe3de8594e2c36bbd by djtodoro
[RemoveRedundantDebugValues] Add a Pass that removes redundant DBG_VALUEs

This new MIR pass removes redundant DBG_VALUEs.

After the register allocator is done, more precisely, after
the Virtual Register Rewriter, we end up having duplicated
DBG_VALUEs, since some virtual registers are being rewritten
into the same physical register as some of existing DBG_VALUEs.
Each DBG_VALUE should indicate (at least before the LiveDebugValues)
variables assignment, but it is being clobbered for function
parameters during the SelectionDAG since it generates new DBG_VALUEs
after COPY instructions, even though the parameter has no assignment.
For example, if we had a DBG_VALUE $regX as an entry debug value
representing the parameter, and a COPY and after the COPY,
DBG_VALUE $virt_reg, and after the virtregrewrite the $virt_reg gets
rewritten into $regX, we'd end up having redundant DBG_VALUE.

This breaks the definition of the DBG_VALUE since some analysis passes
might be built on top of that premise..., and this patch tries to fix
the MIR with the respect to that.

This first patch performs bacward scan, by trying to detect a sequence of
consecutive DBG_VALUEs, and to remove all DBG_VALUEs describing one
variable but the last one:

For example:

(1) DBG_VALUE $edi, !"var1", ...
(2) DBG_VALUE $esi, !"var2", ...
(3) DBG_VALUE $edi, !"var1", ...
...

in this case, we can remove (1).

By combining the forward scan that will be introduced in the next patch
(from this stack), by inspecting the statistics, the RemoveRedundantDebugValues
removes 15032 instructions by using gdb-7.11 as a testbed.

Differential Revision: https://reviews.llvm.org/D105279
The file was modifiedllvm/utils/gn/secondary/llvm/lib/CodeGen/BUILD.gn
The file was addedllvm/lib/CodeGen/RemoveRedundantDebugValues.cpp
The file was modifiedllvm/test/CodeGen/X86/O0-pipeline.ll
The file was modifiedllvm/include/llvm/CodeGen/Passes.h
The file was modifiedllvm/lib/CodeGen/TargetPassConfig.cpp
The file was modifiedllvm/test/CodeGen/AArch64/O0-pipeline.ll
The file was modifiedllvm/test/CodeGen/ARM/O3-pipeline.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/llc-pipeline.ll
The file was modifiedllvm/test/CodeGen/X86/opt-pipeline.ll
The file was modifiedllvm/include/llvm/InitializePasses.h
The file was modifiedllvm/test/CodeGen/AMDGPU/ptr-arg-dbg-value.ll
The file was modifiedllvm/test/DebugInfo/MIR/Hexagon/live-debug-values-bundled-entry-values.mir
The file was modifiedllvm/test/CodeGen/PowerPC/non-debug-mi-search-frspxsrsp.ll
The file was modifiedllvm/test/DebugInfo/MIR/X86/multiple-param-dbg-value-entry.mir
The file was modifiedllvm/docs/SourceLevelDebugging.rst
The file was modifiedllvm/include/llvm/CodeGen/MachinePassRegistry.def
The file was addedllvm/test/DebugInfo/MIR/X86/remove-redundant-dbg-vals.mir
The file was modifiedllvm/test/CodeGen/AArch64/O3-pipeline.ll
The file was modifiedllvm/lib/CodeGen/CodeGen.cpp
The file was modifiedllvm/test/CodeGen/PowerPC/O3-pipeline.ll
The file was modifiedllvm/include/llvm/CodeGen/CodeGenPassBuilder.h
The file was modifiedllvm/lib/CodeGen/CMakeLists.txt
Commit d21772fa21de6a1c5d0f4792fbd175ff3d18c842 by alexshap
[lld][MachO] Code cleanup

Make use of ArgList::getLastArgValue. NFC.

Test plan: make check-lld-macho

Differential revision: https://reviews.llvm.org/D105452
The file was modifiedlld/MachO/Driver.cpp
Commit bdf31471c76b5ded9e8d5a039250c2a7ba7aead6 by gabor.marton
[Analyzer][solver] Add dump methods for (dis)equality classes.

This proved to be very useful during debugging.

Differential Revision: https://reviews.llvm.org/D103967
The file was modifiedclang/lib/StaticAnalyzer/Core/RangeConstraintManager.cpp
The file was addedclang/test/Analysis/expr-inspection-printState-diseq-info.c
The file was modifiedclang/test/Analysis/expr-inspection.c
The file was addedclang/test/Analysis/expr-inspection-printState-eq-classes.c
Commit 25ee55c0baff316d3a7b1d7d2830a168af3fc46a by spatel
[SLP] match logical and/or as reduction candidates

This has been a work-in-progress for a long time...we finally have all of
the pieces in place to handle vectorization of compare code as shown in:
https://llvm.org/PR41312

To do this (see PhaseOrdering tests), we converted SimplifyCFG and
InstCombine to the poison-safe (select) forms of the logic ops, so now we
need to have SLP recognize those patterns and insert a freeze op to make
a safe reduction:
https://alive2.llvm.org/ce/z/NH54Ah

We get the minimal patterns with this patch, but the PhaseOrdering tests
show that we still need adjustments to get the ideal IR in some or all of
the motivating cases.

Differential Revision: https://reviews.llvm.org/D105730
The file was modifiedllvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
The file was modifiedllvm/test/Transforms/PhaseOrdering/X86/vector-reductions-logical.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/reduction-logical.ll
Commit b18bda67915c67285c2b8d5fb88210f9a7436b8c by Tim Northover
ARM: reuse existing libcall global variable if possible.

If we try to create a new GlobalVariable on each iteration, the Module will
detect the name collision and "helpfully" rename later iterations by appending
".1" etc. But "___udivsi3.1" doesn't exist and we definitely don't want to try
to call it.

So instead check whether there's already a global with the right name in the
module and use that if so.
The file was modifiedllvm/lib/Target/ARM/ARMFastISel.cpp
The file was modifiedllvm/test/CodeGen/ARM/fast-isel-call.ll
Commit 56e6d4742e6909bd7d2db201cc5e0e3e77c6f282 by ty1208chiang
[docs] Update CMake cross compiling guide link

The CMake community Wiki has been moved to the [[ https://gitlab.kitware.com/cmake/community/wikis/home | Kitware GitLab Instance ]].
Also, the original anchor for `Information how to set up various cross compiling toolchains` section might not work as expected. The original content is now being collapsed, so browser won't navigate to the right section directly.

Hence, I think it might be better to provide the section name instead of `this section` with link to help readers find the right section by themselves.

Reviewed By: void

Differential Revision: https://reviews.llvm.org/D104996
The file was modifiedllvm/docs/CMake.rst
Commit b70dde522d50c4aa5471ed7270fb9191c6b35424 by springerm
[mlir][linalg] Fix typo in ExtractSliceOfPadTensorSwapPattern

Differential Revision: https://reviews.llvm.org/D105607
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/Transforms.cpp
The file was modifiedmlir/test/Dialect/Linalg/subtensor-of-padtensor.mlir
Commit fe52296a3433aebc95fadb6f0b187bc3433c9058 by Jinsong Ji
[AIX] Enable dollar sign as PC in inlineasm

$ is used as PC for PowerPC inlineasm, ELF use it,
enable it for AIX XCOFF as well.

Reviewed By: #powerpc, amyk, nemanjai

Differential Revision: https://reviews.llvm.org/D105956
The file was modifiedllvm/lib/Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.cpp
The file was addedllvm/test/MC/PowerPC/dollarpc.s
The file was addedllvm/test/CodeGen/PowerPC/inline-asm-dollarpc.ll
Commit 67002b5f20c2c4c9bd5e89f79077ae8d6e165aae by arnamoy.bhattacharyya
[flang][OpenMP] Fix semantic check of test case in taskloop simd construct

The following semantic check is removed in OpenMP Version 5.0:
```
Taskloop simd construct restrictions: No reduction clause can be specified.
```

Also fix several typos.

Reviewed By: kiranchandramohan

Differential Revision: https://reviews.llvm.org/D105874
The file was modifiedflang/test/Semantics/omp-taskloop-simd01.f90
The file was modifiedflang/lib/Semantics/check-omp-structure.cpp
The file was modifiedflang/test/Semantics/omp-clause-validity01.f90
Commit 93dc73b1e0f31c712e5b8bbac14491ce55c414ad by yitzhakm
[Lexer] Fix bug in `makeFileCharRange` called on split tokens.

When the end loc of the specified range is a split token, `makeFileCharRange`
does not process it correctly.  This patch adds proper support for split tokens.

Differential Revision: https://reviews.llvm.org/D105365
The file was modifiedclang/lib/Lex/Lexer.cpp
The file was modifiedclang/unittests/Lex/LexerTest.cpp
Commit 77396bbc981a96e22eae9f0bc79a7d55316501c1 by Louis Dionne
[runtimes] NFCI: Drop intermediate CMake variable TARGET_TRIPLE

We might as well use the various XXX_TARGET_TRIPLE variables directly.
The file was modifiedlibunwind/CMakeLists.txt
The file was modifiedlibcxxabi/test/CMakeLists.txt
The file was modifiedlibcxx/CMakeLists.txt
The file was modifiedlibcxx/lib/abi/CMakeLists.txt
The file was modifiedlibcxx/test/CMakeLists.txt
The file was modifiedlibcxxabi/CMakeLists.txt
The file was modifiedlibunwind/test/CMakeLists.txt
Commit 2eb50baf059648214cb1c624b5269978a62e86a1 by a.bataev
[SLP]Workaround for InsertSubVector cost.

The cost of the InsertSubvector shuffle kind cost is not complete and
may end up with just extracts + inserts costs in many cases. Added
a workaround to represent it as a generic PermuteSingleSrc, which is
still pessimistic but better than InsertSubvector.

Differential Revision: https://reviews.llvm.org/D105827
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/alternate-calls.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/alternate-int-inseltpoison.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/cmp_commute-inseltpoison.ll
The file was modifiedllvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/cmp_commute.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/pr47629.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/resched.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/AArch64/accelerate-vector-functions.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/alternate-int.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/pr47629-inseltpoison.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/vec_list_bias-inseltpoison.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/vec_list_bias.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/AArch64/accelerate-vector-functions-inseltpoison.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/alternate-calls-inseltpoison.ll
Commit 372bb082524de3db9361ff7b5c1992774f081276 by jay.foad
[AMDGPU] Check llc-pipeline.ll with -match-full-lines -strict-whitespace

This prevents breaking the indentation that shows the structure of the
pass managers.

Differential Revision: https://reviews.llvm.org/D105891
The file was modifiedllvm/test/CodeGen/AMDGPU/llc-pipeline.ll
Commit aefd6c615c91a2af89fa3697cf1813aac0f622de by aaron
Combine two diagnostics into one and correct grammar

The anonymous and non-anonymous bit-field diagnostics are easily
combined into one diagnostic. However, the diagnostic was missing a
"the" that is present in the almost-identically worded
warn_bitfield_width_exceeds_type_width diagnostic, hence the changes to
test cases.
The file was modifiedclang/include/clang/Basic/DiagnosticSemaKinds.td
The file was modifiedclang/test/SemaCXX/ms_wide_bitfield.cpp
The file was modifiedclang/test/SemaObjC/class-bitfield.m
The file was modifiedclang/test/Sema/bitfield.c
The file was modifiedclang/lib/Sema/SemaDecl.cpp
Commit eac167073924e2a27f26a8931b038c1e18cdb08d by sander.desmalen
[CostModel][AArch64] Make loads/stores of <vscale x 1 x eltty> invalid.

At the moment, <vscale x 1 x eltty> are not yet fully handled by the
code-generator, so to avoid vectorizing loops with that VF, we mark the
cost for these types as invalid.
The reason for not adding a new "TTI::getMinimumScalableVF" is because
the type is supposed to be a type that can be legalized. It partially is,
although the support for these types need some more work.

Reviewed By: paulwalker-arm, dmgreen

Differential Revision: https://reviews.llvm.org/D103882
The file was modifiedllvm/test/Transforms/LoopVectorize/AArch64/sve-inductions.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
The file was modifiedllvm/test/Analysis/CostModel/AArch64/masked_ldst.ll
The file was modifiedllvm/test/Analysis/CostModel/AArch64/sve-gather.ll
The file was modifiedllvm/test/Analysis/CostModel/AArch64/sve-scatter.ll
The file was modifiedllvm/test/Analysis/CostModel/AArch64/sve-ldst.ll
Commit 47269da5d83e079a565439cbbacd4bb119ed0aff by Matthew.Arsenault
GlobalISel: Handle lowering non-power-of-2 extloads
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-global.mir
The file was modifiedllvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-global.mir
Commit efaf3099c8cec1954831ee28a2f75a72096f50eb by sander.desmalen
[LV] Print remark when loop cannot be vectorized due to invalid costs.

This patch emits remarks for instructions that have invalid costs for
a given set of vectorization factors. Some example output:

  t.c:4:19: remark: Instruction with invalid costs prevented vectorization at VF=(vscale x 1): load
      dst[i] = sinf(src[i]);
                    ^
  t.c:4:14: remark: Instruction with invalid costs prevented vectorization at VF=(vscale x 1, vscale x 2, vscale x 4): call to llvm.sin.f32
      dst[i] = sinf(src[i]);
               ^
  t.c:4:12: remark: Instruction with invalid costs prevented vectorization at VF=(vscale x 1): store
      dst[i] = sinf(src[i]);
             ^

Reviewed By: fhahn, kmclaughlin

Differential Revision: https://reviews.llvm.org/D105806
The file was modifiedllvm/test/Transforms/LoopVectorize/AArch64/scalable-call.ll
The file was modifiedllvm/lib/Transforms/Vectorize/LoopVectorize.cpp
Commit b155c871f2e21beed45d15a25f7c84fb4f0c1d93 by spatel
[InstCombine] add tests for icmp with constant offset and no-wrap flags; NFC
The file was modifiedllvm/test/Transforms/InstCombine/icmp-add.ll
Commit ca6e117d86341682e20025f204294c0ca78c355e by spatel
[InstCombine] reorder icmp with offset folds for better results

This set of folds was added recently with:
c7b658aeb526
0c400e895306
40b752d28d95

...and I noted that this wasn't likely to fire in code derived
from C/C++ source because of nsw in particular. But I didn't
notice that I had placed the code above the no-wrap block
of transforms.

This is likely the cause of regressions noted from the previous
commit because -- as shown in the test diffs -- we may have
transformed into a compare with an arbitrary constant rather
than a simpler signbit test.
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
The file was modifiedllvm/test/Transforms/InstCombine/icmp-add.ll
Commit 338314f9c26d4594d49fdd3a7656d71c77255c54 by david.green
[ARM] Lower v16i8 -> i64 VMLA reductions.

MVE does not have a VMLALV instruction that can perform v16i8 -> i64
reductions, like it does for v8i16->i64 and v4i32->i64 reductions. That
means that the pattern to create them will be spilt up by type
legalization, creating a lot of instructions.

This extends the patterns for matching i64 reductions a little to handle
the v16i8->i64 case. We need to turn them into a pair of v8i16->i64
VMLALVs that each perform half of the reduction and are summed together
(so the later is a VMLALVA). The order of the lanes does not matter for
the reduction so we generate a MVEEXT for the extension, that will
either be folded into a extending load or can be optimized to a
VREV/VMOVL. Some of the resulting codegen isn't optimal, but will be
improved in a later patch.

Differential Revision: https://reviews.llvm.org/D105680
The file was modifiedllvm/lib/Target/ARM/ARMISelLowering.cpp
The file was modifiedllvm/test/CodeGen/Thumb2/mve-vecreduce-mla.ll
Commit 7de2173c2a4c45711831cfee3ccf53690c76ff07 by i
[ELF] --fortran-common: prefer STB_WEAK to COMMON

The ELF specification says "The link editor honors the common definition and
ignores the weak ones." GNU ld and our Symbol::compare follow this, but the
--fortran-common code (D86142) made a mistake on the precedence.

Fixes https://bugs.llvm.org/show_bug.cgi?id=51082

Reviewed By: peter.smith, sfertile

Differential Revision: https://reviews.llvm.org/D105945
The file was modifiedlld/ELF/InputFiles.cpp
The file was modifiedlld/test/ELF/common-archive-lookup.s
Commit 122b0220fd45ee71acda912b0b712bb8edb6ba46 by tlively
[WebAssembly] Remove datalayout strings from llc tests

The data layout strings do not have any effect on llc tests and will become
misleadingly out of date as we continue to update the canonical data layout, so
remove them from the tests.

Differential Revision: https://reviews.llvm.org/D105842
The file was modifiedllvm/test/CodeGen/WebAssembly/simd-concat.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/snan_literal.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/irreducible-cfg-exceptions.ll
The file was modifiedllvm/test/MC/WebAssembly/array-fill.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/simd-sext-inreg.ll
The file was modifiedllvm/test/MC/WebAssembly/data-symbol-in-text-section.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/offset-folding.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/main-no-args.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/mem-intrinsics.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/reference-types.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/divrem-constant.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/memory-addr32.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/clear-cache.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/tailcall.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/atomic-mem-consistency.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/multivalue-stackify.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/fast-isel-pr47040.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/signext-zeroext.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/function-bitcasts.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/tls-general-dynamic.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/switch-in-loop.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/simd-select.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/f16.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/masked-shifts.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/fast-isel-call-indirect64.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/call-pic.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/simd-load-zero-offset.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/PR40172.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/debugtest-opt.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/simd-arith.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/target-features-tls.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/simd-shuffle-bitcast.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/fast-isel-noreg.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/target-features.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/load-store-static.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/multivalue-stackify.py
The file was modifiedllvm/test/CodeGen/WebAssembly/reg-stackify.ll
The file was modifiedllvm/test/MC/WebAssembly/comdat-sections.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/copysign-casts.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/offset-atomics.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/main-with-args.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/mutable-globals.ll
The file was modifiedllvm/test/MC/WebAssembly/function-alias.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/simd-intrinsics.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/simd-load-lane-offset.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/call.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/store.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/vtable.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/cfg-stackify.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/func.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/simd-load-splat.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/swiftcc.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/i64-load-store-alignment.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/select.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/export-name.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/function-bitcasts-varargs.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/inline-asm-roundtrip.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/eh-lsda.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/custom-sections.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/pr47375.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/signext-arg.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/comparisons-i64.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/unreachable.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/call-indirect.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/simd-comparisons.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/ident.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/immediates.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/atomic-pic.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/weak.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/return-address-emscripten.ll
The file was modifiedllvm/test/MC/WebAssembly/debug-byval-struct.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/conv.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/globl.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/atomic-fence.mir
The file was modifiedllvm/test/CodeGen/WebAssembly/simd-extending.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/multivalue.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/inline-asm.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/i128-returned.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/offset.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/unused-argument.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/conv-trap.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/i64.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/tls-local-exec.ll
The file was modifiedllvm/test/MC/WebAssembly/assembler-binary.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/dead-vreg.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/main-declaration.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/negative-base-reg.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/multi-return.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/simd-scalar-to-vector.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/cfg-stackify-eh.mir
The file was modifiedllvm/test/CodeGen/WebAssembly/bulk-memory.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/address-offsets.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/lower-em-sjlj-sret.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/fast-isel-i256.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/legalize.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/lower-global-dtors.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/cfg-stackify-eh.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/inline-asm-m.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/atomic-rmw.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/atomic-fence.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/f64.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/irreducible-cfg.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/global_dtors.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/stack-insts.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/i32.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/PR40267.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/simd-unsupported.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/PR41149.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/exception.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/simd-extended-extract.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/return-void.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/dbgvalue.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/simd-reductions.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/return-int32.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/PR41841.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/bulk-memory64.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/memory-addr64.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/muloti4.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/comparisons-f64.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/indirect-import.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/simd-offset.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/fast-isel-i24.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/simd-conversions.ll
The file was modifiedllvm/test/MC/WebAssembly/file-headers.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/simd-nested-shuffles.ll
The file was modifiedllvm/test/MC/WebAssembly/debug-localvar.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/comparisons-i32.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/function-pointer64.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/lower-em-ehsjlj-multi-return.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/offset-fastisel.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/comparisons-f32.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/simd-load-store-alignment.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/simd.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/exception.mir
The file was modifiedllvm/test/CodeGen/WebAssembly/main-three-args.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/simd-bitcasts.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/f32.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/simd-build-pair.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/vector-sdiv.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/returned.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/import-module.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/i32-load-store-alignment.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/simd-illegal-signext.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/umulo-i64.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/irreducible-cfg.mir
The file was modifiedllvm/test/CodeGen/WebAssembly/function-info.mir
The file was modifiedllvm/test/CodeGen/WebAssembly/frem.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/i128.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/fast-isel-br-i1.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/signext-inreg.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/switch-unreachable-default.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/phi.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/simd-nonconst-sext.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/libcalls.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/simd-shift-complex-splats.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/debugtrap.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/byval.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/return-address-unknown.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/fast-isel.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/simd-build-vector.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/global.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/null-streamer.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/implicit-def.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/lower-em-ehsjlj-options.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/unsupported-function-bitcasts.ll
Commit 5099e0156818665ae5381337f64ca68d659e0556 by Louis Dionne
[runtimes] Inherit the TARGET_TRIPLE that may be set by LLVM
The file was modifiedlibunwind/CMakeLists.txt
The file was modifiedlibcxx/CMakeLists.txt
The file was modifiedlibcxxabi/CMakeLists.txt
Commit 970e0900104d6f67a9c15fa9c913cf3eeba5d06a by tlively
[WebAssembly] Codegen for v128.loadX_lane instructions

Replace the experimental clang builtin and LLVM intrinsics for these
instructions with normal codegen patterns. Resolves PR50433.

Differential Revision: https://reviews.llvm.org/D105950
The file was modifiedllvm/test/CodeGen/WebAssembly/simd-load-store-alignment.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/simd-build-vector.ll
The file was modifiedllvm/include/llvm/IR/IntrinsicsWebAssembly.td
The file was modifiedclang/include/clang/Basic/BuiltinsWebAssembly.def
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
The file was modifiedllvm/test/CodeGen/WebAssembly/simd-load-lane-offset.ll
The file was modifiedclang/lib/Headers/wasm_simd128.h
The file was modifiedclang/test/Headers/wasm.c
The file was modifiedclang/lib/CodeGen/CGBuiltin.cpp
The file was modifiedclang/test/CodeGen/builtins-wasm.c
Commit 1e30bf8621cc123a7afba3246a36187c5ce3c836 by efriedma
[SelectionDAG] Add an overload of getStepVector that assumes step 1.

This is mostly a minor convenience, but the pattern seems frequent
enough to be worthwhile (and we'll probably add more uses in the
future).

Differential Revision: https://reviews.llvm.org/D105850
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
The file was modifiedllvm/include/llvm/CodeGen/SelectionDAG.h
Commit 9c2de2382197109388a25c9486f0e4408896d36e by Saleem Abdulrasool
Demangle: correct swift_async demangling for Microsoft scheme

The emission was corrected for the swift_async calling convention but
the demangling support was not.  This repairs the demangling support as
well.
The file was modifiedllvm/test/Demangle/ms-mangle.test
The file was modifiedllvm/lib/Demangle/MicrosoftDemangle.cpp
Commit 5e4b33fe9218703f0b29e2446159bcf4202d15fa by nikita.ppv
[Verifier] Improve incompatible attribute type check

A couple of attributes had explicit checks for incompatibility
with pointer types. However, this is already handled generically
by the typeIncompatible() check. We can drop these after adding
SwiftError to typeIncompatible().

However, the previous implementation of the check prints out all
attributes that are incompatible with a given type, even though
those attributes aren't actually used. This has the annoying
result that the error message changes every time a new attribute
is added to the list. Improve this by explicitly finding which
attribute isn't compatible and printing just that.
The file was modifiedllvm/lib/IR/Attributes.cpp
The file was modifiedllvm/lib/IR/Verifier.cpp
The file was modifiedllvm/test/Verifier/noundef.ll
The file was modifiedllvm/test/Verifier/sret.ll
The file was modifiedllvm/test/Verifier/preallocated-invalid.ll
The file was modifiedllvm/test/Verifier/byval-1.ll
The file was modifiedllvm/test/Verifier/byref.ll
The file was modifiedllvm/test/Verifier/align.ll
The file was modifiedllvm/test/Verifier/inalloca1.ll
The file was modifiedllvm/test/Verifier/swifterror.ll
Commit fbab8e6f10dd982281717b5c2b0ce7609ee1ccec by joker.eph
Remove uses of deprecated target AllPassesAndDialectsNoRegistration in Bazel (NFC)

It was an alias for a long time.
The file was modifiedutils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Commit 14362bf1b2589f8a769709be599f24ab7eee6d6e by Vitaly Buka
[scudo] Don't enabled MTE for small alignment

Differential Revision: https://reviews.llvm.org/D105954
The file was modifiedcompiler-rt/lib/scudo/standalone/memtag.h
Commit 31b8f400066c3998edc5650300301c1219468ef2 by david.green
[ARM] Move add(VMLALVA(A, X, Y), B) to VMLALVA(add(A, B), X, Y)

For i64 reductions we currently try and convert add(VMLALV(X, Y), B) to
VMLALVA(B, X, Y), incorporating the addition into the VMLALVA. If we
have an add of an existing VMLALVA, this patch pushes the add up above
the VMLALVA so that it may potentially be simplified further, for
example being folded into another VMLALV.

Differential Revision: https://reviews.llvm.org/D105686
The file was modifiedllvm/test/CodeGen/Thumb2/mve-vecreduce-mla.ll
The file was modifiedllvm/lib/Target/ARM/ARMISelLowering.cpp
Commit a4856c739c570d5115d0b7646a58b918890d37d4 by lebedev.ri
[NFC][PhaseOrdering] Add test for the lack of CSE after SimplifyCFG (PR51092)
The file was addedllvm/test/Transforms/PhaseOrdering/X86/earlycse-after-simplifycfg-two-entry-phi-node-folding.ll
Commit cd88a01cb8e90b5eae9f8bde82ff362b222a61c4 by nikita.ppv
[Attributes] Use single method to fetch type from AttributeSet (NFC)

While it is nice to have separate methods in the public AttributeSet
API, we can fetch the type from the internal AttributeSetNode
using a generic API for all type attribute kinds.
The file was modifiedllvm/lib/IR/Attributes.cpp
The file was modifiedllvm/lib/IR/AttributeImpl.h
Commit dfbfc277b2a45d2cec21763fb1a8be58cd538df8 by lebedev.ri
[NFC] Drop redundant check prefixes in newly added test file
The file was modifiedllvm/test/Transforms/PhaseOrdering/X86/earlycse-after-simplifycfg-two-entry-phi-node-folding.ll
Commit 850b57c5fbe7b44d18c9667bb31adfbe307453a6 by Louis Dionne
[runtimes] Bring back TARGET_TRIPLE

This commit reverts 5099e01568 and 77396bbc98, which broke the build
in various ways. I'm reverting until I can investigate, since that
change appears to be way more subtle than it seemed.
The file was modifiedlibcxxabi/test/CMakeLists.txt
The file was modifiedlibcxx/test/CMakeLists.txt
The file was modifiedlibcxxabi/CMakeLists.txt
The file was modifiedlibunwind/test/CMakeLists.txt
The file was modifiedlibcxx/CMakeLists.txt
The file was modifiedlibcxx/lib/abi/CMakeLists.txt
The file was modifiedlibunwind/CMakeLists.txt
Commit 8461995d35a417b4d161112ded0c0980280c5f64 by gcmn
[Bazel] Uniformly export all MLIR td files

CMake would have no restrictions on this and the custom list is a pain
to maintain.

Reviewed By: jpienaar

Differential Revision: https://reviews.llvm.org/D106003
The file was modifiedutils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Commit 4fd0addb68f603112171a79353bc2a0f1d148183 by llvm-dev
[SLP] Fix case of variable name. NFCI.
The file was modifiedllvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Commit 3bda1c4e22cdf54f899f0330a98213337df9b3d4 by i
[docs] Fix :option:`--file-header` reference in llvm-readelf.rst after D105532
The file was modifiedllvm/docs/CommandGuide/llvm-readelf.rst
Commit ba2690b17b9e463b80a1d6c675e3d04fc2974083 by a.bataev
[SLP][NFC]Fix variables names, NFC.
The file was modifiedllvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Commit 76b7d3432e38bb7690c3bbd4940786b5cb751b95 by Stanislav.Mekhanoshin
[AMDGPU] Add TII::isIgnorableUse() to allow VOP rematerialization

Any def of EXEC prevents rematerialization of any VOP instruction
because of the physreg use. Create a callback to check if the
physreg use can be ingored to allow rematerialization.

Differential Revision: https://reviews.llvm.org/D105836
The file was modifiedllvm/test/CodeGen/AMDGPU/remat-vop.mir
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.h
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.cpp
The file was modifiedllvm/include/llvm/CodeGen/TargetInstrInfo.h
The file was modifiedllvm/test/CodeGen/AMDGPU/remat-sop.mir
The file was modifiedllvm/lib/CodeGen/LiveRangeEdit.cpp
Commit e75a2dfe209d9cc68e4d9813a38441c45d51d8bb by listmail
[tests] Stablize tests for possible change in deref semantics

There's a potential change in dereferenceability attribute semantics in the nearish future.  See llvm-dev thread "RFC: Decomposing deref(N) into deref(N) + nofree" and D99100 for context.

This change simply adds appropriate attributes to tests to keep transform logic exercised under both old and new/proposed semantics.  Note that for many of these cases, O3 would infer exactly these attributes on the test IR.

This change handles the idiomatic pattern of a dereferenceable object being passed to a call which can not free that memory.  There's a couple other tests which need more one-off attention, they'll be handled in another change.
The file was modifiedllvm/test/Transforms/MergeICmps/X86/pair-int32-int32.ll
The file was modifiedllvm/test/Transforms/MergeICmps/X86/gep-references-bb.ll
The file was modifiedllvm/test/Transforms/JumpThreading/guards.ll
The file was modifiedllvm/test/Transforms/SimplifyCFG/X86/SpeculativeExec.ll
The file was modifiedllvm/test/Transforms/InstCombine/select.ll
The file was modifiedllvm/test/Transforms/MergeICmps/X86/multiple-blocks-does-work.ll
The file was modifiedllvm/test/Transforms/VectorCombine/X86/load.ll
The file was modifiedllvm/test/Transforms/LICM/hoist-deref-load.ll
The file was modifiedllvm/test/CodeGen/X86/licm-dominance.ll
The file was modifiedllvm/test/Transforms/GVN/PRE/load-pre-licm.ll
The file was modifiedllvm/test/Transforms/GVN/PRE/pre-load.ll
The file was modifiedllvm/test/Transforms/VectorCombine/X86/load-inseltpoison.ll
The file was modifiedllvm/test/Transforms/MergeICmps/X86/split-block-does-work.ll
The file was modifiedllvm/test/Transforms/GVN/loadpre-context.ll
The file was modifiedllvm/test/Transforms/InstCombine/strcmp-memcmp.ll
The file was modifiedllvm/test/CodeGen/X86/hoist-invariant-load.ll
The file was modifiedllvm/test/CodeGen/X86/memcmp-mergeexpand.ll
The file was modifiedllvm/test/Transforms/MergeICmps/X86/entry-block-shuffled.ll
The file was modifiedllvm/test/Transforms/MemCpyOpt/callslot_deref.ll
The file was modifiedllvm/test/Transforms/InstCombine/call-guard.ll
The file was modifiedllvm/test/Analysis/ValueTracking/deref-bitcast-of-gep.ll
The file was modifiedllvm/test/Transforms/MergeICmps/X86/int64-and-ptr.ll
The file was modifiedllvm/test/CodeGen/X86/load-partial.ll
The file was modifiedllvm/test/Transforms/InstCombine/masked_intrinsics-inseltpoison.ll
The file was modifiedllvm/test/Transforms/InstCombine/masked_intrinsics.ll
The file was modifiedllvm/test/Transforms/MergeICmps/X86/alias-merge-blocks.ll
The file was modifiedllvm/test/Transforms/TailCallElim/reorder_load.ll
Commit d37689e9ababe4badbc0132950425d8f3434a5b8 by martin
[libcxx] [test] Remove a LIBCXX-WINDOWS-FIXME in trivial_abi/unique_ptr_ret

This is the same thing that was clarified in D105906 for weak_ptr_ret.

Differential Revision: https://reviews.llvm.org/D105965
The file was modifiedlibcxx/test/libcxx/memory/trivial_abi/unique_ptr_ret.pass.cpp
Commit b86ddfdb9a80f2343510e07209ceda59d72972e3 by listmail
Global variables with strong definitions cannot be freed

With the current deref semantics, this is redundant - since we assume that anything which is dereferenceable (ever) can't be freed - but it becomes neccessary for the deref-at-point semantics.

Testing wise, this is covered by test/CodeGen/X86/hoist-invariant-load.ll when -use-dereferenceable-at-point-semantics is active.  I didn't bother duplicating the command line since a) it's an in-development mode, and b) the change is pretty obvious.
The file was modifiedllvm/lib/IR/Value.cpp
Commit 7b47de774fd43eb5be7aee86c6f8c15999295b36 by nicolas.vasilache
[mlir] NFC - Add AffineMap::replace variant with dim/symbol inference
The file was modifiedmlir/include/mlir/IR/AffineMap.h
The file was modifiedmlir/lib/IR/AffineMap.cpp
Commit e23dce6c974477d3476bee5256a83a9aaea8eae4 by Steven Wu
[Support] Get correct number of physical cores on Apple Silicon

Fix a bug that `computeHostNumPhysicalCores` is fallback to default
unknown when building for Apple Silicon macs.

rdar://80533675

Reviewed By: arphaman

Differential Revision: https://reviews.llvm.org/D106012
The file was modifiedllvm/lib/Support/Host.cpp
Commit 1e4a417ee639b867b783e52949d22c1965ab25d0 by Jonas Devlieghere
[lldb] Always call DestroyImpl from Process::Finalize

Always destroy the process, regardless of its private state. This will
call the virtual function DoDestroy under the hood, giving our derived
class a chance to do the necessary tear down, including what to do when
the private state is eStateExited.

Differential revision: https://reviews.llvm.org/D106004
The file was modifiedlldb/source/Target/Process.cpp
Commit de448c0a9e5088979526e2e67152fe547ae4ccf0 by Jonas Devlieghere
[lldb] Make TargetList iterable (NFC)

Make it possible to iterate over the TargetList.

Differential revision: https://reviews.llvm.org/D105914
The file was modifiedlldb/source/Core/Debugger.cpp
The file was modifiedlldb/include/lldb/Target/TargetList.h
Commit ac500fd18f0615c45d9d127bfb576ffa1e11425a by Vitaly Buka
[asan][clang] Add flag to outline instrumentation

Summary This option can be used to reduce the size of the
binary. The trade-off in this case would be the run-time
performance.

Reviewed By: vitalybuka

Differential Revision: https://reviews.llvm.org/D105726
The file was modifiedclang/include/clang/Driver/Options.td
The file was modifiedclang/docs/AddressSanitizer.rst
The file was modifiedclang/lib/Driver/SanitizerArgs.cpp
The file was modifiedclang/include/clang/Driver/SanitizerArgs.h
The file was modifiedclang/test/Driver/fsanitize.c
The file was modifiedclang/docs/UsersManual.rst
The file was addedclang/test/CodeGen/asan-use-callbacks.cpp
Commit 7e496c29e2bc85e5b769e0175ca9637dbff5615a by listmail
[tests] Stablize tests for possible change in deref semantics

This is conceptually part of e75a2dfe.  This file contains both tests whose results don't change (with the right attributes added), and tests which fundementally regress with the current proposal.  Doing the update took some care, thus the seperate change.

Here's the e75a2dfe context repeated:

There's a potential change in dereferenceability attribute semantics in the nearish future.  See llvm-dev thread "RFC: Decomposing deref(N) into deref(N) + nofree" and D99100 for context.

This change simply adds appropriate attributes to tests to keep transform logic exercised under both old and new/proposed semantics.  Note that for many of these cases, O3 would infer exactly these attributes on the test IR.

This change handles the idiomatic pattern of a dereferenceable object being passed to a call which can not free that memory.  There's a couple other tests which need more one-off attention, they'll be handled in another change.
The file was modifiedllvm/test/Analysis/BasicAA/dereferenceable.ll
Commit df538fdaa985e7e64a572dd84b878c562899e5e8 by nicolas.vasilache
[mlir][affine] Add single result affine.min/max -> affine.apply canonicalization.

Differential Revision: https://reviews.llvm.org/D106014
The file was modifiedmlir/test/Dialect/Affine/canonicalize.mlir
The file was modifiedmlir/lib/Dialect/Affine/IR/AffineOps.cpp
Commit 0e49c54a8cbd3e779e5526a5888c683c01cc3c50 by jonathan_roelofs
[AArch64] Fix selection of G_UNMERGE <2 x s16>

Differential revision: https://reviews.llvm.org/D106007
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/select-unmerge.mir
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
Commit 5366de7375e653998ff80c3c6cbdfa4f9b9046e3 by aeubanks
[SimpleLoopUnswitch] Don't non-trivially unswitch loops with catchswitch exits

SplitBlock() can't handle catchswitch.

Fixes PR50973.

Reviewed By: aheejin

Differential Revision: https://reviews.llvm.org/D105672
The file was addedllvm/test/Transforms/SimpleLoopUnswitch/catchswitch.ll
The file was modifiedllvm/lib/Transforms/Utils/BasicBlockUtils.cpp
The file was modifiedllvm/lib/Transforms/Scalar/SimpleLoopUnswitch.cpp
Commit d3816ef042d7506e154fb708456147a11264895c by aeubanks
Precommit test for D106017
The file was modifiedllvm/test/Transforms/InstCombine/malloc-free-delete.ll
Commit 7cb25f53875e5490bccaf297accd34b7331cfb8b by dschuff
[llvm-strip][WebAssembly] Support strip flags

Summary:
Add support for the basic section stripping (and keeping) flags for wasm:
strip with no flags, --strip-all, --strip-debug,
--only-section, --keep-section, and --only-keep-debug.

Factor section removal into a function and use a predicate chain like
the ELF implementation.

Reviewers: jhenderson, sbc100

Differential Revision: https://reviews.llvm.org/D73820
The file was modifiedllvm/tools/llvm-objcopy/wasm/WasmObjcopy.cpp
The file was addedllvm/test/tools/llvm-objcopy/wasm/basic-keep.test
The file was addedllvm/test/tools/llvm-objcopy/wasm/basic-only-section.test
The file was modifiedllvm/tools/llvm-objcopy/ConfigManager.cpp
The file was addedllvm/test/tools/llvm-objcopy/wasm/strip-debug.test
The file was addedllvm/test/tools/llvm-objcopy/wasm/strip-reloc.test
The file was addedllvm/test/tools/llvm-objcopy/wasm/only-keep-debug.test
The file was addedllvm/test/tools/llvm-objcopy/wasm/basic-strip.test
The file was addedllvm/test/tools/llvm-objcopy/wasm/strip-all.test
Commit 7e29e57917a9ecb8f1b07aa2d99b0fbea91cda61 by llvm-project
[Polly] Fix misleading debug message. NFC.

The number of parameters can be the reason for aliasing checks not being
generated, but most of the time it for other reasons.
The file was modifiedpolly/lib/Analysis/ScopBuilder.cpp
Commit d1116697be059350a5b04d1af29e2d454afda746 by wolfgang_pieb
[ARM] Fix RELA relocations for 32bit ARM.

RELA relocations for 32 bit ARM ignored the addend. Some tools generate
them instead of REL type relocations. This fixes PR50473.

    Reviewed By: MaskRay, peter.smith

    Differential Revision: https://reviews.llvm.org/D105214
The file was modifiedllvm/lib/Object/RelocationResolver.cpp
The file was addedllvm/test/DebugInfo/ARM/dwarfdump-rela.yaml
Commit 3bf101f34cd466f103af00c764dc1cddb6eb14a6 by aeubanks
[docs][OpaquePtr] Remove finished task
The file was modifiedllvm/docs/OpaquePointers.rst
Commit 58494c856a15f5b0e886c7baf5d505ac6c05dfe5 by owenca
[clang-format] Make BreakAfterReturnType work with K&R C functions

This fixes PR50999.

Differential Revision: https://reviews.llvm.org/D105964
The file was modifiedclang/unittests/Format/FormatTest.cpp
The file was modifiedclang/lib/Format/TokenAnnotator.cpp
Commit 0c7a4870c5b63935b7f0c7cbc380b497341dd203 by georgios.rokos
[libomptarget] Keep the Shadow Pointer Map up-to-date

D105812 introduced a regression where if a PTR_AND_OBJ entry was mapped on the device, then the OBJ was deallocated and then reallocated at a different address, the Shadow Pointer Map would still contain an entry for the PTR but pointing to the old address. This caused test `env/base_ptr_ref_count.c` to fail.

Differential Revision: https://reviews.llvm.org/D105947
The file was modifiedopenmp/libomptarget/src/omptarget.cpp
Commit 483df573135f2287bfd1a6d5c4d7196036f13cbd by Steven Wu
[Support] Turn on SupportTest for Apple Silicon

Follow up for D106012, turn on unittest for Host on Apple Silicon.

Reviewed By: dexonsmith

Differential Revision: https://reviews.llvm.org/D106020
The file was modifiedllvm/unittests/Support/Host.cpp
Commit d14310306827f5c0a4feb6a9ffddddcdfb24fcca by jonathan_roelofs
[GlobalOpt] Fix a miscompile when evaluating struct initializers.

The bug was that evaluateBitcastFromPtr attempts a narrowing to a struct's 0th
element of a store that covers other elements. While this is okay on the load
side, applying it to stores causes us to miss the writes to the additionally
covered elements.

rdar://79503568

Differential revision: https://reviews.llvm.org/D105838
The file was addedllvm/test/Transforms/GlobalOpt/store-struct-element.ll
The file was modifiedllvm/lib/Transforms/Utils/Evaluator.cpp
Commit 4a4229f70f815a0a83e8e226ec1718af693faf4d by tlively
[WebAssembly] Codegen for v128.storeX_lane instructions

Replace the experimental clang builtins and LLVM intrinsics for these
instructions with normal codegen patterns. Resolves PR50435.

Differential Revision: https://reviews.llvm.org/D106019
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
The file was modifiedllvm/test/CodeGen/WebAssembly/simd-load-lane-offset.ll
The file was modifiedllvm/test/CodeGen/WebAssembly/simd-build-pair.ll
The file was modifiedllvm/include/llvm/IR/IntrinsicsWebAssembly.td
The file was modifiedclang/test/CodeGen/builtins-wasm.c
The file was modifiedclang/test/Headers/wasm.c
The file was modifiedclang/lib/CodeGen/CGBuiltin.cpp
The file was modifiedclang/lib/Headers/wasm_simd128.h
The file was modifiedllvm/test/CodeGen/WebAssembly/simd-load-store-alignment.ll
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
The file was modifiedclang/include/clang/Basic/BuiltinsWebAssembly.def
Commit 9cfec72ffeec242783b70e792c50bd163dcf9dbb by zeratul976
[clang] Refactor AST printing tests to share more infrastructure

Differential Revision: https://reviews.llvm.org/D105457
The file was modifiedclang/unittests/AST/StmtPrinterTest.cpp
The file was modifiedclang/unittests/AST/DeclPrinterTest.cpp
The file was modifiedclang/unittests/AST/ASTPrint.h
The file was modifiedclang/unittests/AST/NamedDeclPrinterTest.cpp
Commit 4118858b4e4d072ac2ceef6cbc52088438781f39 by arthur.j.odwyer
[libc++] NFCI: Restore code duplication in wrap_iter, with test.

It turns out that D105040 broke `std::rel_ops`; we actually do need
both a one-template-parameter and a two-template-parameter version of
all the comparison operators, because if we have only the heterogeneous
two-parameter version, then `x > x` is ambiguous:

    template<class T, class U> int f(S<T>, S<U>) { return 1; }
    template<class T> int f(T, T) { return 2; }  // rel_ops
    S<int> s; f(s,s);  // ambiguous between #1 and #2

Adding the one-template-parameter version fixes the ambiguity:

    template<class T, class U> int f(S<T>, S<U>) { return 1; }
    template<class T> int f(T, T) { return 2; }  // rel_ops
    template<class T> int f(S<T>, S<T>) { return 3; }
    S<int> s; f(s,s);  // #3 beats both #1 and #2

We have the same problem with `reverse_iterator` as with `__wrap_iter`.
But so do libstdc++ and Microsoft, so we're not going to worry about it.

Differential Revision: https://reviews.llvm.org/D105894
The file was addedlibcxx/test/std/containers/iterator.rel_ops.compile.pass.cpp
The file was modifiedlibcxx/include/__iterator/wrap_iter.h
Commit a7749c3f79a8b0df9ffe8a814a13f9450981b292 by kuterdinel
[AMDGPU] Use update_test_checks.py script for annotate kernel features tests.

This patch makes the annotate kernel features tests use the update_tests_checks.py
script. Which makes it easy to update the tests.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D105864
The file was modifiedllvm/test/CodeGen/AMDGPU/uniform-work-group-prevent-attribute-propagation.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/direct-indirect-call.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/uniform-work-group-nested-function-calls.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/duplicate-attribute-indirect.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/addrspacecast-constantexpr.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/uniform-work-group-recursion-test.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/uniform-work-group-attribute-missing.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/annotate-kernel-features.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/uniform-work-group-propagate-attribute.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/uniform-work-group-test.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa-call.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/simple-indirect-call.ll
Commit ea469b08b847cef5f4c8187228f1e4bbf881706a by airlied
libclc: Add -cl-no-stdinc to clang flags on clang >=13

cf3ef15a6ec5e5b45c6c54e8fbe3769255e815ce ("[OpenCL] Add builtin
declarations by default.")
switched behaviour to include "opencl-c-base.h". We don't want or need
that for libclc so pass the flag to revert to old behaviour.

Fixes build since cf3ef15a6ec5e5b45c6c54e8fbe3769255e815ce

Reviewed By: tstellar

Differential Revision: https://reviews.llvm.org/D99794
The file was modifiedlibclc/CMakeLists.txt
Commit 090f007e3481863430e4443765769e73f8f40e5f by airlied
[OpenCL][NFC] opencl-c.h: reorder atomic operations

This just reorders the atomics, it doesn't change anything except their layout in the header.

This is a prep patch for adding some conditionals around these for CL3.0 but that patch is much easier to review if all the atomic operations are grouped together like this.

Reviewed By: Anastasia

Differential Revision: https://reviews.llvm.org/D105601
The file was modifiedclang/lib/Headers/opencl-c.h
Commit de79ba9f9a2de3d86fa3f44b57e147844b6f2625 by airlied
[OpenCL] opencl-c.h: CL3.0 generic address space

This is one of the easier pieces of adding CL3.0 support.

Reviewed By: Anastasia

Differential Revision: https://reviews.llvm.org/D105526
The file was modifiedclang/lib/Headers/opencl-c.h
Commit b9c3941cd61de1e1b9e4f3311ddfa92394475f4b by lkail
[PowerPC] Generate inlined quadword lock free atomic operations via AtomicExpand

This patch uses AtomicExpandPass to implement quadword lock free atomic operations. It adopts the method introduced in https://reviews.llvm.org/D47882, which expand atomic operations post RA to avoid spilling that might prevent LL/SC progress.

Reviewed By: jsji

Differential Revision: https://reviews.llvm.org/D103614
The file was modifiedllvm/test/CodeGen/PowerPC/O3-pipeline.ll
The file was addedllvm/test/CodeGen/PowerPC/atomics-i128.ll
The file was modifiedllvm/lib/Target/PowerPC/PPCInstr64Bit.td
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrInfo.td
The file was modifiedllvm/lib/CodeGen/AtomicExpandPass.cpp
The file was modifiedllvm/lib/Target/PowerPC/CMakeLists.txt
The file was modifiedllvm/lib/Target/PowerPC/PPCISelLowering.h
The file was modifiedllvm/include/llvm/IR/IntrinsicsPowerPC.td
The file was modifiedllvm/lib/Target/PowerPC/PPCSubtarget.h
The file was modifiedllvm/lib/Target/PowerPC/PPCISelLowering.cpp
The file was addedllvm/lib/Target/PowerPC/PPCExpandAtomicPseudoInsts.cpp
The file was modifiedllvm/lib/Target/PowerPC/PPCTargetMachine.cpp
The file was modifiedllvm/lib/Target/PowerPC/PPC.h
The file was modifiedllvm/lib/Target/PowerPC/PPC.td
Commit 8b426bdaf1686ed6fb3460b0f03a7ae6f23bce70 by llvmgnsyncbot
[gn build] Port b9c3941cd61d
The file was modifiedllvm/utils/gn/secondary/llvm/lib/Target/PowerPC/BUILD.gn
Commit 3469a8e03b51bdf3513c533d00206dccb624b102 by springerm
[mlir][linalg][NFC] Factor out tile generation in makeTiledShapes

Factor out the functionality into a new function, so that it can be used for creating PadTensorOp tiles.

Differential Revision: https://reviews.llvm.org/D105458
The file was modifiedmlir/lib/Dialect/Linalg/Utils/Utils.cpp
The file was modifiedmlir/include/mlir/Dialect/Linalg/Utils/Utils.h
Commit 5da010af9a058a70fc301b9c02d4ff370ab2f9a7 by springerm
[mlir][linalg] Add optional output operand to PadTensorOp

This optional operand will be used for tiling in a subsequent commit.

Differential Revision: https://reviews.llvm.org/D105459
The file was modifiedmlir/lib/Dialect/Linalg/IR/LinalgOps.cpp
The file was modifiedmlir/test/Dialect/Linalg/canonicalize.mlir
The file was modifiedmlir/test/Dialect/Linalg/invalid.mlir
The file was modifiedmlir/include/mlir/Dialect/Linalg/IR/LinalgOps.td
The file was modifiedmlir/test/Dialect/Linalg/roundtrip.mlir
Commit d624c1b50946b206b6274371fcc107f89d04a307 by springerm
[mlir][NFC] Move asOpFoldResult helper functions to StaticValueUtils

Differential Revision: https://reviews.llvm.org/D105602
The file was modifiedmlir/lib/Dialect/Linalg/IR/LinalgOps.cpp
The file was modifiedmlir/include/mlir/Dialect/Utils/StaticValueUtils.h
The file was modifiedmlir/lib/Dialect/Utils/StaticValueUtils.cpp
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/Transforms.cpp
Commit 4064b6a36348a0405a52b690437a1ae3004beec1 by springerm
[mlir][linalg] Tile PadTensorOp

Tiling can be enabled with `linalg-tile-pad-tensor-ops`. Only scf::ForOp can be generated at the moment.

Differential Revision: https://reviews.llvm.org/D105460
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/Tiling.cpp
The file was addedmlir/test/Dialect/Linalg/tile-pad-tensor-op.mlir
The file was modifiedmlir/lib/Dialect/Linalg/Utils/Utils.cpp
The file was modifiedmlir/test/Dialect/Linalg/tile-and-pad-tensors.mlir
Commit ffb139290d4bf8e46ae88758354bccb647a20f71 by springerm
[mlir][linalg] Fix Windows build

The build failure was introduced by D105458. (Linux builds were not affected.)

Differential Revision: https://reviews.llvm.org/D106029
The file was modifiedmlir/lib/Dialect/Linalg/Utils/Utils.cpp
Commit 318ce4ad927d129a2bf96c2c872f4d107c45bdef by springerm
[mlir][linalg] Improve codegen of ExtractSliceOfPadTensorSwapPattern

Generate simpler code in case low/high padding of the PadTensorOp is statically zero.

Differential Revision: https://reviews.llvm.org/D105529
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/Transforms.cpp
The file was modifiedmlir/test/Dialect/Linalg/subtensor-of-padtensor.mlir
Commit a0e02018beb81946397f577f14df09e4b3b675da by springerm
[mlir][linalg] Improve codegen when tiling PadTensor evenly

Produce simpler IR with more static type information and fewer affine expressions.

Differential Revision: https://reviews.llvm.org/D105530
The file was modifiedmlir/test/Dialect/Linalg/tile-pad-tensor-op.mlir
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/Tiling.cpp
The file was modifiedmlir/test/Dialect/Linalg/tile.mlir
Commit 70788052ac7ffba3c99b8ce644a3f9bf17eaa4a4 by czhengsz
[PowerPC][NFC] add testcase for update-form preparation with non-const increment
The file was modifiedllvm/test/CodeGen/PowerPC/loop-instr-prep-non-const-increasement.ll
Commit 58018858e887320e2432e2e00ace13273b8a1f29 by joker.eph
Defend early against operation created without a registered dialect

Reviewed By: rriddle

Differential Revision: https://reviews.llvm.org/D105961
The file was modifiedmlir/lib/IR/BuiltinTypes.cpp
The file was modifiedmlir/test/IR/invalid-unregistered.mlir
The file was modifiedmlir/test/CAPI/ir.c
The file was modifiedmlir/test/Dialect/PDL/invalid.mlir
The file was modifiedmlir/test/lit.cfg.py
The file was modifiedmlir/unittests/Pass/PassManagerTest.cpp
The file was modifiedmlir/lib/IR/Verifier.cpp
The file was modifiedmlir/test/IR/invalid-module-op.mlir
The file was modifiedmlir/lib/IR/Operation.cpp
The file was modifiedmlir/lib/Parser/Parser.cpp
The file was modifiedmlir/lib/IR/BuiltinAttributes.cpp
Commit ade190c5eabfb432fa273b354d371f84a312052b by kuterdinel
[Attributor] AACallEdges, Add a way to ask nonasm unknown callees

This patch adds a feature to AACallEdges AbstractAttribute that allows
users to ask if there is a unknown callee that isn't a inline assembly.
This feature is needed by some of it's users.

Reviewed By: jdoerfert

Differential Revision: https://reviews.llvm.org/D105992
The file was modifiedllvm/include/llvm/Transforms/IPO/Attributor.h
The file was modifiedllvm/lib/Transforms/IPO/AttributorAttributes.cpp
Commit 3e25ea709cf59bdd7f277501ab6737bac5b394f1 by joker.eph
Revert "Defend early against operation created without a registered dialect"

This reverts commit 58018858e887320e2432e2e00ace13273b8a1f29.

The Python bindings test are broken.
The file was modifiedmlir/test/Dialect/PDL/invalid.mlir
The file was modifiedmlir/test/CAPI/ir.c
The file was modifiedmlir/lib/IR/Operation.cpp
The file was modifiedmlir/test/IR/invalid-unregistered.mlir
The file was modifiedmlir/lib/IR/BuiltinTypes.cpp
The file was modifiedmlir/lib/IR/BuiltinAttributes.cpp
The file was modifiedmlir/unittests/Pass/PassManagerTest.cpp
The file was modifiedmlir/test/lit.cfg.py
The file was modifiedmlir/lib/Parser/Parser.cpp
The file was modifiedmlir/test/IR/invalid-module-op.mlir
The file was modifiedmlir/lib/IR/Verifier.cpp
Commit 5664c5e24ed42f58175428c5aeb53418b4ff76b0 by john.demme
[MLIR] [Python] Add `owner` to PyValue and fix its parent reference

Adds `owner` python call to `mlir.ir.Value`.

Assuming that `PyValue.parentOperation` is intended to be the value's owner, this fixes the construction of it from `PyOpOperandList`.

Reviewed By: stellaraccident

Differential Revision: https://reviews.llvm.org/D103853
The file was modifiedmlir/lib/Bindings/Python/IRCore.cpp
Commit 0f9e6451a836886f39137818c4f0cfd69ae31e62 by joker.eph
Defend early against operation created without a registered dialect

Reviewed By: rriddle

Differential Revision: https://reviews.llvm.org/D105961
The file was modifiedmlir/test/CAPI/ir.c
The file was modifiedmlir/lib/IR/Verifier.cpp
The file was modifiedmlir/unittests/Pass/PassManagerTest.cpp
The file was modifiedmlir/lib/IR/BuiltinAttributes.cpp
The file was modifiedmlir/test/lit.cfg.py
The file was modifiedmlir/lib/IR/Operation.cpp
The file was modifiedmlir/test/Dialect/PDL/invalid.mlir
The file was modifiedmlir/lib/IR/BuiltinTypes.cpp
The file was modifiedmlir/test/IR/invalid-unregistered.mlir
The file was modifiedmlir/test/IR/invalid-module-op.mlir
The file was modifiedmlir/test/python/dialects/python_test.py
The file was modifiedmlir/lib/Parser/Parser.cpp
Commit 8a1727ba51d262365b0d9fe10fef7e50da7022cd by yedeng.yd
[Coroutines] Run coroutine passes by default

This patch make coroutine passes run by default in LLVM pipeline. Now
the clang and opt could handle IR inputs containing coroutine intrinsics
without special options.
It should be fine. On the one hand, the coroutine passes seems to be stable
since there are already many projects using coroutine feature.
On the other hand, the coroutine passes should do nothing for IR who doesn't
contain coroutine intrinsic.

Test Plan: check-llvm

Reviewed by: lxfind, aeubanks

Differential Revision: https://reviews.llvm.org/D105877
The file was modifiedclang/test/CodeGenCoroutines/coro-always-inline.cpp
The file was modifiedllvm/test/Other/new-pm-defaults.ll
The file was modifiedllvm/test/Other/new-pm-thinlto-defaults.ll
The file was modifiedllvm/test/Other/new-pm-O0-defaults.ll
The file was modifiedclang/test/CodeGen/lto-newpm-pipeline.c
The file was modifiedllvm/test/Other/new-pm-thinlto-prelink-pgo-defaults.ll
The file was modifiedllvm/include/llvm-c/Transforms/PassBuilder.h
The file was modifiedclang/test/CodeGenCoroutines/coro-symmetric-transfer-01.cpp
The file was modifiedllvm/lib/Transforms/Utils/InlineFunction.cpp
The file was modifiedllvm/tools/opt/NewPMDriver.h
The file was modifiedclang/lib/CodeGen/BackendUtil.cpp
The file was modifiedllvm/tools/opt/NewPMDriver.cpp
The file was modifiedllvm/lib/Passes/PassBuilder.cpp
The file was modifiedllvm/lib/Passes/PassBuilderBindings.cpp
The file was modifiedllvm/test/Other/new-pm-thinlto-postlink-samplepgo-defaults.ll
The file was modifiedllvm/include/llvm/Passes/PassBuilder.h
The file was modifiedllvm/tools/opt/opt.cpp
The file was modifiedllvm/test/Other/new-pm-thinlto-postlink-pgo-defaults.ll
The file was modifiedllvm/test/Other/new-pm-thinlto-prelink-samplepgo-defaults.ll
Commit 53fed88159d00a340797cb4966dce471bc9fba21 by Tony.Tye
[AMDGPU] Reserve AMDGPU ELF e_flags machine 0x44

Reviewed By: rampitec

Differential Revision: https://reviews.llvm.org/D106034
The file was modifiedllvm/docs/AMDGPUUsage.rst
The file was modifiedllvm/include/llvm/BinaryFormat/ELF.h
Commit fa2daaeff82e3eb26fe7008715024f5bc11f7f1a by djtodoro
[2/2][RemoveRedundantDebugValues] Add a Pass that removes redundant DBG_VALUEs

This patch adds the forward scan for finding redundant DBG_VALUEs.

This analysis aims to remove redundant DBG_VALUEs by going forward
in the basic block by considering the first DBG_VALUE as a valid
until its first (location) operand is not clobbered/modified.
For example:

(1) DBG_VALUE $edi, !"var1", ...
(2) <block of code that does affect $edi>
(3) DBG_VALUE $edi, !"var1", ...
...
in this case, we can remove (3).

Differential Revision: https://reviews.llvm.org/D105280
The file was modifiedllvm/test/CodeGen/PowerPC/non-debug-mi-search-frspxsrsp.ll
The file was modifiedllvm/lib/CodeGen/RemoveRedundantDebugValues.cpp
The file was modifiedllvm/test/DebugInfo/MIR/X86/remove-redundant-dbg-vals.mir
Commit b0d38ad0bc254b887123cd063a5f0db30a80f938 by 1.int32
[clang][Analyzer] Add symbol uninterestingness to bug report.

`PathSensitiveBughReport` has a function to mark a symbol as interesting but
it was not possible to clear this flag. This can be useful in some cases,
so the functionality is added.

Reviewed By: NoQ

Differential Revision: https://reviews.llvm.org/D105637
The file was addedclang/unittests/StaticAnalyzer/BugReportInterestingnessTest.cpp
The file was modifiedclang/unittests/StaticAnalyzer/Reusables.h
The file was modifiedclang/include/clang/StaticAnalyzer/Core/BugReporter/BugReporter.h
The file was modifiedclang/lib/StaticAnalyzer/Core/BugReporter.cpp
The file was modifiedclang/unittests/StaticAnalyzer/CMakeLists.txt
Commit 9805afdfea7e5cc1c73efcd13c4bb1fc8c8d6765 by llvmgnsyncbot
[gn build] Port b0d38ad0bc25
The file was modifiedllvm/utils/gn/secondary/clang/unittests/StaticAnalyzer/BUILD.gn
Commit 04bddb6cc7c405f1a82ee1d94f96596c2cb387d9 by ajcbik
[mlir][crunner] fix bug in memref copy for rank 0

While replacing linalg.copy with the more desired memref.copy
I found a bug in the support library for rank 0 memref copying.
The code would loop for something like the following, since there
is code for no-rank and rank > 0, but rank == 0 was unexpected.

  memref.copy %0, %1: memref<f32> to memref<f32>

Note that a "regression test" for this will follow using the
sparse compiler migration to memref.copy which exercises this
case many times.

Reviewed By: herhut

Differential Revision: https://reviews.llvm.org/D106036
The file was modifiedmlir/lib/ExecutionEngine/CRunnerUtils.cpp
Commit d9cdcfb069e97b106474f11ace9193ca24323006 by tbaeder
[llvm][tools] Hide unrelated llvm-bcanalyzer options

They otherwise show up when we link against the dynamic libLLVM.so.

Differential Revision: https://reviews.llvm.org/D105893
The file was modifiedllvm/tools/llvm-bcanalyzer/llvm-bcanalyzer.cpp
The file was addedllvm/test/tools/llvm-bcanalyzer/help.test
Commit 4b219051a331d49c391fe452548bc220bcfe8ea3 by sguelton
Fix undeduced type assert

If the instantiation of a member variable makes it possible to
compute a previously undeduced type, we should use that piece of
information.

Fix bug#50590

Differential Revision: https://reviews.llvm.org/D103849
The file was modifiedclang/lib/AST/Expr.cpp
The file was modifiedclang/test/CodeGenCXX/auto-variable-template.cpp
Commit 442123cada4c06acf872f22ddfb7e47aec152215 by bgraur
Fixes memory sanitizer 'use-of-uninitialized-value' diagnostic.

Differential Revision: https://reviews.llvm.org/D106047
The file was modifiedllvm/lib/Target/PowerPC/PPCSubtarget.cpp
Commit 0ed1747a92d0f4294bc1ab22627b4c9bab42e27a by fmayer
[NFC] [hwasan] Split argument logic into functions.

Reviewed By: vitalybuka

Differential Revision: https://reviews.llvm.org/D105971
The file was modifiedllvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp
Commit dfa76933c29626d08a3538fcc66f120a5bc563b7 by cullen.rhodes
[AArch64][SME] Add outer product instructions

This patch adds support for the following outer product instructions:

  * BFMOPA, BFMOPS, FMOPA, FMOPS, SMOPA, SMOPS, SUMOPA, SUMOPS, UMOPA,
    UMOPS, USMOPA, USMOPS.

Depends on D105570.

The reference can be found here:
https://developer.arm.com/documentation/ddi0602/2021-06

Reviewed By: david-arm

Differential Revision: https://reviews.llvm.org/D105571
The file was addedllvm/test/MC/AArch64/SME/bfmopa-diagnostics.s
The file was addedllvm/test/MC/AArch64/SME/sumops-diagnostics.s
The file was addedllvm/test/MC/AArch64/SME/smops-32.s
The file was addedllvm/test/MC/AArch64/SME/usmopa-32.s
The file was addedllvm/test/MC/AArch64/SME/usmops-diagnostics.s
The file was modifiedllvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
The file was addedllvm/test/MC/AArch64/SME/sumops-32.s
The file was addedllvm/test/MC/AArch64/SME/fmopa-fp64.s
The file was addedllvm/test/MC/AArch64/SME/umops-diagnostics.s
The file was addedllvm/test/MC/AArch64/SME/sumops-64.s
The file was addedllvm/test/MC/AArch64/SME/umopa-32.s
The file was addedllvm/test/MC/AArch64/SME/smopa-diagnostics.s
The file was addedllvm/test/MC/AArch64/SME/umops-64.s
The file was addedllvm/test/MC/AArch64/SME/smopa-32.s
The file was addedllvm/test/MC/AArch64/SME/usmops-64.s
The file was addedllvm/test/MC/AArch64/SME/smops-64.s
The file was addedllvm/test/MC/AArch64/SME/smops-diagnostics.s
The file was addedllvm/test/MC/AArch64/SME/fmopa-diagnostics.s
The file was addedllvm/test/MC/AArch64/SME/usmopa-64.s
The file was addedllvm/test/MC/AArch64/SME/umops-32.s
The file was addedllvm/test/MC/AArch64/SME/umopa-64.s
The file was modifiedllvm/lib/Target/AArch64/SMEInstrFormats.td
The file was addedllvm/test/MC/AArch64/SME/fmops.s
The file was addedllvm/test/MC/AArch64/SME/bfmops.s
The file was addedllvm/test/MC/AArch64/SME/fmopa.s
The file was addedllvm/test/MC/AArch64/SME/sumopa-64.s
The file was addedllvm/test/MC/AArch64/SME/usmopa-diagnostics.s
The file was addedllvm/test/MC/AArch64/SME/sumopa-32.s
The file was addedllvm/test/MC/AArch64/SME/fmops-diagnostics.s
The file was addedllvm/test/MC/AArch64/SME/fmops-fp64.s
The file was addedllvm/test/MC/AArch64/SME/umopa-diagnostics.s
The file was addedllvm/test/MC/AArch64/SME/smopa-64.s
The file was addedllvm/test/MC/AArch64/SME/usmops-32.s
The file was addedllvm/test/MC/AArch64/SME/bfmops-diagnostics.s
The file was addedllvm/test/MC/AArch64/SME/bfmopa.s
The file was addedllvm/test/MC/AArch64/SME/sumopa-diagnostics.s
Commit 69a3acffdf1b3f5fc040aaeafc1c77588a607d1a by mkazantsev
[Test] We can benefit from pipelining of ymm load/stores

This patch demonstrates a scenario when we need to load/store a single
64-byte value, which is done by 2 ymm loads and stores in AVX. The current
codegen choses the following sequence:

  load ymm0
  load ymm1
  store ymm1
  store ymm0

If we instead stored ymm0 before ymm1, we could execute 2nd load and 1st store
in parallel.
The file was addedllvm/test/CodeGen/X86/ymm-ordering.ll
Commit acf0a6428681dccac803984bfbb1e3e54248f090 by iii
[sanitizer] Fix __sanitizer_kernel_sigset_t endianness issue

setuid(0) hangs on SystemZ under TSan because TSan's BackgroundThread
ignores SIGSETXID. This in turn happens because internal_sigdelset()
messes up the mask bits on big-endian system due to how
__sanitizer_kernel_sigset_t is defined.

Commit d9a1a53b8d80 ("[ESan] [MIPS] Fix workingset-signal-posix.cpp on
MIPS") fixed this for MIPS by adjusting the __sanitizer_kernel_sigset_t
definition. Generalize this by defining __SANITIZER_KERNEL_NSIG based
on kernel's _NSIG and using uptr[] for __sanitizer_kernel_sigset_t.sig
on all platforms.

Reviewed By: dvyukov

Differential Revision: https://reviews.llvm.org/D105629
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_linux.cpp
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_platform_limits_posix.h
Commit 54128b73f8336ffe5cfd89cc860e58c3bb38a425 by iii
[sanitizer] Force TLS allocation on s390

When running with an old glibc, CollectStaticTlsBlocks() calls
__tls_get_addr() in order to force TLS allocation. This function is not
available on s390 and the code simply does nothing in this case,
so all the resulting static TLS blocks end up being incorrect.

Fix by calling __tls_get_offset() on s390.

Reviewed By: dvyukov

Differential Revision: https://reviews.llvm.org/D105629
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_linux_libcdep.cpp
Commit cadbb9241627eefc9f589ae4376fd9ed3e272ecc by iii
[TSan] Align thread_registry_placeholder

s390x requires ThreadRegistry.mtx_.opaque_storage_ to be 4-byte
aligned. Since other architectures may have similar requirements, use
the maximum thread_registry_placeholder alignment from other
sanitizers, which is 64 (LSan).

Reviewed By: dvyukov

Differential Revision: https://reviews.llvm.org/D105629
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_rtl.cpp
Commit 3845f2cd940bd394fc735388ca0cd6652a98b7b9 by iii
[TSan] Use zeroext for function parameters

SystemZ ABI requires zero-extending function parameters to 64-bit. The
compiler is free to optimize the code around this assumption, e.g.
failing to zero-extend __tsan_atomic32_load()'s morder may cause
crashes in to_mo() switch table lookup.

Fix by adding zeroext attributes to TSan's FunctionCallees, similar to
how it was done in commit 3bc439bdff8b ("[MSan] Add instrumentation for
SystemZ"). This is a no-op on arches that don't need it.

Reviewed By: dvyukov

Differential Revision: https://reviews.llvm.org/D105629
The file was modifiedllvm/lib/Transforms/Instrumentation/ThreadSanitizer.cpp
Commit d5c34ee5b666e12f92cf5b6e35490e1746fcc5e9 by iii
[TSan] Build ignore_lib{0,1,5} tests with -fno-builtin

These tests depend on TSan seeing the intercepted memcpy(), so they
break when the compiler chooses the builtin version.

Reviewed By: dvyukov

Differential Revision: https://reviews.llvm.org/D105629
The file was modifiedcompiler-rt/test/tsan/ignore_lib1.cpp
The file was modifiedcompiler-rt/test/tsan/ignore_lib5.cpp
The file was modifiedcompiler-rt/test/tsan/ignore_lib0.cpp
Commit fab044045b63d59586caa09aa47892d0f7ce31d0 by iii
[TSan] Define PTHREAD_ABI_BASE for SystemZ

SystemZ's glibc symbols use version 2.3.2.

Reviewed By: dvyukov

Differential Revision: https://reviews.llvm.org/D105629
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_interceptors_posix.cpp
Commit 96a29df0b166ed52806dfd01236c604c0eb8b7d1 by iii
[TSan] Define C/C++ address ranges for SystemZ

The kernel supports a full 64-bit VMA, but we can use only 48 bits due
to the limitation imposed by SyncVar::GetId(). So define the address
ranges similar to the other architectures, except that the address
space "tail" needs to be made inaccessible in CheckAndProtect(). Since
it's for only one architecture, don't make an abstraction for this.

Reviewed By: dvyukov

Differential Revision: https://reviews.llvm.org/D105629
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_platform.h
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_platform_posix.cpp
Commit 402fc790eb484161866941cc840e20bdf5ae80e6 by iii
[TSan] Add SystemZ longjmp support

Implement the interceptor and stack pointer demangling.

Reviewed By: dvyukov

Differential Revision: https://reviews.llvm.org/D105629
The file was modifiedcompiler-rt/lib/tsan/CMakeLists.txt
The file was modifiedllvm/utils/gn/secondary/compiler-rt/lib/tsan/BUILD.gn
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_platform_linux.cpp
The file was addedcompiler-rt/lib/tsan/rtl/tsan_rtl_s390x.S
Commit b17673816d7f65e07015489993b22049e36b04db by iii
[TSan] Disable __TSAN_HAS_INT128 on SystemZ

SystemZ does not have 128-bit atomics.

Reviewed By: dvyukov

Differential Revision: https://reviews.llvm.org/D105629
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_interface.h
Commit bd77f742d656afa20faf9ce79b552e1ded4af5e5 by iii
[TSan] Intercept __tls_get_addr_internal and __tls_get_offset on SystemZ

Reuse the assembly glue code from sanitizer_common_interceptors.inc and
the handling logic from the __tls_get_addr interceptor.

Reviewed By: dvyukov

Differential Revision: https://reviews.llvm.org/D105629
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_common_interceptors.inc
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_interceptors_posix.cpp
Commit 937242cecc13f60c8e31ce8f936bfe218af42a90 by iii
[TSan] Adjust tests for SystemZ

XFAIL map32bit, define the maximum possible allocation size in
mmap_large.cpp.

Reviewed By: dvyukov

Differential Revision: https://reviews.llvm.org/D105629
The file was modifiedcompiler-rt/test/tsan/mmap_large.cpp
The file was modifiedcompiler-rt/test/tsan/map32bit.cpp
Commit e34078f121a58b503d225cf715d1494117e7948b by iii
[TSan] Enable SystemZ support

Enable building the runtime and enable -fsanitize=thread in clang.

Reviewed By: dvyukov

Differential Revision: https://reviews.llvm.org/D105629
The file was modifiedclang/lib/Driver/ToolChains/Linux.cpp
The file was modifiedcompiler-rt/cmake/config-ix.cmake
Commit 9bf2e7eeebbd7524cfa3c448b40196fcd0a1a4cb by iii
[TSan] Add SystemZ SANITIZER_GO support

Define the address ranges (similar to the C/C++ ones, but with the heap
range merged into the app range) and enable the sanity check.

Reviewed By: dvyukov

Differential Revision: https://reviews.llvm.org/D105629
The file was modifiedcompiler-rt/lib/tsan/go/buildgo.sh
The file was modifiedcompiler-rt/lib/tsan/CMakeLists.txt
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_platform.h
The file was modifiedcompiler-rt/test/tsan/CMakeLists.txt
Commit afd895709db96f86fe80c4c0980e449f67bdbe9e by sebastian.neubauer
[AMDGPU] Use isMetaInstruction for instruction size

Meta instructions have a size of 0. Use isMetaInstruction instead of
listing them explicitly.

Differential Revision: https://reviews.llvm.org/D106043
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.cpp
Commit 831ee6b0c38bbb9ed1206a67a5a1df4e24066ea0 by irina.dobrescu
[AArch64][GlobalISel] Optimise lowering for some vector types for min/max

Differential Revision: https://reviews.llvm.org/D105696
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
The file was modifiedllvm/test/CodeGen/AArch64/min-max.ll
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/legalize-min-max.mir
Commit ffe6a5832533e71e1edc4fe0eebda421f24fb61a by akuegel
[mlir][nvvm]: Add math::Exp2Op lowering to NVVM.

Differential Revision: https://reviews.llvm.org/D106050
The file was modifiedmlir/lib/Conversion/GPUToNVVM/LowerGpuOpsToNVVMOps.cpp
The file was modifiedmlir/test/Conversion/GPUToNVVM/gpu-to-nvvm.mlir
Commit d179c43206fde9280101804830f43a4e35d6aa84 by llvm-dev
[MIPS] Refresh ashr test checks. NFCI.
The file was modifiedllvm/test/CodeGen/Mips/llvm-ir/ashr.ll
Commit 944f39f38d2b1d54ac9a5668e3ef33d946a81344 by llvm-dev
[InstCombine] Strip inbounds from (select C, (gep Ptr, Idx), Ptr) -> (gep Ptr, (select C, Idx, 0)) fold

As discussed on rGd561b6fbdbe6, we can't guarantee that the new gep is inbounds
The file was modifiedllvm/test/Transforms/InstCombine/select-gep.ll
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
Commit e21663d32b30211c145c5ab85f079e33bbdc72bb by llvm-dev
[NVPTX] Add selp.f32 checks to select(cond,fpbinop(),fpbinop()) tests

Will help show codegen diffs in an upcoming patch
The file was modifiedllvm/test/CodeGen/NVPTX/fast-math.ll
Commit 5cbd5c62beeb8f1cb1408bc8f68ec1b522b4061c by fraser
[VP][NFC] Correct formatting in unit test
The file was modifiedllvm/unittests/IR/VPIntrinsicTest.cpp
Commit 0c3401c86e82cb5d8ba0c9dec6573473e505c5fc by Louis Dionne
[runtimes] Serialize all Lit params instead of passing them to add_lit_testsuite

add_lit_testsuite() takes Lit parameters passed to it and adds them
to the parameters used globally when running all test suites. That
means that a target like `check-all`, which ends up calling Lit on
the whole monorepo, will see the test parameters for all the individual
project's test suites.

So, for example, it would see `--param std=c++03` (from libc++abi), and
`--param std=c++03` (from libc++), and `--param whatever` (from another
project being tested at the same time). While always unclean, that works
when the parameters all agree. However, if the parameters share the same
name but have different values, only one of those two values will be used
and it will be incredibly confusing to understand why one of the test
suites is being run with the incorrect parameter value.

For that reason, this commit moves away from using add_lit_testsuite()'s
PARAM functionality, and serializes the parameter values for the runtimes
in the generated config.py file instead, which is local to the specific
test suite.

Differential Revision: https://reviews.llvm.org/D105991
The file was modifiedlibcxx/test/CMakeLists.txt
The file was modifiedlibunwind/test/CMakeLists.txt
The file was modifiedlibcxxabi/test/CMakeLists.txt
Commit 3001b48d76bcf10063286efc722a8479522f4c50 by Louis Dionne
[libc++] Implement views::all_t and ranges::viewable_range

Differential Revision: https://reviews.llvm.org/D105816
The file was removedlibcxx/test/std/ranges/range.adaptors/range.all.pass.cpp
The file was modifiedlibcxx/test/std/containers/associative/multiset/range_concept_conformance.compile.pass.cpp
The file was modifiedlibcxx/test/std/input.output/filesystems/class.directory_iterator/range_concept_conformance.compile.pass.cpp
The file was modifiedlibcxx/include/__ranges/transform_view.h
The file was modifiedlibcxx/test/std/re/re.results/range_concept_conformance.compile.pass.cpp
The file was modifiedlibcxx/test/std/containers/sequences/forwardlist/range_concept_conformance.compile.pass.cpp
The file was modifiedlibcxx/test/std/containers/views/range_concept_conformance.compile.pass.cpp
The file was addedlibcxx/test/std/ranges/range.req/range.refinements/viewable_range.compile.pass.cpp
The file was modifiedlibcxx/test/std/containers/sequences/vector.bool/range_concept_conformance.compile.pass.cpp
The file was modifiedlibcxx/test/std/containers/associative/map/range_concept_conformance.compile.pass.cpp
The file was modifiedlibcxx/test/std/containers/unord/unord.set/range_concept_conformance.compile.pass.cpp
The file was modifiedlibcxx/test/std/containers/sequences/deque/range_concept_conformance.compile.pass.cpp
The file was modifiedlibcxx/test/std/ranges/range.adaptors/range.ref.view.pass.cpp
The file was modifiedlibcxx/test/std/containers/unord/unord.multimap/range_concept_conformance.compile.pass.cpp
The file was modifiedlibcxx/test/std/containers/associative/set/range_concept_conformance.compile.pass.cpp
The file was modifiedlibcxx/include/__ranges/drop_view.h
The file was modifiedlibcxx/test/std/containers/sequences/list/range_concept_conformance.compile.pass.cpp
The file was modifiedlibcxx/test/std/containers/sequences/vector/range_concept_conformance.compile.pass.cpp
The file was addedlibcxx/test/std/ranges/range.adaptors/range.all/all.pass.cpp
The file was modifiedlibcxx/test/std/strings/basic.string/range_concept_conformance.compile.pass.cpp
The file was modifiedlibcxx/include/__ranges/concepts.h
The file was modifiedlibcxx/test/std/containers/associative/multimap/range_concept_conformance.compile.pass.cpp
The file was modifiedlibcxx/test/std/strings/string.view/range_concept_conformance.compile.pass.cpp
The file was modifiedlibcxx/include/ranges
The file was modifiedlibcxx/test/std/containers/sequences/array/range_concept_conformance.compile.pass.cpp
The file was modifiedlibcxx/test/std/input.output/filesystems/class.path/range_concept_conformance.compile.pass.cpp
The file was modifiedlibcxx/docs/Status/RangesPaper.csv
The file was modifiedlibcxx/include/__ranges/all.h
The file was modifiedlibcxx/test/std/containers/unord/unord.map/range_concept_conformance.compile.pass.cpp
The file was addedlibcxx/test/std/ranges/range.adaptors/range.all/all_t.compile.pass.cpp
The file was modifiedlibcxx/test/std/containers/unord/unord.multiset/range_concept_conformance.compile.pass.cpp
Commit 47633af9d4a8b93f50cb711cf23489736e0226f1 by stephen.tozer
Reapply "[DebugInfo] Enable variadic debug value salvaging"

Reapplied after previous build failures were fixed in 14b62f7e2.

This reverts commit 540b4a5fb31086b6d40735e96e6ec497022107e7.
The file was modifiedllvm/lib/Transforms/Utils/Local.cpp
The file was modifiedllvm/test/DebugInfo/salvage-gep.ll
The file was modifiedllvm/test/DebugInfo/salvage-duplicate-values.ll
The file was modifiedllvm/test/DebugInfo/salvage-nonconst-binop.ll
Commit 5024fe93068082ac230643095cbbac5c2aa74d36 by Louis Dionne
[libc++] Mark failing rel_ops test as XFAIL in back-deployment

The test triggers availability errors.
The file was modifiedlibcxx/test/std/containers/iterator.rel_ops.compile.pass.cpp
Commit 01bdb0f75efb2bb795a79cea9f3f918136d13a7f by nicolas.vasilache
[mlir][linalg] Improve implementation of hoist padding.

Instead of relying on adhoc bounds calculations, use a projection-based
implementation. This simplifies the implementation and finds more static
constant sizes than previously/

Differential Revision: https://reviews.llvm.org/D106054
The file was modifiedmlir/test/Dialect/Linalg/hoist-padding.mlir
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/Hoisting.cpp
The file was modifiedmlir/lib/Dialect/Linalg/Analysis/CMakeLists.txt
The file was addedmlir/include/mlir/Dialect/Linalg/Analysis/ConstraintsSet.h
The file was addedmlir/lib/Dialect/Linalg/Analysis/ConstraintsSet.cpp
Commit dc7bdc1e7121693df112f2fdb11cc6b88580ba4b by sander.desmalen
[LV] Fix determinism for failing scalable-call.ll test.

The sort function for emitting an OptRemark was not deterministic,
which caused scalable-call.ll to fail on some buildbots. This patch
fixes that.

This patch also fixes an issue where `Instruction::comesBefore()`
is called when two Instructions are in different basic blocks,
which would otherwise cause an assertion failure.
The file was modifiedllvm/test/Transforms/LoopVectorize/AArch64/scalable-call.ll
The file was modifiedllvm/lib/Transforms/Vectorize/LoopVectorize.cpp
Commit 91e151476c75ebad640a62b469328e7184f45ef2 by llvm-dev
[TTI] Consistently make getMinVectorRegisterBitWidth() methods const. NFCI.

The underlying getMinVectorRegisterBitWidth() methods are const, but it was missed in a couple of TargetTransformInfo wrappers.

Noticed while working on D103925
The file was modifiedllvm/include/llvm/Analysis/TargetTransformInfo.h
The file was modifiedllvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
Commit 74b88807ae761da3ae1d5eb947d242a3492e23d0 by akuegel
[mlir][rocdl] Add math::Exp2Op lowering to ROCDL

Differential Revision: https://reviews.llvm.org/D106057
The file was modifiedmlir/test/Conversion/GPUToROCDL/gpu-to-rocdl.mlir
The file was modifiedmlir/lib/Conversion/GPUToROCDL/LowerGpuOpsToROCDLOps.cpp
Commit 3e6c383dc63685a6248fd6f1ffabad0b42af99a0 by lebedev.ri
[SimplifyCFG] Rerun PHI deduplication after common code sinkinkg (PR51092)

`SinkCommonCodeFromPredecessors()` doesn't itself ensure that duplicate PHI nodes aren't created.
I suppose, we could teach it to do that on-the-fly (& account for the already-existing PHI nodes,
& adjust costmodel), the diff will be bigger than this.

The alternative is to schedule a new EarlyCSE pass invocation somewhere later in the pipeline.
Clearly, we don't have any EarlyCSE runs in module optimization passline, so this pattern isn't cleaned up...
That would perhaps better, but it will again have some compile time impact.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D106010
The file was modifiedllvm/lib/Transforms/Utils/SimplifyCFG.cpp
The file was modifiedllvm/test/Transforms/PGOProfile/cspgo_profile_summary.ll
The file was modifiedllvm/test/Transforms/SimplifyCFG/X86/sink-common-code.ll
The file was modifiedllvm/test/Transforms/PhaseOrdering/X86/earlycse-after-simplifycfg-two-entry-phi-node-folding.ll
Commit 034b94bb7161c64234e4ec35bf49428c3a1f8f0a by aaron
Fix documentation; NFC

The documentation about ignoringImpCasts is wrong, which can cause
misunderstandings. This patch fixes it.
The file was modifiedclang/include/clang/ASTMatchers/ASTMatchers.h
The file was modifiedclang/docs/LibASTMatchersReference.html
Commit 5d7632ee72c51b518bde17e385b71c5d3f0d2560 by Tim Northover
MachO: don't emit L... private symbols in do_not_dead_strip sections.

The linker can sometimes drop the do_not_dead_strip if it can't associate the
atom with a symbol (the other place to specify no dead-stripping in MachO
files).
The file was modifiedllvm/test/CodeGen/X86/osx-private-labels.ll
The file was modifiedllvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
Commit dad506bd4e27b52e671a8b927320845732e1e073 by david.green
[ARM] Expand types handled in VQDMULH recognition

We have a DAG combine for recognizing the sequence of nodes that make up
an MVE VQDMULH, but only currently handles specifically legal types.
This patch expands that to other power-2 vector types. For smaller than
legal types this means any_extending the type and casting it to a legal
type, using a VQDMULH where we only use some of the lanes. The result is
sign extended back to the original type, to properly set the invalid
lanes. Larger than legal types are split into chunks with extracts and
concat back together.

Differential Revision: https://reviews.llvm.org/D105814
The file was modifiedllvm/test/CodeGen/Thumb2/mve-vqdmulh.ll
The file was modifiedllvm/lib/Target/ARM/ARMISelLowering.cpp
Commit b36c4bb3ecc954f8c78d21a3200fc8faaec240d0 by nathan
[docs] More CMAKE variable documentation

This breaks out some (more) common llvm-specific
variables. Controlling the subprojects and target architectures, along
with clues about restricting build parallelism when linking. 'more
common' is somewhat subjective, of course.

Differential Revision: https://reviews.llvm.org/D105822
The file was modifiedllvm/docs/CMake.rst
Commit f24335c69ea363082d922797363e98f1dcb3b14f by Tim Northover
MachO: fix Clang test broken by dropping private labels in LLVM.

LLVM changed to not emit L... labels for things marked "do_not_dead_strip"
because the linker can sometimes drop the flag if there's no proper symbol.
This Clang test checked for the old behaviour, but doesn't actually care about
that bit.
The file was modifiedclang/test/CodeGenObjC/protocol-in-extended-class.m
Commit 05eb59e1d0ea7505539434a32ccc5c3dc2097597 by anton.zabaznov
[OpenCL] Add support of __opencl_c_program_scope_global_variables feature macro

Reviewed By: Anastasia

Differential Revision: https://reviews.llvm.org/D103191
The file was modifiedclang/test/CodeGenOpenCL/addr-space-struct-arg.cl
The file was modifiedclang/test/SemaOpenCL/storageclass.cl
The file was modifiedclang/include/clang/Basic/OpenCLOptions.h
The file was modifiedclang/lib/Sema/SemaDecl.cpp
Commit a607f64118240f70bf1b14ec121b65f49d63800d by sander.desmalen
Revert "[LV] Print remark when loop cannot be vectorized due to invalid costs."

This reverts commit efaf3099c8cec1954831ee28a2f75a72096f50eb.
This reverts commit dc7bdc1e7121693df112f2fdb11cc6b88580ba4b.

Reverting patches due to buildbot failures.
The file was modifiedllvm/lib/Transforms/Vectorize/LoopVectorize.cpp
The file was modifiedllvm/test/Transforms/LoopVectorize/AArch64/scalable-call.ll
Commit d0d37fcc4e2965c4ccd3401f8bdf22935815136a by gabor.marton
[Analyzer][solver] Remove unused functions

../../git/llvm-project/clang/lib/StaticAnalyzer/Core/RangeConstraintManager.cpp:2395:17: warning: 'clang::ento::ProgramStateRef {anonymous}::RangeConstraintManager::setRange(clang::ento::ProgramStateRef, {anonymous}::EquivalenceClass, clang::ento::RangeSet)' defined but not used [-Wunused-function]
../../git/llvm-project/clang/lib/StaticAnalyzer/Core/RangeConstraintManager.cpp:2384:10: warning: 'clang::ento::RangeSet {anonymous}::RangeConstraintManager::getRange(clang::ento::ProgramStateRef, {anonymous}::EquivalenceClass)' defined but not used [-Wunused-function]

Differential Revision: https://reviews.llvm.org/D106063
The file was modifiedclang/lib/StaticAnalyzer/Core/RangeConstraintManager.cpp
Commit 3cc38703d5ab05be0b01c31f829d19b47f183c5f by llvm-dev
[NVPTX] Tweak fast-math tests to avoid select(binop(x,y),binop(x,z)) fold

As suggested on D106058, tweak the tests to keep the combineRepeatedFPDivisors test coverage.
The file was modifiedllvm/test/CodeGen/NVPTX/fast-math.ll
Commit 68ac2e53ff289ae541e5e9929605a649d6f3019b by ajcbik
[mlir][sparse] replace linalg.copy with memref.copy

Note, this revision relies on the following revision
for a bugfix in the memref copy library in order for
all sparse integration tests to pass.

https://reviews.llvm.org/D106036

Reviewed By: ftynse

Differential Revision: https://reviews.llvm.org/D106038
The file was modifiedmlir/test/Dialect/SparseTensor/sparse_lower_inplace.mlir
The file was modifiedmlir/lib/Dialect/SparseTensor/Transforms/Sparsification.cpp
The file was modifiedmlir/test/Dialect/SparseTensor/sparse_1d.mlir
The file was modifiedmlir/test/Dialect/SparseTensor/sparse_lower.mlir
The file was modifiedmlir/test/Dialect/SparseTensor/sparse_lower_col.mlir
The file was modifiedmlir/test/Dialect/SparseTensor/sparse_nd.mlir
The file was modifiedmlir/test/Dialect/SparseTensor/sparse_3d.mlir
The file was modifiedmlir/test/Dialect/SparseTensor/dense.mlir
The file was modifiedmlir/test/Dialect/SparseTensor/sparse_2d.mlir
Commit 0aece73aba65b92770e63bc6c138e8b1a177d45f by llvm-dev
[DAG] Fold select(cond,binop(x,y),binop(x,z)) -> binop(x,select(cond,y,z))

Similar to the folds performed in InstCombinerImpl::foldSelectOpOp, this attempts to push a select further up to help merge a pair of binops.

I'm primarily interested in select(cond,add(x,y),add(x,z)) folds to help expose pointer math (see https://bugs.llvm.org/show_bug.cgi?id=51069 etc.) but I've tried to use the more generic isBinOp().

Differential Revision: https://reviews.llvm.org/D106058
The file was modifiedllvm/test/CodeGen/X86/select.ll
The file was modifiedllvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Commit a70ef3f568cb7ce963aeb04000d3c29699ee1c47 by tianshilei1992
Revert "[AbstractAttributor] Fold function calls to `__kmpc_is_spmd_exec_mode` if possible"

This reverts commit 1100e4aafea233bc8bbc307c5758a7d287ad3bae.
The file was modifiedllvm/lib/Transforms/IPO/OpenMPOpt.cpp
The file was modifiedllvm/test/Transforms/OpenMP/custom_state_machines.ll
The file was removedllvm/test/Transforms/OpenMP/is_spmd_exec_mode_fold.ll
Commit d40e8091bd1f48e8d3f64e4f99952f0139e9c27b by wei.huang
[PowerPC] Add PowerPC rotate related builtins and emit target independent code for XL compatibility

This patch is in a series of patches to provide builtins for compatibility
with the XL compiler. This patch adds the builtins and emit target independent
code for rotate related operations.

Reviewed By: nemanjai, #powerpc

Differential revision: https://reviews.llvm.org/D104744
The file was modifiedclang/lib/Sema/SemaChecking.cpp
The file was modifiedclang/include/clang/Basic/DiagnosticSemaKinds.td
The file was modifiedclang/lib/Basic/Targets/PPC.cpp
The file was modifiedclang/lib/CodeGen/CGBuiltin.cpp
The file was addedclang/test/CodeGen/builtins-ppc-xlcompat-rotate.c
The file was modifiedclang/include/clang/Basic/BuiltinsPPC.def
The file was modifiedclang/include/clang/Sema/Sema.h
The file was modifiedclang/test/CodeGen/builtins-ppc-xlcompat-error.c
Commit e33446ea58b8357dd8b79eb39140a1de2baff1ae by dvyukov
tsan: make obtaining current PC faster

We obtain the current PC is all interceptors and collectively
common interceptor code contributes to overall slowdown
(in particular cheaper str/mem* functions).

The current way to obtain the current PC involves:

  4493e1:       e8 3a f3 fe ff          callq  438720 <_ZN11__sanitizer10StackTrace12GetCurrentPcEv>
  4493e9:       48 89 c6                mov    %rax,%rsi

and the called function is:

uptr StackTrace::GetCurrentPc() {
  438720:       48 8b 04 24             mov    (%rsp),%rax
  438724:       c3                      retq

The new way uses address of a local label and involves just:

  44a888:       48 8d 35 fa ff ff ff    lea    -0x6(%rip),%rsi

I am not switching all uses of StackTrace::GetCurrentPc to GET_CURRENT_PC
because it may lead some differences in produced reports and break tests.
The difference comes from the fact that currently we have PC pointing
to the CALL instruction, but the new way does not yield any code on its own
so the PC points to a random instruction in the function and symbolizing
that instruction can produce additional inlined frames (if the random
instruction happen to relate to some inlined function).

Reviewed By: melver

Differential Revision: https://reviews.llvm.org/D106046
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_stacktrace.h
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_interceptors.h
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_interceptors_posix.cpp
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_stacktrace.cpp
Commit f59209a86eaf5ec2edea74b9b6e4932148efb3e0 by nikita.ppv
[AsmParser] Unify parsing of attributes

Continuing on from D105780, this should be the last major bit of
attribute cleanup. Currently, LLParser implements attribute parsing
for functions, parameters and returns separately, enumerating all
supported (and unsupported) attributes each time. This patch
extracts the common parsing logic, and performs a check afterwards
whether the attribute is valid in the given position. Parameters
and returns are handled together, while function attributes need
slightly different logic to support attribute groups.

Differential Revision: https://reviews.llvm.org/D105938
The file was modifiedllvm/test/Assembler/byref-parse-error-6.ll
The file was modifiedllvm/test/Assembler/invalid-safestack-return.ll
The file was modifiedllvm/test/Assembler/mustprogress-parse-error-0.ll
The file was modifiedllvm/test/Assembler/byref-parse-error-8.ll
The file was modifiedllvm/test/Assembler/invalid-immarg3.ll
The file was modifiedllvm/include/llvm/AsmParser/LLParser.h
The file was modifiedllvm/test/Assembler/byref-parse-error-9.ll
The file was modifiedllvm/test/Verifier/swifterror2.ll
The file was modifiedllvm/test/Assembler/invalid-safestack-param.ll
The file was modifiedllvm/test/Transforms/LoopDeletion/assume.ll
The file was modifiedllvm/test/Assembler/invalid-immarg2.ll
The file was modifiedllvm/test/Assembler/mustprogress-parse-error-1.ll
The file was modifiedllvm/test/Assembler/byref-parse-error-5.ll
The file was modifiedllvm/test/Assembler/byref-parse-error-10.ll
The file was modifiedllvm/test/Assembler/byref-parse-error-7.ll
The file was modifiedllvm/lib/AsmParser/LLParser.cpp
Commit 95346ba87740aabcb82cb3c8d0e722e7b86d93b7 by listmail
[LV] Enable vectorization of multiple exit loops w/computable exit counts

This change enables vectorization of multiple exit loops when the exit count is statically computable. That requirement - shared with the rest of LV - in turn requires each exit to be analyzeable and to dominate the latch.

The majority of work to support this was done in a set of previous patches. In particular,, 72314466 avoids having multiple edges from the middle block to the exits, and 4b33b2387 which added support for non-latch single exit and multiple exits with a single exiting block. As a result, this change is basically just removing a bailout and adjusting some tests now that the prerequisite work is done and has stuck in tree for a bit.

Differential Revision: https://reviews.llvm.org/D105817
The file was modifiedllvm/test/Transforms/LoopVectorize/loop-form.ll
The file was modifiedllvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp
The file was modifiedllvm/test/Transforms/LoopVectorize/loop-legality-checks.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/remarks-multi-exit-loops.ll
Commit ab03ef124afd97f8c272fd6ef2dd91b88c55e4fa by gcmn
[Bazel] Update for 01bdb0f75efb

Update the build files for
https://github.com/llvm/llvm-project/commit/01bdb0f75efb

Tested:
bazel query //... + @llvm-project//... | xargs bazel test --config=generic_clang --config=rbe --test_output=errors --test_ta
g_filters=-nobuildkite --build_tag_filters=-nobuildkite

Differential Revision: https://reviews.llvm.org/D106075
The file was modifiedutils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Commit 04b75c05b033d5c7fd503de90b257be713c95e00 by aeubanks
[InstCombine] Look through invariant group intrinsics when removing malloc

Fixes some regressions with -fstrict-vtable-pointers in llvm-test-suite.

Reviewed By: lebedev.ri

Differential Revision: https://reviews.llvm.org/D106017
The file was modifiedllvm/lib/Transforms/InstCombine/InstructionCombining.cpp
The file was modifiedllvm/test/Transforms/InstCombine/malloc-free-delete.ll
Commit 1fd23a065bf729836dd52ef1ad3c84c449735a56 by nikita.ppv
[LangRef] Add elementtype attribute

This adds an elementtype(<ty>) attribute, which can be used to
attach an element type to a pointer typed argument. It is similar
to byval/byref in purpose, but unlike those does not carry any
specific semantics by itself. However, certain intrinsics may
require it and interpret it in specific ways.

The in-tree use cases for this that I'm currently aware of are:

    call ptr @llvm.preserve.array.access.index.p0.p0(ptr elementtype(%ty) %base, i32 %dim, i32 %index)
    call ptr @llvm.preserve.struct.access.index.p0.p0(ptr elementtype(%ty) %base, i32 %gep_index, i32 %di_index)
    call token @llvm.experimental.gc.statepoint.p0(i64 0, i32 0, ptr elementtype(void ()) @foo, i32 0, i32 0, i32 0, i32 0, ptr addrspace(1) %obj)

Notably, the gc.statepoint case needs a function as element type,
in which case the workaround of adding a separate %ty undef
argument would not work, as arguments cannot be unsized.

Differential Revision: https://reviews.llvm.org/D105407
The file was modifiedllvm/docs/LangRef.rst
Commit c191035f421b5dc69873cba8885fee41e984cc5d by nikita.ppv
[IR] Add elementtype attribute

This implements the elementtype attribute specified in D105407. It
just adds the attribute and the specified verifier rules, but
doesn't yet make use of it anywhere.

Differential Revision: https://reviews.llvm.org/D106008
The file was modifiedllvm/lib/Bitcode/Reader/BitcodeReader.cpp
The file was modifiedllvm/lib/Bitcode/Writer/BitcodeWriter.cpp
The file was modifiedllvm/lib/IR/Attributes.cpp
The file was modifiedllvm/lib/Transforms/Utils/CodeExtractor.cpp
The file was modifiedllvm/test/Verifier/opaque-ptr.ll
The file was modifiedllvm/include/llvm/IR/Attributes.h
The file was modifiedllvm/include/llvm/AsmParser/LLToken.h
The file was modifiedllvm/include/llvm/Bitcode/LLVMBitCodes.h
The file was modifiedllvm/lib/AsmParser/LLLexer.cpp
The file was modifiedllvm/lib/IR/Verifier.cpp
The file was modifiedllvm/test/Bitcode/attributes.ll
The file was modifiedllvm/include/llvm/IR/Attributes.td
The file was addedllvm/test/Verifier/elementtype.ll
Commit 1f8e286cdc14488c80eeb4a92ff791510d19a0d3 by Louis Dionne
[libc++] Add a CMake target to re-generate files and revamp CONTRIBUTING.rst

As we automate more and more things in the library, it becomes useful for
contributors to have a single target for running all the automation as
part of their workflow. This commit adds a new `libcxx-generate-files`
target that should re-generate all the auto-generated files in the library.

As a fly-by, I also revamped the documentation on Contributing to account
for this new target and present it as a bullet list of things to check
before committing. I also added a few things that are often overlooked
to that list, such as updating the synopsis and the status files.

Differential Revision: https://reviews.llvm.org/D106067
The file was modifiedlibcxx/utils/ci/run-buildbot
The file was modifiedlibcxx/docs/Contributing.rst
The file was modifiedlibcxx/CMakeLists.txt
The file was addedlibcxx/utils/CMakeLists.txt
Commit e6e79b3f0b2a2fd2b22ed8aa9267a6c915782632 by ajcbik
[mlir][sparse] remove linalg-to-loops from integration tests

With the migration from linalg.copy to memref.copy, this pass
(which was there solely to handle the linalg.copy op) is no
longer required for the end-to-end path for sparse compilation.

Reviewed By: ftynse

Differential Revision: https://reviews.llvm.org/D106073
The file was modifiedmlir/test/Integration/Dialect/SparseTensor/CPU/sparse_mttkrp.mlir
The file was modifiedmlir/test/Integration/Dialect/SparseTensor/CPU/sparse_sum.mlir
The file was modifiedmlir/test/Integration/Dialect/SparseTensor/CPU/sparse_flatten.mlir
The file was modifiedmlir/test/Integration/Dialect/SparseTensor/CPU/dense_output.mlir
The file was modifiedmlir/test/Integration/Dialect/SparseTensor/CPU/sparse_spmm.mlir
The file was modifiedmlir/test/Integration/Dialect/SparseTensor/CPU/sparse_matvec.mlir
The file was modifiedmlir/test/Integration/Dialect/SparseTensor/CPU/sparse_out_simple.mlir
The file was modifiedmlir/test/Integration/Dialect/SparseTensor/CPU/sparse_sampled_matmul.mlir
Commit 47f846f8c5ba54fde266ced3d9228d9f003c03ee by andrzej.warzynski
Enable Flang by default in the test-release.sh script

I've also brought this up on llvm-dev:
  https://lists.llvm.org/pipermail/llvm-dev/2021-July/151744.html

Differential Revision: https://reviews.llvm.org/D105885
The file was modifiedllvm/utils/release/test-release.sh
Commit 9f6ff37a36ffb7601fd9e23f0b6ae2156ae3ff77 by andrzej.warzynski
[flang][driver] Randomise the names of the unparsed files

This patch makes sure that the base name of the temporary unparsed files
(generated by the `flang` bash script) are randomised and unique to a
particular invocation of the script. Otherwise, we cannot reliably run
the script in parallel.

Differential Revision: https://reviews.llvm.org/D106052
The file was modifiedflang/tools/f18/flang.in
Commit 2b6e433230ab9fa8a898261cd460a3f1a1bc91ec by ajcbik
[mlir][sparse] add shift ops support

Arbitrary shifts have some complications, but shift by invariants
(viz. tensor index exp only at left hand side) can be easily
handled with the conjunctive rule.

Reviewed By: gussmith23

Differential Revision: https://reviews.llvm.org/D106002
The file was modifiedmlir/include/mlir/Dialect/SparseTensor/Utils/Merger.h
The file was modifiedmlir/lib/Dialect/SparseTensor/Utils/Merger.cpp
The file was modifiedmlir/test/Dialect/SparseTensor/sparse_int_ops.mlir
Commit 7299c6f635681aeec250309b1675329fbcb8bb1a by i
[test] Avoid llvm-nm one-dash long options
The file was modifiedlld/test/mach-o/debug-syms.yaml
The file was modifiedcompiler-rt/test/asan/TestCases/Darwin/dead-strip.c
Commit 96e9bc42447531a20569e0a680c029837a4868d8 by i
[llvm-nm] Remove one-dash long options except -arch

The documentation and help messages have recommended the double-dash forms for
quite a while. Remove one-dash long options which are not recognized by GNU
style `getopt_long`.

`-arch` is kept as it is in the manpage of classic nm
https://keith.github.io/xcode-man-pages/nm.1.html

Note: the dyldinfo related options don't have a test.

Reviewed By: jhenderson

Differential Revision: https://reviews.llvm.org/D105948
The file was modifiedllvm/tools/llvm-nm/Opts.td
The file was modifiedllvm/test/tools/llvm-nm/X86/posix-aliases.test
Commit c46d99e4ba16c76e666eb46dce710036ecbcee0d by Stanislav.Mekhanoshin
[AMDGPU] Refine -O0 and -O1 passes.

Differential Revision: https://reviews.llvm.org/D105579
The file was modifiedllvm/test/CodeGen/AMDGPU/llvm.amdgcn.update.dpp.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/wwm-reserved-spill.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/wwm-reserved.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/llc-pipeline.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/scalar_to_vector_v2x16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/control-flow-fastregalloc.ll
Commit c931ff72bde42846db4530893a94c044879c5ae9 by thakis
[lld-macho] Add LTO cache support

This adds support for the lld-only `--thinlto-cache-policy` option, as well as
implementations for ld64's `-cache_path_lto`, `-prune_interval_lto`,
`-prune_after_lto`, and `-max_relative_cache_size_lto`.

Test is adapted from lld/test/ELF/lto/cache.ll

Differential Revision: https://reviews.llvm.org/D105922
The file was modifiedlld/MachO/Options.td
The file was modifiedlld/MachO/Driver.cpp
The file was modifiedlld/MachO/LTO.cpp
The file was modifiedlld/MachO/LTO.h
The file was addedlld/test/MachO/lto-cache.ll
The file was modifiedlld/MachO/Config.h
Commit 4157b6033d09d17e8492f3bc7c4e050e63501757 by aardappel
[WebAssembly] Fixed LLD generation of 64-bit __wasm_apply_data_relocs

Differential Revision: https://reviews.llvm.org/D105863
The file was modifiedlld/wasm/SyntheticSections.cpp
The file was modifiedlld/test/wasm/shared64.s
The file was modifiedlld/wasm/InputChunks.cpp
The file was modifiedlld/wasm/Driver.cpp
Commit 5da0f9ab612d8677c74705521700677966344d48 by Jessica Paquette
[GlobalISel] Fix infinite loop in reassociationCanBreakAddressingModePattern

It didn't update the opcode while walking through G_INTTOPTR/G_PTRTOINT.

Differential Revision: https://reviews.llvm.org/D106080
The file was modifiedllvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/combine-ptradd-reassociation.mir
Commit 99cb2507f3943ec437e95f9a0f3d25f5f3afd7c3 by aeubanks
Revert "[SLP]Workaround for InsertSubVector cost."

This reverts commit 2eb50baf059648214cb1c624b5269978a62e86a1.

Causes hangs, see comments on D105827.
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/pr47629.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/cmp_commute-inseltpoison.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/alternate-calls.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/vec_list_bias-inseltpoison.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/alternate-int-inseltpoison.ll
The file was modifiedllvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/alternate-calls-inseltpoison.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/alternate-int.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/cmp_commute.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/AArch64/accelerate-vector-functions.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/resched.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/vec_list_bias.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/AArch64/accelerate-vector-functions-inseltpoison.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/pr47629-inseltpoison.ll
Commit a35480f85960feccc44ac9a7641070d2a6a78c2f by vyng
[llvm-exegesis] Fix missing-headers build errors.

Details:

Switch all #includes to use <> because that is consistent with what happens in the cmake checks.
Otherwise, we could be in the situation where cmake checks see that headers exist at <perfmon/...>
but in  llvm-exegesis code, we use "perfmon/...", which may not exist.

Related PR/revisions: D84076, PR51017+D105615

    Differential Revision: https://reviews.llvm.org/D105861
The file was modifiedllvm/tools/llvm-exegesis/lib/X86/X86Counter.cpp
The file was modifiedllvm/tools/llvm-exegesis/lib/PerfHelper.cpp
Commit aa3df8ddcd52ec5e40e73cf8d25471145e3913cb by i
[test] Avoid llvm-readelf/llvm-readobj one-dash long options and deprecated aliases (e.g. --file-headers)
The file was modifiedllvm/test/lit.cfg.py
The file was modifiedllvm/test/MC/AMDGPU/reloc.s
The file was modifiedllvm/test/MC/ARM/mappingsymbols.s
The file was modifiedllvm/test/tools/llvm-objcopy/ELF/compress-debug-sections-groups.test
The file was modifiedlld/test/COFF/resource-objs.test
The file was modifiedllvm/test/tools/llvm-objcopy/ELF/group-unchanged.test
The file was modifiedllvm/test/CodeGen/AMDGPU/hsa-metadata-kernel-code-props-v3.ll
The file was modifiedllvm/test/tools/llvm-readobj/ELF/packed-relocs.test
The file was modifiedllvm/test/CodeGen/PowerPC/aix-xcoff-data-sections.ll
The file was modifiedllvm/test/MC/WebAssembly/debug-info64.ll
The file was modifiedllvm/test/tools/llvm-objcopy/ELF/group-big-endian.test
The file was modifiedllvm/test/MC/MachO/loc.s
The file was modifiedllvm/test/MC/AMDGPU/hsa-v4.s
The file was modifiedllvm/test/MC/WebAssembly/func-address.ll
The file was modifiedllvm/test/MC/MachO/reloc-pcrel-offset.s
The file was modifiedcompiler-rt/test/asan/TestCases/Windows/delay_dbghelp.cpp
The file was modifiedllvm/test/CodeGen/AArch64/win64-jumptable.ll
The file was modifiedllvm/test/MC/ELF/comdat-name-number.s
The file was modifiedllvm/test/CodeGen/AMDGPU/code-object-v3.ll
The file was modifiedllvm/test/tools/llvm-objcopy/ELF/strip-dwo-groups.test
The file was modifiedllvm/test/CodeGen/AMDGPU/elf-header-flags-mach.ll
The file was modifiedllvm/test/tools/llvm-objcopy/ELF/group-reorder.test
The file was modifiedllvm/test/tools/obj2yaml/ELF/program-headers.yaml
The file was modifiedllvm/test/tools/yaml2obj/ELF/duplicate-section-names.yaml
The file was modifiedllvm/test/tools/yaml2obj/ELF/comdat-broken.yaml
The file was modifiedllvm/test/MC/AMDGPU/hsa-v3.s
The file was modifiedllvm/test/MC/AMDGPU/hsa-gfx10-v3.s
The file was modifiedllvm/test/tools/llvm-objcopy/ELF/group.test
The file was modifiedllvm/test/CodeGen/AMDGPU/amdgpu-reloc-const.ll
The file was modifiedllvm/test/CodeGen/PowerPC/aix-return55.ll
The file was modifiedllvm/test/CodeGen/PowerPC/aix-xcoff-mergeable-const.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/elf-header-flags-sramecc.ll
The file was modifiedllvm/test/tools/llvm-readobj/ELF/demangle.test
The file was modifiedllvm/test/tools/llvm-readobj/ELF/groups.test
The file was modifiedllvm/test/CodeGen/PowerPC/aix-xcoff-explicit-section.ll
The file was modifiedllvm/test/MC/WebAssembly/debug-info.ll
The file was modifiedllvm/test/DebugInfo/PDB/annotation.test
The file was modifiedllvm/test/tools/llvm-objcopy/MachO/remove-swift-symbols.test
Commit 4628ff4c31b72a62346defee32b8dec9b9adef93 by Louis Dionne
[libc++] NFC: Reindent the run-buildbot script
The file was modifiedlibcxx/utils/ci/run-buildbot
Commit a99d420a937bd7792739767c8bed6d189a444c54 by listmail
[SCEV] Fix unsound reasoning in howManyLessThans

This is split from D105216, it handles only a subset of the cases in that patch.

Specifically, the issue being fixed is that the code incorrectly assumed that (Start-Stide) < End implied that the backedge was taken at least once. This is not true when e.g. Start = 4, Stride = 2, and End = 3. Note that we often do produce the right backedge taken count despite the flawed reasoning.

The fix chosen here is to use an alternate form of uceil (ceiling of unsigned divide) lowering which is safe when max(RHS,Start) > Start - Stride.  (Note that signedness of both max expression and comparison depend on the signedness of the comparison being analyzed, and that overflow in the Start - Stride expression is allowed.)  Note that this is weaker than proving the backedge is taken because it allows start - stride < end < start.  Some cases which can't be proven safe are sent down the generic path, and we do end up generating less optimal expressions in a few cases.

Credit for coming up with the approach goes entirely to Eli.  I just split it off, tweaked the comments a bit, and did some additional testing.

Differential Revision: https://reviews.llvm.org/D105942
The file was modifiedllvm/lib/Analysis/ScalarEvolution.cpp
The file was modifiedllvm/test/Analysis/ScalarEvolution/2008-11-18-Stride2.ll
The file was modifiedllvm/test/Analysis/ScalarEvolution/trip-count-unknown-stride.ll
The file was modifiedllvm/test/Transforms/LoopReroll/nonconst_lb.ll
Commit 7b302fc9b04c7991cdb869b65316e0d72e41042e by dvyukov
tsan: strip top inlined internal frames

The new GET_CURRENT_PC() can lead to spurious top inlined internal frames.
Here are 2 examples from bots, in both cases the malloc is supposed to be
the top frame (#0):

  WARNING: ThreadSanitizer: signal-unsafe call inside of a signal
    #0 __sanitizer::StackTrace::GetNextInstructionPc(unsigned long)
    #1 malloc

  Location is heap block of size 99 at 0xbe3800003800 allocated by thread T1:
    #0 __sanitizer::StackTrace::GetNextInstructionPc(unsigned long)
    #1 malloc

Let's strip these internal top frames from reports.
With other code changes I also observed some top frames
from __tsan::ScopedInterceptor, proactively remove these as well.

Differential Revision: https://reviews.llvm.org/D106081
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_rtl_report.cpp
Commit d2cd3f88e78d01eec19c50ff2da1ed659a2cd210 by llvm-dev
[InstCombine] Add 3-operand gep test with different ptr and same indices
The file was modifiedllvm/test/Transforms/InstCombine/select-gep.ll
Commit 0a614ca22522d6a77356f491a90171b5de916bc7 by llvm-dev
Fix "unknown pragma 'GCC'" MSVC warning. NFCI.
The file was modifiedllvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp
Commit de3956605a701295c928925a3e5096008a8521ba by kamau.bridgeman
[PowerPC] Fix popcntb XL Compat Builtin for 32bit

This patch implements the `__popcntb` XL compatibility builtin for 32bit in the frontend and backend. This patch also updates tests for `__popcntb` and other XL Compat sync related builtins.

Reviewed By: #powerpc, nemanjai, amyk

Differential Revision: https://reviews.llvm.org/D105360
The file was modifiedllvm/lib/Target/PowerPC/PPCInstr64Bit.td
The file was modifiedclang/lib/CodeGen/CGBuiltin.cpp
The file was modifiedclang/test/CodeGen/builtins-ppc-xlcompat-sync.c
The file was modifiedllvm/lib/Target/PowerPC/P9InstrResources.td
The file was addedllvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync-64.ll
The file was modifiedllvm/include/llvm/IR/IntrinsicsPowerPC.td
The file was addedllvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync-32.ll
The file was modifiedllvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-msync.ll
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrInfo.td
The file was removedllvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-sync.ll
Commit ff0ef6a518578231d963c9cdeeae51411efb97d5 by samuel.tebbs
[ARM][LowOverheadLoops] Make some stack spills valid for tail predication

This patch makes vector spills valid for tail predication when all loads
from the same stack slot are within the loop

Differential Revision: https://reviews.llvm.org/D105443
The file was addedllvm/test/CodeGen/Thumb2/LowOverheadLoops/vector_spill_in_loop.mir
The file was modifiedllvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
Commit ecf5813c824cee2e332a2a625ff88d55c8e51b29 by llvm-dev
[InstCombine] Add select(cond,gep(gep(x,y),z),gep(x,y)) tests from PR51069
The file was modifiedllvm/test/Transforms/InstCombine/select-gep.ll
Commit c03d25860a6f57be8e839e0879973b7d4d165333 by nikita.ppv
[Verifier] Use isIntrinsic() (NFC)

Call Function::isIntrinsic() instead of manually checking the
function name for an "llvm." prefix.
The file was modifiedllvm/lib/IR/Verifier.cpp
Commit 80f9fd4ce32b59d055543aef75d651f9ffcda182 by i
[ELF][test] Rework non-preemptible ifunc tests
The file was removedlld/test/ELF/gnu-ifunc.s
The file was removedlld/test/ELF/gnu-ifunc-dynsym.s
The file was addedlld/test/ELF/gnu-ifunc-nonpreemptible.s
Commit f8cb78e99aae9aa3f89f7bfe667db2c5b767f21f by i
[ELF] Don't define __rela_iplt_start for -pie/-shared

`clang -fuse-ld=lld -static-pie -fpie` produced executable
currently crashes and this patch makes it work.

See https://sourceware.org/bugzilla/show_bug.cgi?id=27164
and https://sourceware.org/pipermail/libc-alpha/2021-July/128810.html

While it seems unreasonable to keep csu/libc-start.c ARCH_APPLY_IREL unclear in
static-pie mode and have an unneeded diff -u =(ld.bfd --verbose) =(ld.bfd -pie
--verbose) difference, glibc folks don't want to fix their code.
I feel sad about that but this patch can remove an iffy condition for lld/ELF
as well: `needsInterpSection()`.
The file was modifiedlld/ELF/Writer.cpp
The file was modifiedlld/test/ELF/gnu-ifunc-nonpreemptible.s
Commit 8fb47456a356c5bfe0046a9d1c74cb048a4624bf by Louis Dionne
[libc++/abi] Fix broken Lit feature no-noexcept-function-type

The feature was always defined, which means that the two test cases
guarded by it were never run.

Differential Revision: https://reviews.llvm.org/D106062
The file was modifiedlibcxxabi/test/catch_function_03.pass.cpp
The file was modifiedlibcxxabi/test/catch_member_function_pointer_02.pass.cpp
The file was modifiedlibcxxabi/test/libcxxabi/test/config.py
The file was modifiedlibcxx/utils/libcxx/test/features.py
Commit b980d2f54bb652208eeb9a6543b8d838b65ad099 by listmail
[unittest] Exercise SCEV's udiv and udiv ceiling routines

The ceiling variant was recently added (due to the work towards D105216), and we're spending a lot of time trying to find optimizations for the expression. This patch brute forces the space of i8 unsigned divides and checks that we get a correct (well consistent with APInt) result for both udiv and udiv ceiling.

(This is basically what I've been doing locally in a hand rolled C++ program, and I realized there no good reason not to check it in as a unit test which directly exercises the logic on constants.)

Differential Revision: https://reviews.llvm.org/D106083
The file was modifiedllvm/unittests/Analysis/ScalarEvolutionTest.cpp
The file was modifiedllvm/include/llvm/Analysis/ScalarEvolution.h
Commit c3c324dddf73bfc85034267901fce22002a4bb78 by dvyukov
tsan: lock ScopedErrorReportLock around fork

Currently we don't lock ScopedErrorReportLock around fork
and it mostly works becuase tsan has own report_mtx that
is locked around fork and tsan reports.
However, sanitizer_common code prints some own reports
which are not protected by tsan's report_mtx. So it's better
to lock ScopedErrorReportLock explicitly.

Reviewed By: melver

Differential Revision: https://reviews.llvm.org/D106048
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_symbolizer_report.cpp
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_common.h
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_thread_safety.h
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_rtl.cpp
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_mutex.h
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_thread_registry.h
Commit aaccc985a88db4fb7ae4be341db62bb1fe974102 by Anshil.Gandhi
[M68k][GloballSel] LegalizerInfo implementation

Added rules for G_ADD, G_SUB, G_MUL, G_UDIV to be legal.

Differential Revision: https://reviews.llvm.org/D105536
The file was modifiedllvm/lib/Target/M68k/GlSel/M68kLegalizerInfo.cpp
The file was addedllvm/test/CodeGen/M68k/GlobalISel/arithmetic.ll
Commit d774b4aa5eac785ffe40009091667521e183df40 by tra
[NVPTX, CUDA] Add .and.popc variant of the b1 MMA instruction.

That should allow clang to compile mma.h from CUDA-11.3.

Differential Revision: https://reviews.llvm.org/D105384
The file was modifiedclang/test/CodeGen/builtins-nvptx-mma.cu
The file was modifiedclang/test/CodeGen/builtins-nvptx-mma.py
The file was modifiedllvm/lib/Target/NVPTX/NVPTXInstrInfo.td
The file was modifiedclang/include/clang/Basic/BuiltinsNVPTX.def
The file was modifiedclang/lib/CodeGen/CGBuiltin.cpp
The file was modifiedllvm/include/llvm/IR/IntrinsicsNVVM.td
The file was modifiedllvm/lib/Target/NVPTX/NVPTXIntrinsics.td
The file was modifiedllvm/test/CodeGen/NVPTX/wmma.py
Commit afc760ef3527ef783a9f14f53583df2de8f0bd84 by ajcbik
[mlir][sparse] add int64 storage type to sparse tensor runtime support library

This format was missing from the support library. Although there are some
subtleties reading in an external format for int64 as double, there is no
good reason to omit support for this data type form the support library.

Reviewed By: gussmith23

Differential Revision: https://reviews.llvm.org/D106016
The file was modifiedmlir/lib/ExecutionEngine/SparseUtils.cpp
The file was modifiedmlir/lib/Dialect/SparseTensor/Transforms/SparseTensorConversion.cpp
Commit 66ab8568c485c4dd7461f1acf0e55cd4a7a3b4a0 by harald
[Driver] Fix compiler-rt lookup for x32

x86_64-linux-gnu and x86_64-linux-gnux32 use different ABIs and objects
built for one cannot be used for the other. In order to build and use
compiler-rt for x32, we need to treat x32 as a new arch there. This
updates the driver to search using the new arch name.

Reviewed By: glaubitz

Differential Revision: https://reviews.llvm.org/D100148
The file was modifiedclang/test/Driver/sanitizer-ld.c
The file was modifiedclang/lib/Driver/ToolChain.cpp
Commit 3a7ca4cad4dd42120ea39b919f45a166e85d54a8 by George Burgess IV
utils: fix broken assertion in revert_checker

`intermediate_commits` is a list of full SHAs, and `across_ref` may/may
not be a full SHA (or a SHA at all). We already have `across_sha`, which
is the resolved form of `across_ref`, so use that instead.

Thanks to probinson for catching this in post-commit review of
https://reviews.llvm.org/D105578!
The file was modifiedllvm/utils/revert_checker.py
Commit d5cf437d3a3f496deed21211782f8fc640c688b0 by nikita.ppv
[ObjCARC] Use objc_msgSend instead of llvm.objc.msgSend in tests

D55348 replaced @objc_msgSend with @llvm.objc.msgSend in tests
together with many other objc intrinsics. However, this is not a
recognized objc intrinsic (https://llvm.org/docs/LangRef.html#objective-c-arc-runtime-intrinsics)
and does not receive special treatment by LLVM. It's likely that
uses of this function were renamed by accident.

This came up in D106013, because the address of @llvm.objs.msgSend
is taken, something which is normally not allowed for intrinsics.

Differential Revision: https://reviews.llvm.org/D106094
The file was modifiedllvm/test/Transforms/ObjCARC/move-and-merge-autorelease.ll
The file was modifiedllvm/test/Transforms/ObjCARC/retain-not-declared.ll
The file was modifiedllvm/test/Transforms/ObjCARC/allocas.ll
The file was modifiedllvm/test/Transforms/ObjCARC/invoke.ll
The file was modifiedllvm/test/Transforms/ObjCARC/nested.ll
The file was modifiedllvm/test/Transforms/ObjCARC/ensure-that-exception-unwind-path-is-visited.ll
The file was modifiedllvm/test/Transforms/ObjCARC/path-overflow.ll
The file was modifiedllvm/test/Transforms/ObjCARC/contract-testcases.ll
The file was modifiedllvm/test/Transforms/ObjCARC/invoke-2.ll
The file was modifiedllvm/test/Transforms/ObjCARC/basic.ll
The file was modifiedllvm/test/Transforms/ObjCARC/move-and-form-retain-autorelease.ll
Commit c97cb11efdfacff6231ee058b413df252a8be0d9 by hedingarcia
[libc] Relocate the closing directive of #ifdef

Changed where an #endif was placed because previously it
prevented three macro definitions from being enable in Windows.

Reviewed By: sivachandra

Differential Revision: https://reviews.llvm.org/D106087
The file was modifiedlibc/utils/UnitTest/LibcTest.h
Commit 6596778b46ba69517191e7397289228168064ff4 by martin
[libcxx] [test] Fix mismatches between aligned operator new and std::free

The XFAIL comments about VCRuntime not providing aligned operator new
are outdated; these days VCRuntime does provide them.

However, the tests used to fail on Windows, as the pointers allocated
with an aligned operator new (which is implemented with _aligned_malloc
on Windows) can't be freed using std::free() on Windows (but they need
to be freed with the corresponding function _aligned_free instead).

Instead override the aligned operator new to return a dummy suitably
aligned pointer instead, like other tests that override aligned operator
new.

Also override `operator delete[]` instead of plain `operator delete`
in the array testcase; the fallback from `operator delete[]` to
user defined `operator delete` doesn't work in all DLL build
configurations on Windows.

Also expand the TEST_NOEXCEPT macros, as these tests only are built
in C++17 mode.

By providing the aligned operator new within the tests, this also makes
these test cases pass when testing back deployment on macOS 10.9.

Differential Revision: https://reviews.llvm.org/D105962
The file was modifiedlibcxx/test/std/language.support/support.dynamic/new.delete/new.delete.single/delete_align_val_t_replace.pass.cpp
The file was modifiedlibcxx/test/std/language.support/support.dynamic/new.delete/new.delete.array/delete_align_val_t_replace.pass.cpp
Commit a59165b01778a3b02c510a96951d115d39babd86 by Louis Dionne
[runtimes] Don't try passing --target flags to GCC

When a target triple is specified in CMake via XXX_TARGET_TRIPLE, we tried
passing the --target=<...> flag to the compiler. However, not all compilers
support that flag (e.g. GCC, which is not a cross-compiler). As a result,
setting e.g. LIBCXX_TARGET_TRIPLE=<host-triple> would end up trying to
pass --target=<host-triple> to GCC, which breaks everything because the
flag isn't even supported.

This commit only adds `--target=<...>` & friends to the flags if it is
supported by the compiler.

One could argue that it's confusing to pass LIBCXX_TARGET_TRIPLE=<...>
and have it be ignored. That's correct, and one possibility would be
to assert that the requested triple is the same as the host triple when
we know the compiler is unable to cross-compile. However, note that this
is a pre-existing issue (setting the TARGET_TRIPLE variable never had an
influence on the flags passed to the compiler), and also fixing that is
starting to look like reimplementing a lot of CMake logic that is already
handled with CMAKE_CXX_COMPILER_TARGET.

Differential Revision: https://reviews.llvm.org/D106082
The file was modifiedlibunwind/CMakeLists.txt
The file was modifiedlibcxx/CMakeLists.txt
The file was modifiedlibcxx/cmake/Modules/HandleLibcxxFlags.cmake
The file was modifiedlibcxxabi/CMakeLists.txt
The file was modifiedlibunwind/cmake/Modules/HandleLibunwindFlags.cmake
The file was modifiedlibcxxabi/cmake/Modules/HandleLibcxxabiFlags.cmake
Commit af06f7bcf35f146fd70e4424bbec62dadc4dba70 by zhijian
[AIX][XCOFF][Bug-Fixed] parse the parameter type of the traceback table

Summary:
in the function PPCFunctionInfo::getParmsType(), there is if (Bits > 31 || (Bits > 30 && (Elt != FixedType || hasVectorParms())))

when the Bit is 31 and the Elt is not FixedType(for example the Elt is FloatingType) , the 31th bit will be not encoded, it leave the bit as zero, when the function Expected<SmallString<32>> XCOFF::parseParmsType() the original implement
**// unsigned ParmsNum = FixedParmsNum + FloatingParmsNum;

while (Bits < 32 && ParsedNum < ParmsNum) {
...
}//**
it will look the 31 bits (zero) as FixedType. which should be FloatingType,  and get a error.

Reviewers: Jason Liu,ZarkoCA

Differential Revision: https://reviews.llvm.org/D105023
The file was modifiedllvm/lib/BinaryFormat/XCOFF.cpp
The file was modifiedllvm/test/CodeGen/PowerPC/aix-emit-tracebacktable.ll
Commit 46c8e7122b51960fa1ba100d3efca26411a8aacb by Jessica Paquette
[AArch64][GlobalISel] Clamp <n x p0> vecs when legalizing G_EXTRACT_VECTOR_ELT

This case was missing from G_EXTRACT_VECTOR_ELT. It's the same as for s64.

https://godbolt.org/z/Tnq4acY8z

Differential Revision: https://reviews.llvm.org/D105952
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/legalize-extract-vector-elt.mir
Commit ada580863f8941f8b0426be0d78249f4cfa8f4d5 by sumesh.uk
[mlir] Enable cleanup of single iteration reduction loops being sibling-fused maximally

Changes include the following:
    1. Single iteration reduction loops being sibling fused at innermost insertion level
     are skipped from being considered as sequential loops.
    Otherwise, the slice bounds of these loops is reset.

    2. Promote loops that are skipped in previous step into outer loops.

    3. Two utility function - buildSliceTripCountMap, getSliceIterationCount - are moved from
mlir/lib/Transforms/Utils/LoopFusionUtils.cpp to mlir/lib/Analysis/Utils.cpp

Reviewed By: bondhugula, vinayaka-polymage

Differential Revision: https://reviews.llvm.org/D104249
The file was modifiedmlir/include/mlir/Dialect/Affine/IR/AffineOps.h
The file was modifiedmlir/include/mlir/Analysis/Utils.h
The file was modifiedmlir/include/mlir/Transforms/LoopFusionUtils.h
The file was modifiedmlir/test/Transforms/loop-fusion.mlir
The file was modifiedmlir/lib/Analysis/Utils.cpp
The file was modifiedmlir/lib/Transforms/Utils/LoopFusionUtils.cpp
The file was modifiedmlir/lib/Transforms/LoopFusion.cpp
The file was modifiedmlir/lib/Dialect/Affine/IR/AffineOps.cpp
Commit 803cf7ac0c7be0eb48a99562e99aae578617755a by wei.huang
[PowerPC][NFC] Add the missing 'REQUIRES: powerpc-registered-target.' in the builtins' front end test cases for XL compatibility
The file was modifiedclang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond-64bit-only.c
The file was modifiedclang/test/CodeGen/builtins-ppc-xlcompat-pwr9.c
The file was modifiedclang/test/CodeGen/builtins-ppc-xlcompat-trap-64bit-only.c
The file was modifiedclang/test/CodeGen/builtins-ppc-xlcompat-rotate.c
The file was modifiedclang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c
The file was modifiedclang/test/CodeGen/builtins-ppc-xlcompat-multiply.c
The file was modifiedclang/test/CodeGen/builtins-ppc-xlcompat-pwr9-64bit.c
The file was modifiedclang/test/CodeGen/builtins-ppc-xlcompat-conversionfunc.c
The file was modifiedclang/test/CodeGen/builtins-ppc-xlcompat-trap.c
The file was modifiedclang/test/CodeGen/builtins-ppc-xlcompat-multiply-64bit-only.c
The file was modifiedclang/test/CodeGen/builtins-ppc-xlcompat-sync.c
Commit ff59a1cfe64c0b619c1a8e9ae14406a47897b98d by nikita.ppv
[Verifier] Extend address taken check for unknown intrinsics

Intrinsics can only be called directly, taking their address is not
legal. This is currently only enforced for intrinsics that have an
ID, rather than all intrinsics. Adjust the check to cover all
intrinsics.

This came up in D106013.

Differential Revision: https://reviews.llvm.org/D106095
The file was modifiedllvm/lib/IR/Verifier.cpp
The file was addedllvm/test/Verifier/intrinsic-addr-taken.ll
Commit 81ce3aa30cc275bd7f2b51acf391ab69609ca211 by spatel
[SLP] avoid leaking poison in reduction of safe boolean logic ops

This bug was introduced with D105730 / 25ee55c0baff .

If we are not converting all of the operations of a reduction
into a vector op, we need to preserve the existing select form
of the remaining ops. Otherwise, we are potentially leaking
poison where it did not in the original code.

Alive2 agrees that the version that freezes some inputs
and then falls back to scalar is correct:
https://alive2.llvm.org/ce/z/erF4K2
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/reduction-logical.ll
The file was modifiedllvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
The file was modifiedllvm/test/Transforms/PhaseOrdering/X86/vector-reductions-logical.ll
Commit a8ad9170543906fc58336ab736a109fb42082fbf by harald
[X86] Fix handling of maskmovdqu in X32

The maskmovdqu instruction is an odd one: it has a 32-bit and a 64-bit
variant, the former using EDI, the latter RDI, but the use of the
register is implicit. In 64-bit mode, a 0x67 prefix can be used to get
the version using EDI, but there is no way to express this in
assembly in a single instruction, the only way is with an explicit
addr32.

This change adds support for the instruction. When generating assembly
text, that explicit addr32 will be added. When not generating assembly
text, it will be kept as a single instruction and will be emitted with
that 0x67 prefix. When parsing assembly text, it will be re-parsed as
ADDR32 followed by MASKMOVDQU64, which still results in the correct
bytes when converted to machine code.

The same applies to vmaskmovdqu as well.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D103427
The file was modifiedllvm/lib/Target/X86/Disassembler/X86Disassembler.cpp
The file was modifiedllvm/test/CodeGen/X86/maskmovdqu.ll
The file was modifiedllvm/lib/Target/X86/X86InstrSSE.td
The file was modifiedllvm/include/llvm/Support/X86DisassemblerDecoderCommon.h
The file was modifiedllvm/lib/Target/X86/X86ScheduleBtVer2.td
The file was modifiedllvm/test/CodeGen/X86/sse2-intrinsics-fast-isel.ll
The file was modifiedllvm/utils/TableGen/X86DisassemblerTables.cpp
The file was addedllvm/test/MC/X86/maskmovdqu.s
The file was addedllvm/test/MC/X86/maskmovdqu64.s
The file was modifiedllvm/utils/TableGen/X86RecognizableInstr.cpp
Commit 5d5b08761f944d5b9822d582378333cc4b36a0a7 by efriedma
[DependenceAnalysis] Guard analysis using getPointerBase().

D104806 broke some uses of getMinusSCEV() in DependenceAnalysis:
subtraction with different pointer bases returns a SCEVCouldNotCompute.
Make sure we avoid cases involving such subtractions.

Differential Revision: https://reviews.llvm.org/D106099
The file was addedllvm/test/Analysis/DependenceAnalysis/lcssa.ll
The file was modifiedllvm/lib/Analysis/DependenceAnalysis.cpp
Commit 0321dbc87e43e651c50998701f349d1791fa9cb6 by gclayton
[LLDB][GUI] Add Process Attach form

This patch adds a form window to attach a process, either by PID or by
name. This patch also adds support for dynamic field visibility such
that the form delegate can hide or show certain fields based on some
conditions.

Reviewed By: clayborg

Differential Revision: https://reviews.llvm.org/D105655
The file was modifiedlldb/source/Core/IOHandlerCursesGUI.cpp
Commit 8f053eadbe2712686a917cb703645089cec72d08 by mcgrathr
[libc] Fix typos in x86_64/FEnv.h

Reviewed By: sivachandra

Differential Revision: https://reviews.llvm.org/D106105
The file was modifiedlibc/utils/FPUtil/x86_64/FEnv.h
Commit 4e3dc6b8dd8354308362a5013f722cdf22578cbf by Amara Emerson
GlobalISel: Introduce GenericMachineInstr classes and derivatives for idiomatic LLVM RTTI.

This adds some level of type safety, allows helper functions to be added for
specific opcodes for free, and also allows us to succinctly check for class
membership with the usual dyn_cast/isa/cast functions.

To start off with, add variants for the different load/store operations with some
places using it.

Differential Revision: https://reviews.llvm.org/D105751
The file was addedllvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/Utils.h
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
The file was modifiedllvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
The file was modifiedllvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
Commit ca662297d5fbbf65a19eaa6122d7c12815d8add9 by tianshilei1992
[AbstractAttributor] Fold function calls to `__kmpc_is_spmd_exec_mode` if possible

In the device runtime there are many function calls to `__kmpc_is_spmd_exec_mode`
to query the execution mode of current kernels. In many cases, user programs
only contain target region executing in one mode. As a consequence, those runtime
function calls will only return one value. If we can get rid of these function
calls during compliation, it can potentially improve performance.

In this patch, we use `AAKernelInfo` to analyze kernel execution. Basically, for
each kernel (device) function `F`, we collect all kernel entries `K` that can
reach `F`. A new AA, `AAFoldRuntimeCall`, is created for each call site. In each
iteration, it will check all reaching kernel entries, and update the folded value
accordingly.

In the future we will support more function.

Reviewed By: jdoerfert

Differential Revision: https://reviews.llvm.org/D105787
The file was modifiedllvm/lib/Transforms/IPO/OpenMPOpt.cpp
The file was modifiedllvm/test/Transforms/OpenMP/custom_state_machines.ll
The file was addedllvm/test/Transforms/OpenMP/is_spmd_exec_mode_fold.ll
Commit 4eb107ccbad791098494c26dfc1d423ecf558ef7 by wei.huang
[PowerPC] Add PowerPC population count, reversed load and store related builtins and instrinsics for XL compatibility

This patch is in a series of patches to provide builtins for compatibility
with the XL compiler. This patch adds the builtins and instrisics for population
count, reversed load and store related operations.

Reviewed By: nemanjai, #powerpc

Differential revision: https://reviews.llvm.org/D106021
The file was addedclang/test/CodeGen/builtins-ppc-xlcompat-load-store-reversed.c
The file was addedllvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-popcnt.ll
The file was modifiedllvm/include/llvm/IR/IntrinsicsPowerPC.td
The file was addedllvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-load-store-reversed.ll
The file was modifiedclang/lib/Basic/Targets/PPC.cpp
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrInfo.td
The file was addedllvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-load-store-reversed-64bit-only.ll
The file was modifiedclang/lib/Sema/SemaChecking.cpp
The file was modifiedclang/include/clang/Basic/BuiltinsPPC.def
The file was addedclang/test/CodeGen/builtins-ppc-xlcompat-load-store-reversed-64bit-only.c
The file was modifiedclang/lib/CodeGen/CGBuiltin.cpp
The file was addedclang/test/CodeGen/builtins-ppc-xlcompat-popcnt.c
The file was modifiedllvm/lib/Target/PowerPC/PPCInstr64Bit.td
Commit bba8a76b8736fcf005ebbd0a4fb789a22eadf9ba by Vitaly Buka
[NFC][hwasan] Remove default arguments in internal class
The file was modifiedllvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp
Commit 2e7ec447cc7eab89a72413ad91a897049f551c56 by Raphael Isemann
[lldb] Add AllocateMemory/DeallocateMemory to the SBProcess API

This change adds AllocateMemory and DeallocateMemory methods to the SBProcess
API, so that clients can allocate and deallocate memory blocks within the
process being debugged (for storing JIT-compiled code or other uses).

(I am developing a debugger + REPL using the API; it will need to store
JIT-compiled code within the target.)

Reviewed By: clayborg, jingham

Differential Revision: https://reviews.llvm.org/D105389
The file was modifiedlldb/test/API/python_api/process/main.cpp
The file was modifiedlldb/test/API/python_api/process/TestProcessAPI.py
The file was modifiedlldb/include/lldb/API/SBProcess.h
The file was modifiedlldb/bindings/interface/SBProcess.i
The file was modifiedlldb/source/API/SBProcess.cpp
Commit e91da668d00c1edbe224ecf34c106687a2a47db0 by Matthew.Arsenault
GlobalISel: Track argument pointeriness with arg flags

Since we're still building on top of the MVT based infrastructure, we
need to track the pointer type/address space on the side so we can end
up with the correct pointer LLTs when interpreting CCValAssigns.
The file was modifiedllvm/test/CodeGen/X86/GlobalISel/GV.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-function-args.ll
The file was modifiedllvm/test/CodeGen/X86/GlobalISel/frameIndex.ll
The file was modifiedllvm/test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll
The file was modifiedllvm/test/CodeGen/X86/GlobalISel/irtranslator-callingconv.ll
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/CallLowering.h
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
The file was modifiedllvm/test/CodeGen/Mips/GlobalISel/irtranslator/pointers.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll
The file was modifiedllvm/test/CodeGen/ARM/GlobalISel/irtranslator-varargs-lowering.ll
The file was modifiedllvm/lib/CodeGen/GlobalISel/CallLowering.cpp
The file was addedllvm/test/CodeGen/X86/GlobalISel/x32-irtranslator.ll
The file was modifiedllvm/test/CodeGen/ARM/GlobalISel/arm-param-lowering.ll
Commit a81a7a9ad81969bce757fbf7a6ebe94a946902d2 by Matthew.Arsenault
AMDGPU/GlobalISel: Fix incorrect memory types in test
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-global.mir
Commit a2d7ace3e3e9804c5b616be402f37b21549db80e by Matthew.Arsenault
GlobalISel: Surface offsets parameter from ComputeValueVTs
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/CallLowering.h
The file was modifiedllvm/lib/CodeGen/GlobalISel/CallLowering.cpp
Commit 557855e047aea53023165756586697c0f1cbc3ce by thakis
Revert "tsan: make obtaining current PC faster"

This reverts commit e33446ea58b8357dd8b79eb39140a1de2baff1ae.
Doesn't build on mac, and causes other problems. See reports
on https://reviews.llvm.org/D106046 and https://reviews.llvm.org/D106081

Also revert follow-up "tsan: strip top inlined internal frames"
This reverts commit 7b302fc9b04c7991cdb869b65316e0d72e41042e.
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_rtl_report.cpp
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_interceptors_posix.cpp
The file was modifiedcompiler-rt/lib/tsan/rtl/tsan_interceptors.h
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_stacktrace.h
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_stacktrace.cpp
Commit 7139497656147275156e7242a8bf08794af9130a by kstoimenov
[asan] Slightly modified the documentation.

The goal of this change is to test if I can commit changes.

Reviewed By: kcc

Differential Revision: https://reviews.llvm.org/D106101
The file was modifiedclang/docs/AddressSanitizer.rst
Commit f2b1264141b02efb1ba76b6eb7a7d2fff6d4c21a by leevince
[lld-macho] Use intermediate arrays to store opcodes

We want to incorporate some of the optimization passes in bind opcodes from ld64.
This revision makes no functional changes but to start storing opcodes in intermediate
containers in preparation for implementing the optimization passes in a follow-up revision.

Differential Revision: https://reviews.llvm.org/D105866
The file was modifiedlld/MachO/SyntheticSections.cpp
Commit 108a320a58b13f7adc238d91ab1895ad4569df7a by weiwei.li1
[mlir][spirv] Add support for GLSL FMix

Add spv.GLSL.FMix opertaion.

co-authered-by: Alan Liu <alanliu.yf@gmail.com>

Reviewed By: mravishankar

Differential Revision: https://reviews.llvm.org/D104153
The file was modifiedmlir/test/Target/SPIRV/glsl-ops.mlir
The file was modifiedmlir/include/mlir/Dialect/SPIRV/IR/SPIRVGLSLOps.td
The file was modifiedmlir/test/Dialect/SPIRV/IR/glsl-ops.mlir
Commit 3c4023b225ace3a5c0ed23bc491b47c9dad4353c by danielrodriguez
[test] Use double pound to denote comments.

Use double pound at the start of the line to differentiate comments from
statements for Lit or FileCheck.

I will also use this small commit to check my commit access.

Differential Revision: https://reviews.llvm.org/D106103
The file was modifiedllvm/test/tools/llvm-objcopy/grouped-options.test
Commit 766a08df12c111b15ed51d0fcac06042d2f68cd6 by vsapsai
[Frontend] Only compile modules if not already finalized

It was possible to re-add a module to a shared in-memory module cache
when search paths are changed. This can eventually cause a crash if the
original module is referenced after this occurs.
  1. Module A depends on B
  2. B exists in two paths C and D
  3. First run only has C on the search path, finds A and B and loads
     them
  4. Second run adds D to the front of the search path. A is loaded and
     contains a reference to the already compiled module from C. But
     searching finds the module from D instead, causing a mismatch
  5. B and the modules that depend on it are considered out of date and
     thus rebuilt
  6. The recompiled module A is added to the in-memory cache, freeing
     the previously inserted one

This can never occur from a regular clang process, but is very easy to
do through the API - whether through the use of a shared case or just
running multiple compilations from a single `CompilerInstance`. Update
the compilation to return early if a module is already finalized so that
the pre-condition in the in-memory module cache holds.

Resolves rdar://78180255

Differential Revision: https://reviews.llvm.org/D105328
The file was addedclang/unittests/Serialization/ModuleCacheTest.cpp
The file was modifiedclang/lib/Frontend/CompilerInstance.cpp
The file was modifiedclang/unittests/Serialization/CMakeLists.txt
The file was modifiedclang/include/clang/Basic/DiagnosticCommonKinds.td
The file was modifiedclang/include/clang/Basic/DiagnosticSerializationKinds.td
The file was modifiedclang/lib/Serialization/ASTReader.cpp
The file was modifiedclang/include/clang/Serialization/ASTReader.h
Commit 851a335b1e64d0d32e15a8d2ace48c9b0967cd5a by Louis Dionne
[libc++] Add a job running GCC with C++11

This configuration is interesting because GCC has a different level of
strictness for some C++ rules. In particular, it implements the older
standards more stringently than Clang, which can help find places where
we are non-conforming (especially in the test suite).

Differential Revision: https://reviews.llvm.org/D105936
The file was modifiedlibcxxabi/test/unwind_02.pass.cpp
The file was modifiedlibcxxabi/test/unwind_05.pass.cpp
The file was modifiedlibcxx/test/std/input.output/file.streams/c.files/cstdio.pass.cpp
The file was modifiedlibcxx/test/support/test_macros.h
The file was modifiedlibcxx/test/std/utilities/smartptr/unique.ptr/unique.ptr.class/unique.ptr.ctor/auto_pointer.pass.cpp
The file was modifiedlibcxx/utils/ci/run-buildbot
The file was modifiedlibcxxabi/test/unwind_04.pass.cpp
The file was modifiedlibcxxabi/test/unwind_03.pass.cpp
The file was modifiedlibcxx/test/std/atomics/atomics.types.operations/atomics.types.operations.req/atomic_is_lock_free.pass.cpp
The file was modifiedlibcxx/utils/ci/buildkite-pipeline.yml
The file was modifiedlibcxx/test/std/depr/depr.auto.ptr/auto.ptr/AB.h
The file was modifiedlibcxx/test/std/strings/string.view/string.view.ops/copy.pass.cpp
The file was modifiedlibcxx/test/std/depr/depr.auto.ptr/auto.ptr/A.h
Commit 97c8f60bbaf0986320fdfd03b11328b91c730a96 by tianshilei1992
[NFC][OpenMP][Offloading] Replaced explicit parallel level computation with function `__kmpc_parallel_level`

There are two places in current deviceRTLs where it computes parallel level explicitly,
which is basically the functionality of `__kmpc_parallel_level`. Starting from
D105787, we plan to introduce a series of function call folding based on information
that can be deducted during compilation time. Computation of parallel level is
the next target. This patch makes steps for the optimization.

Reviewed By: jdoerfert

Differential Revision: https://reviews.llvm.org/D105955
The file was modifiedopenmp/libomptarget/deviceRTLs/common/src/support.cu
The file was modifiedopenmp/libomptarget/deviceRTLs/interface.h
The file was modifiedopenmp/libomptarget/deviceRTLs/common/src/libcall.cu
The file was modifiedopenmp/libomptarget/deviceRTLs/common/src/parallel.cu
Commit 18d8779747951d07fcc88de2283aceff602bc3c5 by thakis
[gn build] port 766a08df12c1
The file was modifiedllvm/utils/gn/secondary/clang/unittests/Serialization/BUILD.gn
Commit b1ffa8fc61a72f9bd0abc0ab8e61fbad31161eca by llvmgnsyncbot
[gn build] Port 766a08df12c1
The file was modifiedllvm/utils/gn/secondary/clang/unittests/Serialization/BUILD.gn
Commit b4c93ece8e4f6e98a15daca10c8a3db33cf8c195 by john.demme
[MLIR] [Python ODS] Use @builtins.property for cases where 'property' is already defined

In cases where an operation has an argument or result named 'property', the
ODS-generated python fails on import because the `@property` resolves to the
`property` operation argument instead of the builtin `@property` decorator. We
should always use the fully qualified decorator name.

Reviewed By: mikeurbach

Differential Revision: https://reviews.llvm.org/D106106
The file was modifiedmlir/test/python/python_test_ops.td
The file was modifiedmlir/tools/mlir-tblgen/OpPythonBindingGen.cpp
The file was modifiedmlir/test/mlir-tblgen/op-python-bindings.td
Commit 42f588f39c5ce6f521e3709b8871d1fdd076292f by joker.eph
Use ManagedStatic and lazy initialization of cl::opt in libSupport to make it free of global initializer

We can build it with -Werror=global-constructors now. This helps
in situation where libSupport is embedded as a shared library,
potential with dlopen/dlclose scenario, and when command-line
parsing or other facilities may not be involved. Avoiding the
implicit construction of these cl::opt can avoid double-registration
issues and other kind of behavior.

Reviewed By: lattner, jpienaar

Differential Revision: https://reviews.llvm.org/D105959
The file was modifiedllvm/lib/Support/Windows/Signals.inc
The file was modifiedllvm/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp
The file was modifiedllvm/lib/Support/Debug.cpp
The file was modifiedllvm/lib/Support/TimeProfiler.cpp
The file was modifiedclang-tools-extra/clangd/indexer/IndexerMain.cpp
The file was modifiedclang/tools/clang-refactor/ClangRefactor.cpp
The file was modifiedllvm/include/llvm/Support/ARMBuildAttributes.h
The file was modifiedllvm/lib/Support/TypeSize.cpp
The file was modifiedllvm/unittests/Support/RISCVAttributeParserTest.cpp
The file was modifiedllvm/include/llvm/Support/RISCVAttributeParser.h
The file was modifiedllvm/tools/llvm-dwarfdump/llvm-dwarfdump.cpp
The file was modifiedllvm/lib/Support/GraphWriter.cpp
The file was modifiedllvm/unittests/Support/ARMAttributeParser.cpp
The file was modifiedllvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
The file was modifiedllvm/include/llvm/Support/ARMAttributeParser.h
The file was modifiedllvm/lib/Support/DebugCounter.cpp
The file was modifiedllvm/docs/CommandLine.rst
The file was modifiedllvm/lib/Support/ELFAttributeParser.cpp
The file was modifiedllvm/include/llvm/Support/CommandLine.h
The file was modifiedllvm/unittests/Support/CommandLineTest.cpp
The file was modifiedllvm/lib/Support/ARMBuildAttrs.cpp
The file was modifiedllvm/include/llvm/Support/RISCVAttributes.h
The file was modifiedllvm/include/llvm/Support/WithColor.h
The file was modifiedllvm/lib/Support/RandomNumberGenerator.cpp
The file was modifiedllvm/tools/llvm-libtool-darwin/llvm-libtool-darwin.cpp
The file was modifiedllvm/lib/Support/Timer.cpp
The file was modifiedllvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
The file was addedllvm/lib/Support/DebugOptions.h
The file was modifiedllvm/lib/Support/CommandLine.cpp
The file was modifiedllvm/lib/Support/WithColor.cpp
The file was modifiedllvm/lib/Support/Statistic.cpp
The file was modifiedllvm/include/llvm/Support/ScopedPrinter.h
The file was modifiedllvm/lib/Support/RISCVAttributes.cpp
The file was modifiedllvm/lib/Support/Signals.cpp
The file was modifiedclang-tools-extra/clangd/index/dex/dexp/Dexp.cpp
Commit 16b5e9d6a269913e8da0fa037e8af32eaf304c8f by joker.eph
Revert "Use ManagedStatic and lazy initialization of cl::opt in libSupport to make it free of global initializer"

This reverts commit 42f588f39c5ce6f521e3709b8871d1fdd076292f.
Broke some buildbots
The file was modifiedllvm/lib/Support/TimeProfiler.cpp
The file was modifiedllvm/lib/Support/WithColor.cpp
The file was modifiedllvm/tools/llvm-libtool-darwin/llvm-libtool-darwin.cpp
The file was modifiedllvm/include/llvm/Support/RISCVAttributes.h
The file was modifiedllvm/lib/Support/RandomNumberGenerator.cpp
The file was modifiedllvm/lib/Support/ARMBuildAttrs.cpp
The file was modifiedllvm/lib/Support/Debug.cpp
The file was modifiedllvm/tools/llvm-dwarfdump/llvm-dwarfdump.cpp
The file was removedllvm/lib/Support/DebugOptions.h
The file was modifiedllvm/lib/Support/Windows/Signals.inc
The file was modifiedllvm/include/llvm/Support/ScopedPrinter.h
The file was modifiedllvm/lib/Support/Timer.cpp
The file was modifiedllvm/unittests/Support/ARMAttributeParser.cpp
The file was modifiedclang-tools-extra/clangd/indexer/IndexerMain.cpp
The file was modifiedllvm/lib/Support/GraphWriter.cpp
The file was modifiedllvm/lib/Support/Signals.cpp
The file was modifiedllvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
The file was modifiedllvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
The file was modifiedclang/tools/clang-refactor/ClangRefactor.cpp
The file was modifiedllvm/lib/Support/ELFAttributeParser.cpp
The file was modifiedllvm/docs/CommandLine.rst
The file was modifiedllvm/lib/Support/DebugCounter.cpp
The file was modifiedllvm/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp
The file was modifiedllvm/lib/Support/CommandLine.cpp
The file was modifiedllvm/unittests/Support/CommandLineTest.cpp
The file was modifiedllvm/unittests/Support/RISCVAttributeParserTest.cpp
The file was modifiedllvm/include/llvm/Support/RISCVAttributeParser.h
The file was modifiedllvm/include/llvm/Support/WithColor.h
The file was modifiedllvm/include/llvm/Support/ARMAttributeParser.h
The file was modifiedllvm/lib/Support/Statistic.cpp
The file was modifiedllvm/lib/Support/TypeSize.cpp
The file was modifiedclang-tools-extra/clangd/index/dex/dexp/Dexp.cpp
The file was modifiedllvm/lib/Support/RISCVAttributes.cpp
The file was modifiedllvm/include/llvm/Support/ARMBuildAttributes.h
The file was modifiedllvm/include/llvm/Support/CommandLine.h
Commit c23da666b5be4da631c2ff8db4d129a90f319777 by tianshilei1992
[Attributor] Add support for compound assignment for ChangeStatus

A common use of `ChangeStatus` is as follows:
```
ChangeStatus Changed = ChangeStatus::UNCHANGED;
Changed |= foo();
```
where `foo` returns `ChangeStatus` as well. Currently `ChangeStatus` doesn't
support compound assignment, we have to write as
```
Changed = Changed | foo();
```
which is not that convenient.

This patch add the support for compound assignment for `ChangeStatus`. Compound
assignment is usually implemented as a member function, and binary arithmetic
operator is therefore implemented using compound assignment. However, unlike
regular C++ class, enum class doesn't support member functions. As a result, they
can only be implemented in the way shown in the patch.

Reviewed By: jdoerfert

Differential Revision: https://reviews.llvm.org/D106109
The file was modifiedllvm/include/llvm/Transforms/IPO/Attributor.h
The file was modifiedllvm/lib/Transforms/IPO/Attributor.cpp
The file was modifiedllvm/lib/Transforms/IPO/OpenMPOpt.cpp
Commit d695d0d6f60528841ab8671cdccff85f889ca95d by leevince
[lld-macho] Optimize bind opcodes with multiple passes

In D105866, we used an intermediate container to store a list of opcodes. Here,
we use that data structure to help us perform optimization passes that would allow
a more efficient encoding of bind opcodes. Currently, the functionality mirrors the
optimization pass {1,2} done in ld64 for bind opcodes under optimization gate
to prevent slight regressions.

Reviewed By: int3, #lld-macho

Differential Revision: https://reviews.llvm.org/D105867
The file was modifiedlld/MachO/SyntheticSections.cpp
The file was modifiedlld/test/MachO/bind-opcodes.s
The file was modifiedlld/MachO/Config.h
The file was modifiedlld/MachO/Driver.cpp
The file was modifiedlld/MachO/Options.td
Commit f5917e0312edacf1fe4cfebc532e3a78c854adee by carl.ritson
[TableGen] Allow isAllocatable inheritence from any superclass

When setting Allocatable on a generated register class check all
superclasses and set Allocatable true if any superclass is
allocatable.

Without this change generated register classes based on an
allocatable class may end up unallocatable due to the topological
inheritance order.

This change primarily effects AMDGPU backend; however, there are
a few changes in MIPs GlobalISel register constraints as a result.

Reviewed By: kparzysz

Differential Revision: https://reviews.llvm.org/D105967
The file was modifiedllvm/utils/TableGen/CodeGenRegisters.cpp
Commit 48688257c52dfc2c666b64730f0467c2cc38210c by deep.majumder2019
[analyzer] Model comparision methods of std::unique_ptr

This patch handles all the comparision methods (defined via overloaded
operators) on std::unique_ptr. These operators compare the underlying
pointers, which is modelled by comparing the corresponding inner-pointer
SVal. There is also a special case for comparing the same pointer.

Differential Revision: https://reviews.llvm.org/D104616
The file was modifiedclang/include/clang/StaticAnalyzer/Core/PathSensitive/CheckerHelpers.h
The file was modifiedclang/lib/StaticAnalyzer/Checkers/SmartPtr.h
The file was modifiedclang/lib/StaticAnalyzer/Core/CheckerHelpers.cpp
The file was modifiedclang/test/Analysis/Inputs/system-header-simulator-cxx.h
The file was modifiedclang/lib/StaticAnalyzer/Checkers/SmartPtrModeling.cpp
The file was modifiedclang/test/Analysis/smart-ptr.cpp
Commit f98ed74f6910f8b09e77497aeb30c860c433610d by mkazantsev
[LSR] Handle case 1*reg => reg. PR50918

This patch addresses assertion failure in case when the only found formula for LSR
is `1*reg => reg` which was supposed to be an impossible situation, however there
is a test that shows it is possible.

In this case, we can use scale register with scale of 1 as the missing base register.

Reviewed By: huihuiz, reames
Differential Revision: https://reviews.llvm.org/D105009
The file was modifiedllvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
The file was addedllvm/test/Transforms/LoopStrengthReduce/pr50918.ll
Commit 39a36999f9b4d6eb5bedbce1d6d54156b8cdf6bf by sepavloff
Fix typo in test
The file was modifiedllvm/test/Transforms/InstSimplify/fdiv-strictfp.ll
Commit 25dade54d3ece60dc9fb8f9960e4a558e85f7ae9 by phosek
[profile] Decommit memory after counter relocation

After we relocate counters, we no longer need to keep the original copy
around so we can return the memory back to the operating system.

Differential Revision: https://reviews.llvm.org/D104839
The file was modifiedcompiler-rt/lib/profile/InstrProfilingPlatformFuchsia.c
The file was modifiedcompiler-rt/lib/profile/InstrProfilingUtil.h
The file was modifiedcompiler-rt/lib/profile/WindowsMMap.h
The file was modifiedcompiler-rt/lib/profile/InstrProfilingUtil.c
The file was modifiedcompiler-rt/lib/profile/InstrProfilingFile.c
The file was modifiedcompiler-rt/lib/profile/WindowsMMap.c
Commit b5a84e214d49c56d13dc1fb76273f575e6752c68 by Jonas Devlieghere
[debugserver] Un-conditionalize code guarded by macOS 10.10 checks

We've been requiring macOS 10.11 since 2018 so there's no point in
keeping code for 10.10 around.
The file was modifiedlldb/tools/debugserver/source/MacOSX/MachProcess.mm
The file was modifiedlldb/tools/debugserver/source/RNBRemote.cpp
Commit 20113d66c7bfe935cf2b300fc6cc3ef996bb847d by joker.eph
Fix mismatch between the provisioning of asyncExecutors and the actual thread count currently in the context (NFC)

This fixes an assert in some deployment where the threadpool is
customized.
The file was modifiedmlir/lib/Pass/Pass.cpp
Commit af9321739b20becf170e6bb5060b8d780e1dc8dd by joker.eph
Use ManagedStatic and lazy initialization of cl::opt in libSupport to make it free of global initializer

We can build it with -Werror=global-constructors now. This helps
in situation where libSupport is embedded as a shared library,
potential with dlopen/dlclose scenario, and when command-line
parsing or other facilities may not be involved. Avoiding the
implicit construction of these cl::opt can avoid double-registration
issues and other kind of behavior.

Reviewed By: lattner, jpienaar

Differential Revision: https://reviews.llvm.org/D105959
The file was modifiedllvm/include/llvm/Support/RISCVAttributes.h
The file was modifiedllvm/lib/Support/Statistic.cpp
The file was modifiedllvm/docs/CommandLine.rst
The file was modifiedllvm/lib/Support/ELFAttributeParser.cpp
The file was modifiedllvm/lib/Support/TypeSize.cpp
The file was modifiedclang-tools-extra/clangd/index/dex/dexp/Dexp.cpp
The file was modifiedclang/tools/clang-refactor/ClangRefactor.cpp
The file was modifiedllvm/unittests/Support/ARMAttributeParser.cpp
The file was modifiedllvm/tools/llvm-libtool-darwin/llvm-libtool-darwin.cpp
The file was modifiedllvm/include/llvm/Support/ARMAttributeParser.h
The file was modifiedllvm/tools/llvm-dwarfdump/llvm-dwarfdump.cpp
The file was modifiedllvm/lib/Support/Timer.cpp
The file was modifiedllvm/lib/Support/TimeProfiler.cpp
The file was modifiedllvm/unittests/Support/RISCVAttributeParserTest.cpp
The file was modifiedllvm/lib/Support/Signals.cpp
The file was modifiedllvm/lib/Support/Windows/Signals.inc
The file was modifiedllvm/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp
The file was modifiedllvm/lib/Support/CommandLine.cpp
The file was modifiedllvm/include/llvm/Support/ScopedPrinter.h
The file was modifiedllvm/lib/Support/ARMBuildAttrs.cpp
The file was modifiedllvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
The file was modifiedllvm/include/llvm/Support/ARMBuildAttributes.h
The file was modifiedllvm/lib/Support/Debug.cpp
The file was modifiedllvm/lib/Support/GraphWriter.cpp
The file was modifiedllvm/lib/Support/RandomNumberGenerator.cpp
The file was modifiedllvm/lib/Support/DebugCounter.cpp
The file was modifiedllvm/include/llvm/Support/CommandLine.h
The file was modifiedllvm/include/llvm/Support/WithColor.h
The file was modifiedllvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
The file was modifiedllvm/unittests/Support/CommandLineTest.cpp
The file was addedllvm/lib/Support/DebugOptions.h
The file was modifiedllvm/tools/llvm-bcanalyzer/llvm-bcanalyzer.cpp
The file was modifiedllvm/lib/Support/RISCVAttributes.cpp
The file was modifiedllvm/include/llvm/Support/RISCVAttributeParser.h
The file was modifiedllvm/lib/Support/WithColor.cpp
The file was modifiedclang-tools-extra/clangd/indexer/IndexerMain.cpp
Commit 13fe78212fe7fa3a4491ffbbac6f0c58cb1e0573 by deep.majumder2019
[analyzer] Handle << operator for std::unique_ptr

    This patch handles the `<<` operator defined for `std::unique_ptr` in
    the std namespace (ignores custom overloads of the operator).

    Differential Revision: https://reviews.llvm.org/D105421
The file was modifiedclang/lib/StaticAnalyzer/Checkers/SmartPtrModeling.cpp
The file was modifiedclang/test/Analysis/Inputs/system-header-simulator-cxx.h
The file was modifiedclang/test/Analysis/smart-ptr.cpp
Commit 77f2f0f9b7c7c1bd56879c86a0c63ffdd5e8166e by marcos.horro
[llvm-mca][JSON] Store extra information about driver flags used for the simulation

Added information stored in PipelineOptions and the MCSubtargetInfo.

Bug: https://bugs.llvm.org/show_bug.cgi?id=51041

Reviewed By: andreadb

Differential Revision: https://reviews.llvm.org/D106077
The file was modifiedllvm/tools/llvm-mca/PipelinePrinter.cpp
The file was modifiedllvm/tools/llvm-mca/llvm-mca.cpp
The file was modifiedllvm/test/tools/llvm-mca/JSON/X86/instruction-tables-multiple-regions.s
The file was modifiedllvm/test/tools/llvm-mca/JSON/X86/views.s
The file was modifiedllvm/test/tools/llvm-mca/JSON/X86/views-multiple-region.s
The file was modifiedllvm/tools/llvm-mca/PipelinePrinter.h
The file was addedllvm/test/tools/llvm-mca/JSON/X86/views-custom-parameters.s
The file was modifiedllvm/test/tools/llvm-mca/JSON/X86/views-multiple-anonymous-regions.s
The file was modifiedllvm/test/tools/llvm-mca/JSON/X86/instruction-tables-multiple-anonymous-regions.s
Commit 7c63726072005cc331bb21694c9022e6d18a3b93 by tbaeder
[llvm][tools] Hide unrelated llvm-cfi-verify options

Differential Revision: https://reviews.llvm.org/D106055
The file was modifiedllvm/tools/llvm-cfi-verify/llvm-cfi-verify.cpp
The file was addedllvm/test/tools/llvm-cfi-verify/help.test
Commit 3d3dc9523f9b2ec9d83d37bd8a757726f37b6ee5 by tbaeder
Revert "[llvm][tools] Hide unrelated llvm-cfi-verify options"

This reverts commit 7c63726072005cc331bb21694c9022e6d18a3b93.
The file was modifiedllvm/tools/llvm-cfi-verify/llvm-cfi-verify.cpp
The file was removedllvm/test/tools/llvm-cfi-verify/help.test
Commit 8d051d854619956de633047409149cdab1e3319a by joker.eph
Revert "Use ManagedStatic and lazy initialization of cl::opt in libSupport to make it free of global initializer"

This reverts commit af9321739b20becf170e6bb5060b8d780e1dc8dd.
Still some specific config broken in some way that requires more
investigation.
The file was modifiedllvm/lib/Support/Windows/Signals.inc
The file was modifiedllvm/unittests/Support/RISCVAttributeParserTest.cpp
The file was modifiedllvm/include/llvm/Support/ARMBuildAttributes.h
The file was modifiedllvm/lib/Support/RandomNumberGenerator.cpp
The file was modifiedllvm/lib/Support/GraphWriter.cpp
The file was modifiedclang-tools-extra/clangd/index/dex/dexp/Dexp.cpp
The file was modifiedllvm/include/llvm/Support/RISCVAttributes.h
The file was modifiedllvm/include/llvm/Support/RISCVAttributeParser.h
The file was modifiedclang/tools/clang-refactor/ClangRefactor.cpp
The file was modifiedllvm/lib/Support/ELFAttributeParser.cpp
The file was modifiedclang-tools-extra/clangd/indexer/IndexerMain.cpp
The file was removedllvm/lib/Support/DebugOptions.h
The file was modifiedllvm/tools/llvm-bcanalyzer/llvm-bcanalyzer.cpp
The file was modifiedllvm/include/llvm/Support/CommandLine.h
The file was modifiedllvm/lib/Support/Debug.cpp
The file was modifiedllvm/lib/Support/RISCVAttributes.cpp
The file was modifiedllvm/lib/Support/TypeSize.cpp
The file was modifiedllvm/include/llvm/Support/WithColor.h
The file was modifiedllvm/docs/CommandLine.rst
The file was modifiedllvm/lib/Support/CommandLine.cpp
The file was modifiedllvm/lib/Support/Statistic.cpp
The file was modifiedllvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
The file was modifiedllvm/tools/llvm-libtool-darwin/llvm-libtool-darwin.cpp
The file was modifiedllvm/lib/Support/Signals.cpp
The file was modifiedllvm/lib/Support/TimeProfiler.cpp
The file was modifiedllvm/lib/Support/Timer.cpp
The file was modifiedllvm/lib/Support/DebugCounter.cpp
The file was modifiedllvm/unittests/Support/CommandLineTest.cpp
The file was modifiedllvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
The file was modifiedllvm/lib/Support/WithColor.cpp
The file was modifiedllvm/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp
The file was modifiedllvm/unittests/Support/ARMAttributeParser.cpp
The file was modifiedllvm/lib/Support/ARMBuildAttrs.cpp
The file was modifiedllvm/tools/llvm-dwarfdump/llvm-dwarfdump.cpp
The file was modifiedllvm/include/llvm/Support/ARMAttributeParser.h
The file was modifiedllvm/include/llvm/Support/ScopedPrinter.h
Commit 76374573ce829b083b95b74937a11e9b91f8f45f by joker.eph
Use ManagedStatic and lazy initialization of cl::opt in libSupport to make it free of global initializer

We can build it with -Werror=global-constructors now. This helps
in situation where libSupport is embedded as a shared library,
potential with dlopen/dlclose scenario, and when command-line
parsing or other facilities may not be involved. Avoiding the
implicit construction of these cl::opt can avoid double-registration
issues and other kind of behavior.

Reviewed By: lattner, jpienaar

Differential Revision: https://reviews.llvm.org/D105959
The file was modifiedclang/tools/clang-refactor/ClangRefactor.cpp
The file was modifiedllvm/include/llvm/Support/ARMBuildAttributes.h
The file was modifiedllvm/lib/Support/WithColor.cpp
The file was modifiedllvm/lib/Support/TypeSize.cpp
The file was modifiedllvm/lib/Support/Debug.cpp
The file was modifiedllvm/lib/Support/ELFAttributeParser.cpp
The file was modifiedllvm/lib/Support/CommandLine.cpp
The file was modifiedllvm/unittests/Support/ARMAttributeParser.cpp
The file was modifiedllvm/lib/Support/GraphWriter.cpp
The file was modifiedllvm/lib/Support/DebugCounter.cpp
The file was modifiedllvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
The file was modifiedllvm/lib/Support/Windows/Signals.inc
The file was modifiedllvm/include/llvm/Support/RISCVAttributeParser.h
The file was modifiedllvm/include/llvm/Support/RISCVAttributes.h
The file was modifiedllvm/lib/Support/ARMBuildAttrs.cpp
The file was addedllvm/lib/Support/DebugOptions.h
The file was modifiedllvm/lib/Support/Signals.cpp
The file was modifiedllvm/include/llvm/Support/ScopedPrinter.h
The file was modifiedllvm/lib/Support/Timer.cpp
The file was modifiedllvm/lib/Support/RISCVAttributes.cpp
The file was modifiedllvm/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp
The file was modifiedllvm/include/llvm/Support/WithColor.h
The file was modifiedllvm/tools/llvm-dwarfdump/llvm-dwarfdump.cpp
The file was modifiedllvm/lib/Support/Statistic.cpp
The file was modifiedllvm/unittests/Support/RISCVAttributeParserTest.cpp
The file was modifiedllvm/unittests/Support/CommandLineTest.cpp
The file was modifiedllvm/lib/Support/TimeProfiler.cpp
The file was modifiedllvm/tools/llvm-bcanalyzer/llvm-bcanalyzer.cpp
The file was modifiedclang-tools-extra/clangd/indexer/IndexerMain.cpp
The file was modifiedllvm/include/llvm/Support/CommandLine.h
The file was modifiedllvm/docs/CommandLine.rst
The file was modifiedclang-tools-extra/clangd/index/dex/dexp/Dexp.cpp
The file was modifiedllvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
The file was modifiedllvm/tools/llvm-libtool-darwin/llvm-libtool-darwin.cpp
The file was modifiedllvm/lib/Support/RandomNumberGenerator.cpp
The file was modifiedllvm/include/llvm/Support/ARMAttributeParser.h
Commit a12000e4289bb2d630d2ef594d369db375a03e2f by simon.giesecke
Reformat files.

Differential Revision: https://reviews.llvm.org/D105982
The file was modifiedllvm/include/llvm/DebugInfo/Symbolize/Symbolize.h
The file was modifiedllvm/lib/DebugInfo/Symbolize/Symbolize.cpp
The file was modifiedllvm/include/llvm/DebugInfo/GSYM/LookupResult.h
The file was modifiedllvm/include/llvm/DebugInfo/DIContext.h
Commit 918bda1241202d0480c6d94ec8f72c483d77a06c by vince.a.bridgers
[analyzer] Do not assume that all pointers have the same bitwidth as void*

This change addresses this assertion that occurs in a downstream
compiler with a custom target.

```APInt.h:1151: bool llvm::APInt::operator==(const llvm::APInt &) const: Assertion `BitWidth == RHS.BitWidth && "Comparison requires equal bit widths"'```

No covering test case is susbmitted with this change since this crash
cannot be reproduced using any upstream supported target. The test case
that exposes this issue is as simple as:

```lang=c++
  void test(int * p) {
    int * q = p-1;
    if (q) {}
    if (q) {} // crash
    (void)q;
  }
```

The custom target that exposes this problem supports two address spaces,
16-bit `char`s, and a `_Bool` type that maps to 16-bits. There are no upstream
supported targets with similar attributes.

The assertion appears to be happening as a result of evaluating the
`SymIntExpr` `(reg_$0<int * p>) != 0U` in `VisitSymIntExpr` located in
`SimpleSValBuilder.cpp`. The `LHS` is evaluated to `32b` and the `RHS` is
evaluated to `16b`. This eventually leads to the assertion in `APInt.h`.

While this change addresses the crash and passes LITs, two follow-ups
are required:
  1) The remainder of `getZeroWithPtrWidth()` and `getIntWithPtrWidth()`
     should be cleaned up following this model to prevent future
     confusion.
  2) We're not sure why references are found along with the modified
     code path, that should not be the case. A more principled
     fix may be found after some further comprehension of why this
     is the case.

Acks: Thanks to @steakhal and @martong for the discussions leading to this
fix.

Reviewed By: NoQ

Differential Revision: https://reviews.llvm.org/D105974
The file was modifiedclang/lib/StaticAnalyzer/Core/SValBuilder.cpp
The file was addedclang/test/Analysis/solver-sym-simplification-ptr-bool.cl
Commit 69a56845317b340e01e75d0cff8fb2f90f6fe1d2 by tbaeder
[llvm][tools] Hide unrelated llvm-cfi-verify options

Differential Revision: https://reviews.llvm.org/D106055
The file was modifiedllvm/tools/llvm-cfi-verify/llvm-cfi-verify.cpp
The file was addedllvm/test/tools/llvm-cfi-verify/help.test
Commit edfcfa6f7bf058052a377a974a8c76df3fb6bca0 by uday
[MLIR][NFC] Improve doc comment and delete stale comment

Remove duplicate and stale doc comment on affineParallelize. NFC.
The file was modifiedmlir/include/mlir/Dialect/Affine/Utils.h
The file was modifiedmlir/lib/Dialect/Affine/Utils/Utils.cpp
Commit a6ca88e908b5befcd9b0f8c8cb40f53095cc17bc by fraser
[RISCV] Lower more BUILD_VECTOR sequences to RVV's VID

This patch teaches the compiler to identify a wider variety of
`BUILD_VECTOR`s which form integer arithmetic sequences, and to lower
them to `vid.v` with modifications for non-unit steps and non-zero
addends.

The sequences handled by this optimization must either be monotonically
increasing or decreasing. Consecutive elements holding the same value
indicate a fractional step which, while simple mathematically,
becomes more complex to handle both in the realm of lossy integer
division and in the presence of `undef`s.

For example, a common "interleaving" shuffle index will be lowered by
LLVM to both `<0,u,1,u,2,...>` and `<u,0,u,1,u,...>` `BUILD_VECTOR`
nodes. Either of these would ideally be lowered to `vid.v` shifted right
by 1. Detection of this sequence in presence of general `undef` values
is more complicated, however: `<0,u,u,1,>` could match either
`<0,0,0,1,>` or `<0,0,1,1,>` depending on later values in the sequence.
Both are possible, so backtracking or multiple passes is inevitable.

Sticking to monotonic sequences keeps the logic simpler as it can be
done in one pass. Fractional steps will likely be a separate
optimization in a future patch.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D104921
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-stepvector-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-stepvector-rv32.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.cpp
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
Commit 239d01fa884d8707ece2f2dbf0eafcbbf8714aa4 by sander.desmalen
Reland "[LV] Print remark when loop cannot be vectorized due to invalid costs."

The original patch was:
  https://reviews.llvm.org/D105806

There were some issues with undeterministic behaviour of the sorting
function, which led to scalable-call.ll passing and/or failing. This
patch fixes the issue by numbering all instructions in the array first,
and using that number as the order, which should provide a consistent
ordering.

This reverts commit a607f64118240f70bf1b14ec121b65f49d63800d.
The file was modifiedllvm/lib/Transforms/Vectorize/LoopVectorize.cpp
The file was modifiedllvm/test/Transforms/LoopVectorize/AArch64/scalable-call.ll
Commit d046fb62b7e7cd273b104fee0162725003411c00 by david.spickett
[lldb][AArch64] Refactor memory tag range handling

Previously GetMemoryTagManager checked many things in one:
* architecture supports memory tagging
* process supports memory tagging
* memory range isn't inverted
* memory range is all tagged

Since writing follow up patches for tag writing (in review
at the moment) it has become clear that this gets unwieldy
once we add the features needed for that.

It also implies that the memory tag manager is tied to the
range you used to request it with but it is not. It's a per
process object.

Instead:
* GetMemoryTagManager just checks architecture and process.
* Then the MemoryTagManager can later be asked to check a
  memory range.

This is better because:
* We don't imply that range and manager are tied together.
* A slightly diferent range calculation for tag writing
  doesn't add more code to Process.
* Range checking code can now be unit tested.

Reviewed By: omjavaid

Differential Revision: https://reviews.llvm.org/D105630
The file was modifiedlldb/include/lldb/Target/MemoryTagManager.h
The file was modifiedlldb/unittests/Process/Utility/MemoryTagManagerAArch64MTETest.cpp
The file was modifiedlldb/source/Plugins/Process/Utility/MemoryTagManagerAArch64MTE.h
The file was modifiedlldb/source/Commands/CommandObjectMemoryTag.cpp
The file was modifiedlldb/include/lldb/Target/Process.h
The file was modifiedlldb/source/Plugins/Process/Utility/MemoryTagManagerAArch64MTE.cpp
The file was modifiedlldb/source/Target/Process.cpp
Commit 99eb96f03186bf94476498979d5a6cd6a9cbf066 by cullen.rhodes
[AArch64][SME] Add load and store instructions

This patch adds support for following contiguous load and store
instructions:

  * LD1B, LD1H, LD1W, LD1D, LD1Q
  * ST1B, ST1H, ST1W, ST1D, ST1Q

A new register class and operand is added for the 32-bit vector select
register W12-W15. The differences in the following tests which have been
re-generated are caused by the introduction of this register class:

  * llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-inline-asm.ll
  * llvm/test/CodeGen/AArch64/GlobalISel/regbank-inlineasm.mir
  * llvm/test/CodeGen/AArch64/stp-opt-with-renaming-reserved-regs.mir
  * llvm/test/CodeGen/AArch64/stp-opt-with-renaming.mir

D88663 attempts to resolve the issue with the store pair test
differences in the AArch64 load/store optimizer.

The GlobalISel differences are caused by changes in the enum values of
register classes, tests have been updated with the new values.

The reference can be found here:
https://developer.arm.com/documentation/ddi0602/2021-06

Reviewed By: CarolineConcatto

Differential Revision: https://reviews.llvm.org/D105572
The file was addedllvm/test/MC/AArch64/SME/ld1d.s
The file was addedllvm/test/MC/AArch64/SME/ld1q-diagnostics.s
The file was addedllvm/test/MC/AArch64/SME/ld1h-diagnostics.s
The file was addedllvm/test/MC/AArch64/SME/st1d-diagnostics.s
The file was modifiedllvm/test/MC/AArch64/SME/addha-diagnostics.s
The file was addedllvm/test/MC/AArch64/SME/st1q-diagnostics.s
The file was modifiedllvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
The file was addedllvm/test/MC/AArch64/SME/st1b.s
The file was addedllvm/test/MC/AArch64/SME/ld1h.s
The file was addedllvm/test/MC/AArch64/SME/st1h-diagnostics.s
The file was addedllvm/test/MC/AArch64/SME/st1w.s
The file was modifiedllvm/test/MC/AArch64/neon-diagnostics.s
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/irtranslator-inline-asm.ll
The file was modifiedllvm/test/CodeGen/AArch64/stp-opt-with-renaming.mir
The file was modifiedllvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
The file was addedllvm/test/MC/AArch64/SME/st1h.s
The file was modifiedllvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
The file was modifiedllvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrFormats.td
The file was addedllvm/test/MC/AArch64/SME/ld1w.s
The file was addedllvm/test/MC/AArch64/SME/st1q.s
The file was modifiedllvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/regbank-inlineasm.mir
The file was addedllvm/test/MC/AArch64/SME/st1b-diagnostics.s
The file was modifiedllvm/test/CodeGen/AArch64/stp-opt-with-renaming-reserved-regs.mir
The file was addedllvm/test/MC/AArch64/SME/ld1b-diagnostics.s
The file was addedllvm/test/MC/AArch64/SME/ld1b.s
The file was addedllvm/test/MC/AArch64/SME/ld1d-diagnostics.s
The file was addedllvm/test/MC/AArch64/SME/st1d.s
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64RegisterInfo.td
The file was modifiedllvm/lib/Target/AArch64/SMEInstrFormats.td
The file was addedllvm/test/MC/AArch64/SME/ld1w-diagnostics.s
The file was addedllvm/test/MC/AArch64/SME/ld1q.s
The file was addedllvm/test/MC/AArch64/SME/st1w-diagnostics.s
Commit 49d73130ca17a19bd68c251451a4ff0c0cdc00e1 by kerry.mclaughlin
[LV] Avoid scalable vectorization for loops containing alloca

This patch returns an Invalid cost from getInstructionCost() for alloca
instructions if the VF is scalable, as otherwise loops which contain
these instructions will crash when attempting to scalarize the alloca.

Reviewed By: sdesmalen

Differential Revision: https://reviews.llvm.org/D105824
The file was addedllvm/test/Transforms/LoopVectorize/AArch64/scalable-alloca.ll
The file was modifiedllvm/lib/Transforms/Vectorize/LoopVectorize.cpp
Commit 9769535efd56680958d8004ddc33f0569e617bdf by nicholas.guy
[AArch64] Update Cortex-A55 SchedModel to improve LDP scheduling

Specifying the latencies of specific LDP variants appears to improve
performance almost universally.

Differential Revision: https://reviews.llvm.org/D105882
The file was modifiedllvm/test/tools/llvm-mca/AArch64/Cortex/A55-basic-instructions.s
The file was modifiedllvm/lib/Target/AArch64/AArch64SchedA55.td
Commit e4b79a542e2217b1838cae8e3434ebc3705e8d43 by zinenko
[mlir] add an interface to support custom types in LLVM dialect pointers

This may be necessary in partial multi-stage conversion when a container type
from dialect A containing types from dialect B goes through the conversion
where only dialect A is converted to the LLVM dialect. We will need to keep a
pointer-to-non-LLVM type in the IR until a further conversion can convert
dialect B types to LLVM types.

Reviewed By: wsmoses

Differential Revision: https://reviews.llvm.org/D106076
The file was modifiedmlir/include/mlir/Dialect/LLVMIR/LLVMTypes.h
The file was modifiedmlir/include/mlir/Dialect/LLVMIR/LLVMOpBase.td
The file was modifiedmlir/test/Dialect/LLVMIR/types.mlir
The file was modifiedutils/bazel/llvm-project-overlay/mlir/BUILD.bazel
The file was modifiedmlir/test/lib/Dialect/Test/CMakeLists.txt
The file was modifiedmlir/include/mlir/Dialect/LLVMIR/CMakeLists.txt
The file was modifiedmlir/include/mlir/Dialect/LLVMIR/LLVMOpsInterfaces.td
The file was modifiedmlir/test/lib/Dialect/Test/TestTypes.cpp
The file was modifiedutils/bazel/llvm-project-overlay/mlir/test/BUILD.bazel
The file was modifiedmlir/lib/Dialect/LLVMIR/IR/LLVMTypes.cpp
The file was modifiedmlir/include/mlir/Dialect/LLVMIR/LLVMOps.td
Commit a0b4f424f56486fe6c3d5f6bac757c59e0ff72a4 by sepavloff
Use update_test_checks.py to auto-generate check lines
The file was modifiedllvm/test/Transforms/InstSimplify/constfold-constrained.ll
Commit 46ef86b5d82ea8ec36de680f10b69d36487e4d1d by pifon
[mlir] Move linalg::Expand/CollapseShapeOp to memref dialect.

RFC: https://llvm.discourse.group/t/rfc-reshape-ops-restructuring/3310

Differential Revision: https://reviews.llvm.org/D106141
The file was modifiedutils/bazel/llvm-project-overlay/mlir/BUILD.bazel
The file was modifiedmlir/test/Conversion/MemRefToLLVM/memref-to-llvm.mlir
The file was modifiedmlir/test/Dialect/MemRef/ops.mlir
The file was modifiedmlir/test/Dialect/Linalg/invalid.mlir
The file was modifiedmlir/test/Dialect/Linalg/canonicalize.mlir
The file was modifiedmlir/include/mlir/Dialect/Linalg/IR/LinalgOps.td
The file was modifiedmlir/lib/Conversion/MemRefToLLVM/MemRefToLLVM.cpp
The file was modifiedmlir/test/Dialect/MemRef/invalid.mlir
The file was modifiedmlir/lib/Conversion/LinalgToStandard/LinalgToStandard.cpp
The file was modifiedmlir/lib/Dialect/Linalg/IR/LinalgOps.cpp
The file was modifiedmlir/lib/Conversion/LinalgToLLVM/LinalgToLLVM.cpp
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/Bufferize.cpp
The file was modifiedmlir/test/Dialect/MemRef/canonicalize.mlir
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/DropUnitDims.cpp
The file was modifiedmlir/test/Dialect/Linalg/bufferize.mlir
The file was modifiedmlir/test/Dialect/Linalg/roundtrip.mlir
The file was modifiedmlir/test/Dialect/Linalg/llvm.mlir
The file was modifiedmlir/include/mlir/Dialect/Utils/ReshapeOpsUtils.h
The file was modifiedmlir/lib/Dialect/MemRef/IR/MemRefOps.cpp
The file was modifiedmlir/lib/Dialect/Utils/ReshapeOpsUtils.cpp
The file was modifiedmlir/include/mlir/Dialect/MemRef/IR/MemRefOps.td
The file was modifiedmlir/test/Dialect/Linalg/drop-unit-extent-dims.mlir
The file was modifiedmlir/include/mlir/Dialect/MemRef/IR/MemRef.h
Commit 66225db98d832bec75ffb96298107c015b0035f0 by zarko
[PowerPC][AIX] Add warning when alignment is incompatible with XL

https://reviews.llvm.org/D105659 implements ByVal handling in llc but
some cases are not compatible with existing XL compiler on AIX.  Adding
a clang warning for such cases.

Reviewed By: aaron.ballman

Differential Revision: https://reviews.llvm.org/D105660
The file was modifiedclang/include/clang/Basic/DiagnosticGroups.td
The file was modifiedclang/include/clang/Basic/DiagnosticSemaKinds.td
The file was modifiedclang/lib/Sema/SemaDeclAttr.cpp
The file was addedclang/test/Sema/aix-attr-align.c
Commit 09c9f4dc7db2c6f3972089c08dcfc64a5d6bc091 by dmitry.preobrazhensky
[AMDGPU][MC] Added missing isCall/isBranch flags

Added isCall for S_CALL_B64; added isBranch for S_SUBVECTOR_LOOP_*.

Differential Revision: https://reviews.llvm.org/D106072
The file was modifiedllvm/lib/Target/AMDGPU/SOPInstructions.td
Commit 8ada884cbc2f02863cd71bddd97c7ff206ad3256 by sguelton
SubstTemplateTypeParmType can contain an 'auto' type in their replacement type

This fixes bug 36064

Differential Revision: https://reviews.llvm.org/D106093
The file was addedclang/test/SemaCXX/crash-auto-36064.cpp
The file was modifiedclang/lib/AST/Type.cpp
Commit d9abb15774c5054b582cff434aedb9198abba294 by spatel
[SLP] add tests for poison-safe bool logic reductions; NFC

More coverage for D105730
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/reduction-logical.ll
Commit 231bf52119ee09ed4b4977195d83dd7f42a2e13c by jeremy.morse
[InstrRef][FastISel] Support emitting DBG_INSTR_REF from fast-isel

If you attach __attribute__((optnone)) to a function when using
optimisations, that function will use fast-isel instead of the usual
SelectionDAG method. This is a problem for instruction referencing,
because it means DBG_VALUEs of virtual registers will be created,
triggering some safety assertions in LiveDebugVariables. Those assertions
exist to detect exactly this scenario, where an unexpected piece of code is
generating virtual register references in instruction referencing mode.

Fix this by transforming the DBG_VALUEs created by fast-isel into
half-formed DBG_INSTR_REFs, after which they get patched up in
finalizeDebugInstrRefs. The test modified adds a fast-isel mode to the
instruction referencing isel test.

Differential Revision: https://reviews.llvm.org/D105694
The file was modifiedllvm/test/DebugInfo/X86/instr-ref-selectiondag.ll
The file was modifiedllvm/lib/CodeGen/SelectionDAG/FastISel.cpp
Commit 21a0ef8d19aaec9f948ab20d880605161b366ad1 by Matthew.Arsenault
AMDGPU/GlobalISel: Redo kernel argument load handling

This avoids relying on G_EXTRACT on unusual types, and also properly
decomposes structs into multiple registers. This also preserves the
LLTs in the memory operands.
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUCallLowering.h
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_kernel.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
Commit 3ceb92295eeae71263055308824e7096d40cef45 by Matthew.Arsenault
AMDGPU/GlobalISel: Preserve more memory types
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/global-value.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_kernel.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.format.f16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.format.ll
Commit f57f8f7ccc804d0ae24541442abdd8bbc4c129cb by Matthew.Arsenault
GlobalISel: Remove dead function
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/CallLowering.h
The file was modifiedllvm/lib/CodeGen/GlobalISel/CallLowering.cpp
Commit 881dc34f73e2eb20cbb0bf2d95b6fc79485e0fd9 by zinenko
[mlir] replace llvm.mlir.cast with unrealized_conversion_cast

The dialect-specific cast between builtin (ex-standard) types and LLVM
dialect types was introduced long time before built-in support for
unrealized_conversion_cast. It has a similar purpose, but is restricted
to compatible builtin and LLVM dialect types, which may hamper
progressive lowering and composition with types from other dialects.
Replace llvm.mlir.cast with unrealized_conversion_cast, and drop the
operation that became unnecessary.

Also make unrealized_conversion_cast legal by default in
LLVMConversionTarget as the majority of convesions using it are partial
conversions that actually want the casts to persist in the IR. The
standard-to-llvm conversion, which is still expected to run last, cleans
up the remaining casts  standard-to-llvm conversion, which is still
expected to run last, cleans up the remaining casts

Reviewed By: nicolasvasilache

Differential Revision: https://reviews.llvm.org/D105880
The file was modifiedmlir/lib/Conversion/AsyncToLLVM/AsyncToLLVM.cpp
The file was modifiedmlir/test/Conversion/ComplexToLLVM/convert-to-llvm.mlir
The file was modifiedmlir/test/Conversion/MemRefToLLVM/convert-static-memref-ops.mlir
The file was modifiedmlir/lib/Conversion/MathToLLVM/MathToLLVM.cpp
The file was modifiedmlir/lib/Conversion/GPUCommon/GPUToLLVMConversion.cpp
The file was modifiedmlir/lib/Conversion/OpenACCToLLVM/OpenACCToLLVM.cpp
The file was modifiedmlir/lib/Conversion/MemRefToLLVM/MemRefToLLVM.cpp
The file was modifiedmlir/lib/Conversion/LinalgToLLVM/LinalgToLLVM.cpp
The file was modifiedmlir/lib/IR/BuiltinDialect.cpp
The file was modifiedmlir/lib/Conversion/StandardToLLVM/StandardToLLVM.cpp
The file was modifiedmlir/lib/Conversion/ComplexToLLVM/ComplexToLLVM.cpp
The file was modifiedmlir/test/Conversion/VectorToLLVM/vector-to-llvm.mlir
The file was removedmlir/test/Dialect/LLVMIR/dialect-cast.mlir
The file was modifiedmlir/lib/Conversion/LLVMCommon/ConversionTarget.cpp
The file was modifiedmlir/test/Conversion/AsyncToLLVM/convert-runtime-to-llvm.mlir
The file was modifiedmlir/test/Conversion/MemRefToLLVM/convert-dynamic-memref-ops.mlir
The file was modifiedmlir/include/mlir/Dialect/LLVMIR/LLVMOps.td
The file was modifiedmlir/test/Conversion/MemRefToLLVM/memref-to-llvm.mlir
The file was modifiedmlir/test/Dialect/ArmSVE/memcpy.mlir
The file was modifiedmlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
The file was modifiedmlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVMPass.cpp
The file was modifiedmlir/lib/Conversion/LLVMCommon/TypeConverter.cpp
Commit a24e020d1a2dd038a0f1c7be3a728a0f5f62bd00 by zinenko
[mlir] add missing build dependency
The file was modifiedmlir/lib/Conversion/LinalgToLLVM/CMakeLists.txt
Commit adee89f8bcd11529bc9e046493b71fbe4b49dcd1 by david.spickett
[lldb][AArch64] Add tag packing and repetition memory tag manager

PackTags is used by to compress tags to go in the QMemTags packet
and be passed to ptrace when writing memory tags.

The behaviour of RepeatTagsForRange matches that described for QMemTags
in the GDB documentation:
https://sourceware.org/gdb/current/onlinedocs/gdb/General-Query-Packets.html#General-Query-Packets

In addition, unpacking tags with number of tags 0 now means
do not check that number of tags matches the range.
This will be used by lldb-server to unpack tags before repeating
them to fill the requested range.

Reviewed By: omjavaid

Differential Revision: https://reviews.llvm.org/D105179
The file was modifiedlldb/include/lldb/Target/MemoryTagManager.h
The file was modifiedlldb/unittests/Process/Utility/MemoryTagManagerAArch64MTETest.cpp
The file was modifiedlldb/source/Plugins/Process/Utility/MemoryTagManagerAArch64MTE.cpp
The file was modifiedlldb/source/Plugins/Process/Utility/MemoryTagManagerAArch64MTE.h
Commit e3fa2b1eab60342dc882b7b888658b03c472fa2b by fraser
Revert "[RISCV] Lower more BUILD_VECTOR sequences to RVV's VID"

This reverts commit a6ca88e908b5befcd9b0f8c8cb40f53095cc17bc.

More caution is required to avoid overflow/underflow. Thanks to the
santizers for catching this.
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-stepvector-rv32.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-stepvector-rv64.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.cpp
Commit ba627a32e125cab988f97da8e2466398f2bc75b2 by amy.kwan1
[PowerPC] Update Refactored Load/Store Implementation, XForm VSX Patterns, and Tests

This patch includes the following updates to the load/store refactoring effort introduced in D93370:
- Update various VSX patterns that use to "force" an XForm, to instead just XForm.
   This allows the ability for the patterns to compute the most optimal addressing
   mode (and to produce a DForm instruction when possible)
- Update pattern and test case for the LXVD2X/STXVD2X intrinsics
- Update LIT test cases that use to use the XForm instruction to use the DForm instruction

Differential Revision: https://reviews.llvm.org/D95115
The file was modifiedllvm/test/CodeGen/PowerPC/load-shuffle-and-shuffle-store.ll
The file was modifiedllvm/test/CodeGen/PowerPC/vec_conv_i16_to_fp32_elts.ll
The file was modifiedllvm/test/CodeGen/PowerPC/f128-conv.ll
The file was modifiedllvm/test/CodeGen/PowerPC/vavg.ll
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrVSX.td
The file was modifiedllvm/test/CodeGen/PowerPC/f128-arith.ll
The file was modifiedllvm/test/CodeGen/PowerPC/ppc64-align-long-double.ll
The file was modifiedllvm/test/CodeGen/PowerPC/select_const.ll
The file was modifiedllvm/test/CodeGen/PowerPC/vec_conv_i16_to_fp64_elts.ll
The file was modifiedllvm/test/CodeGen/PowerPC/f128_ldst.ll
The file was modifiedllvm/test/CodeGen/PowerPC/canonical-merge-shuffles.ll
The file was modifiedllvm/test/CodeGen/PowerPC/aix-vec-arg-spills-callee.ll
The file was modifiedllvm/test/CodeGen/PowerPC/fma-combine.ll
The file was modifiedllvm/test/CodeGen/PowerPC/vec-itofp.ll
The file was modifiedllvm/test/CodeGen/PowerPC/ppc64-i128-abi.ll
The file was modifiedllvm/test/CodeGen/PowerPC/vector-extend-sign.ll
The file was modifiedllvm/test/CodeGen/PowerPC/vec_conv_i8_to_fp64_elts.ll
The file was modifiedllvm/test/CodeGen/PowerPC/p10-splatImm-CPload-pcrel.ll
The file was modifiedllvm/test/CodeGen/PowerPC/fmf-propagation.ll
The file was modifiedllvm/test/CodeGen/PowerPC/swaps-le-6.ll
The file was modifiedllvm/test/CodeGen/PowerPC/vsx-p9.ll
The file was modifiedllvm/test/CodeGen/PowerPC/PR33671.ll
The file was modifiedllvm/test/CodeGen/PowerPC/store_fptoi.ll
The file was modifiedllvm/test/CodeGen/PowerPC/f128-compare.ll
The file was modifiedllvm/test/CodeGen/PowerPC/scalar_vector_test_1.ll
The file was modifiedllvm/test/CodeGen/PowerPC/urem-vector-lkk.ll
The file was modifiedllvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i8_elts.ll
The file was modifiedllvm/test/CodeGen/PowerPC/vec_conv_i8_to_fp32_elts.ll
The file was modifiedllvm/test/CodeGen/PowerPC/unaligned-addressing-mode.ll
The file was modifiedllvm/test/CodeGen/PowerPC/p9-vinsert-vextract.ll
The file was modifiedllvm/test/CodeGen/PowerPC/scalar-i64-ldst.ll
The file was modifiedllvm/test/CodeGen/PowerPC/extract-and-store.ll
The file was modifiedllvm/test/CodeGen/PowerPC/vsx.ll
The file was modifiedllvm/test/CodeGen/PowerPC/vector-popcnt-128-ult-ugt.ll
The file was modifiedllvm/test/CodeGen/PowerPC/mcm-4.ll
The file was modifiedllvm/test/CodeGen/PowerPC/vec_int_ext.ll
The file was modifiedllvm/test/CodeGen/PowerPC/instr-properties.ll
The file was modifiedllvm/test/CodeGen/PowerPC/scalar-i32-ldst.ll
The file was modifiedllvm/test/CodeGen/PowerPC/tailcall-speculatable-callee.ll
The file was modifiedllvm/test/CodeGen/PowerPC/vec_conv_fp32_to_i8_elts.ll
The file was modifiedllvm/test/CodeGen/PowerPC/pr36292.ll
The file was modifiedllvm/test/CodeGen/PowerPC/VSX-XForm-Scalars.ll
The file was modifiedllvm/test/CodeGen/PowerPC/vec_extract_p9.ll
The file was modifiedllvm/test/CodeGen/PowerPC/non-debug-mi-search-frspxsrsp.ll
The file was modifiedllvm/test/CodeGen/PowerPC/fast-isel-load-store-vsx.ll
The file was modifiedllvm/test/CodeGen/PowerPC/build-vector-tests.ll
The file was modifiedllvm/test/CodeGen/PowerPC/pre-inc-disable.ll
The file was modifiedllvm/test/CodeGen/PowerPC/pr38087.ll
The file was modifiedllvm/test/CodeGen/PowerPC/pcrel_ldst.ll
The file was modifiedllvm/test/CodeGen/PowerPC/scalar-i16-ldst.ll
The file was modifiedllvm/test/CodeGen/PowerPC/srem-vector-lkk.ll
The file was modifiedllvm/test/CodeGen/PowerPC/vsx_insert_extract_le.ll
The file was modifiedllvm/test/CodeGen/PowerPC/scalar_vector_test_2.ll
The file was modifiedllvm/test/CodeGen/PowerPC/pr45628.ll
The file was modifiedllvm/test/CodeGen/PowerPC/vec_conv_fp32_to_i16_elts.ll
The file was modifiedllvm/test/CodeGen/PowerPC/fp128-bitcast-after-operation.ll
The file was modifiedllvm/test/CodeGen/PowerPC/vector-constrained-fp-intrinsics.ll
The file was modifiedllvm/test/CodeGen/PowerPC/aix-dfltabi-rsrvd-reg.ll
The file was modifiedllvm/test/CodeGen/PowerPC/float-load-store-pair.ll
The file was modifiedllvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i16_elts.ll
The file was modifiedllvm/test/CodeGen/PowerPC/p10-vector-rotate.ll
The file was modifiedllvm/test/CodeGen/PowerPC/vsx_builtins.ll
The file was modifiedllvm/test/CodeGen/PowerPC/vsx_scalar_ld_st.ll
The file was modifiedllvm/test/CodeGen/PowerPC/unaligned.ll
The file was modifiedllvm/test/CodeGen/PowerPC/lxv-aligned-stack-slots.ll
The file was modifiedllvm/test/CodeGen/PowerPC/scalar-i8-ldst.ll
The file was modifiedllvm/test/CodeGen/PowerPC/f128-aggregates.ll
The file was modifiedllvm/test/CodeGen/PowerPC/ppcf128-constrained-fp-intrinsics.ll
The file was modifiedllvm/test/CodeGen/PowerPC/aix32-vector-vararg-fixed-callee.ll
The file was modifiedllvm/test/CodeGen/PowerPC/ctrloop-constrained-fp.ll
The file was modifiedllvm/test/CodeGen/PowerPC/fp-strict-conv-f128.ll
The file was modifiedllvm/test/CodeGen/PowerPC/scalar-float-ldst.ll
The file was modifiedllvm/test/CodeGen/PowerPC/aix64-vector-vararg-fixed-callee.ll
The file was modifiedllvm/test/CodeGen/PowerPC/mma-acc-spill.ll
The file was modifiedllvm/test/CodeGen/PowerPC/builtins-ppc-p9-f128.ll
The file was modifiedllvm/test/CodeGen/PowerPC/pr30715.ll
The file was modifiedllvm/test/CodeGen/PowerPC/aix-p9-insert-extract.ll
The file was modifiedllvm/test/CodeGen/PowerPC/mul-const-vector.ll
The file was modifiedllvm/test/CodeGen/PowerPC/aix-vector-vararg-fixed-caller.ll
The file was modifiedllvm/test/CodeGen/PowerPC/constant-pool.ll
The file was modifiedllvm/test/CodeGen/PowerPC/f128-truncateNconv.ll
The file was modifiedllvm/test/CodeGen/PowerPC/register-pressure-reduction.ll
The file was modifiedllvm/test/CodeGen/PowerPC/toc-float.ll
The file was modifiedllvm/test/CodeGen/PowerPC/pcrel-linkeropt.ll
The file was modifiedllvm/test/CodeGen/PowerPC/scalar-double-ldst.ll
The file was modifiedllvm/test/CodeGen/PowerPC/vector-ldst.ll
The file was modifiedllvm/test/CodeGen/PowerPC/recipest.ll
The file was modifiedllvm/test/CodeGen/PowerPC/f128-passByValue.ll
The file was modifiedllvm/test/CodeGen/PowerPC/mma-outer-product.ll
Commit 395271ad11b8c233db1a4e0e6a76aa52e93e5aec by Louis Dionne
[runtimes] Simplify how we set the target triple

Instead of using TARGET_TRIPLE, which is always set to LLVM_DEFAULT_TARGET_TRIPLE,
use that variable directly to populate the various XXXX_TARGET_TRIPLE
variables in the runtimes.

This re-applies 77396bbc98 and 5099e01568, which were reverted in
850b57c5fbe because they broke the build.

Differential Revision: https://reviews.llvm.org/D106009
The file was modifiedlibcxx/CMakeLists.txt
The file was modifiedlibcxx/test/CMakeLists.txt
The file was modifiedlibcxxabi/test/CMakeLists.txt
The file was modifiedlibunwind/CMakeLists.txt
The file was modifiedlibcxx/lib/abi/CMakeLists.txt
The file was modifiedlibunwind/test/CMakeLists.txt
The file was modifiedlibcxxabi/CMakeLists.txt
Commit ee2068b30ecf297c004c06eedd7e1063c67a279c by msd.ataei
[PowerPC] Updated the error message of MASSV pass to mention vectorization
is needed be enable on P8 and later targets.

Differential Revision: https://reviews.llvm.org/D106091
The file was modifiedllvm/lib/Target/PowerPC/PPCLowerMASSVEntries.cpp
Commit 219c729f5ea8257c10755723162f2fb4a88b4466 by gcmn
[Bazel] Delete deprecated gentbl rule

This has been deprecated for a while. There are no users in tree and I'm
not aware of any out of tree users either.

Reviewed By: ftynse

Differential Revision: https://reviews.llvm.org/D106114
The file was modifiedutils/bazel/llvm-project-overlay/mlir/tblgen.bzl
Commit 2994ad3ab8b163e1a797e96b28f4afcf9956846f by pifon
[mlir] Remove unused functions in LinalgOps.cpp
The file was modifiedmlir/lib/Dialect/Linalg/IR/LinalgOps.cpp
Commit 18e21e6832007384dec8163baa7e1bb69f458b29 by Louis Dionne
[libc++] CI: Setup BuildKite agents through launchd

This makes sure that even if a node goes down, the BuildKite agent will
be started again when it goes back up.
The file was modifiedlibcxx/utils/ci/macos-ci-setup
Commit e0a080d3484bc1e0ea28cf2a815a9b9fff0cdefe by Matthew.Arsenault
AArch64/GlobalISel: Update tests to use correct memory types
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/legalize-shuffle-vector.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/store-addressing-modes.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/artifact-find-value.mir
Commit 5a0d940f2ac900554e49f4901d21611aa4884c1d by Matthew.Arsenault
GlobalISel: Preserve memory type for memset expansion
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/inline-memset.mir
The file was modifiedllvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
Commit 9ad1a499562bf9f7bc9f5ef70664201f4e9d51c6 by Matthew.Arsenault
Mips/GlobalISel: Use LLT form of getMachineMemOperand

NFC here since it's just using a scalar anyway.
The file was modifiedllvm/lib/Target/Mips/MipsCallLowering.cpp
Commit fbc3e69f58d0e2e8e143c2a098cc7443bae2fdbb by Louis Dionne
[libc++] ci: Create ~/Library/LaunchAgents if it does not exist yet
The file was modifiedlibcxx/utils/ci/macos-ci-setup
Commit a7b7d22d6ead13c44a8ff55ad119179fbb3d1686 by congzhecao
[LoopInterchange] Check lcssa phis in the inner latch in scenarios of multi-level nested loops

We already know that we need to check whether lcssa
phis are supported in inner loop exit block or in
outer loop exit block, and we have logic to check
them already. Presumably the inner loop latch does
not have lcssa phis and there is no code that deals
with lcssa phis in the inner loop latch. However,
that assumption is not true, when we have loops
with more than two-level nesting. This patch adds
checks for lcssa phis in the inner latch.

Reviewed By: Whitney

Differential Revision: https://reviews.llvm.org/D102300
The file was modifiedllvm/lib/Transforms/Scalar/LoopInterchange.cpp
The file was addedllvm/test/Transforms/LoopInterchange/innermost-latch-uses-values-in-middle-header.ll
Commit aa06f34dac65cbfcbffd7cb3b033eadcd103ffdf by andrzej.warzynski
[flang][driver] Fix output filename generation in `flang`

In the `flang` bash script, we need to be careful _when_ to use <output>
from `flang -c -o <output> <input>` when generating the relocatable
output file name.

In particular, we should use it in this case:
```compilation only
flang -c -o <output> <input>
```
but leave it for the final executable here:
```compile, assemble and link
flang  -o <output> <input>
```
This change is implemented in `get_relocatable_name`.

I've also taken the liberty to fix how errors from sub-commands are
reported (without this change, `flang` always returns `0` on failure).
This is implemented in `main`.

Differential Revision: https://reviews.llvm.org/D105896
The file was modifiedflang/tools/f18/flang.in
Commit 6cb05ca392fb46c3c2ad1f3624dad3b55adc5cf1 by cjdb
[libcxx][modularisation] adds several headers to the module map

* <__algorithm/iter_swap.h>
* <__algorithm/swap_ranges.h>
* <__functional/is_transparent.h>
* <__memory/uses_allocator.h>
* <__ranges/drop_view.h>
* <__ranges/transform_view.h>
* <shared_mutex>
* <span>

Also updates header inclusions that were affected.

**NOTE:** This is a proper subset of D105932. Since the content has
already been LGTM'd, I intend to merge this patch without review,
pending green CI. I decided it would be better to move these changes
into their own commit since the former patch has undergone further
changes and will need yet another light review. In the event any of
that gets rolled back (for whatever reason), the changes in this patch
won't be affected.

Differential Revision: https://reviews.llvm.org/D106040
The file was modifiedlibcxx/test/libcxx/ranges/range.adaptors/range.copy.wrap/has_value.pass.cpp
The file was modifiedlibcxx/test/std/thread/thread.mutex/thread.lock/thread.lock.shared/thread.lock.shared.obs/op_bool.pass.cpp
The file was modifiedlibcxx/test/std/thread/thread.mutex/thread.lock/thread.lock.shared/thread.lock.shared.locking/try_lock_until.pass.cpp
The file was modifiedlibcxx/include/__ranges/transform_view.h
The file was modifiedlibcxx/include/module.modulemap
The file was modifiedlibcxx/test/libcxx/ranges/range.adaptors/range.copy.wrap/assign.move.pass.cpp
The file was modifiedlibcxx/test/std/containers/views/span.sub/first.fail.cpp
The file was modifiedlibcxx/test/std/containers/views/span.sub/subspan.fail.cpp
The file was modifiedlibcxx/test/libcxx/ranges/range.adaptors/range.copy.wrap/assign.copy.pass.cpp
The file was modifiedlibcxx/test/std/ranges/range.adaptors/range.drop/dangling.cache.pass.cpp
The file was modifiedlibcxx/test/std/thread/thread.mutex/thread.lock/thread.lock.shared/thread.lock.shared.locking/try_lock.pass.cpp
The file was modifiedlibcxx/test/std/thread/thread.mutex/thread.lock/thread.lock.shared/thread.lock.shared.locking/try_lock_for.pass.cpp
The file was modifiedlibcxx/test/libcxx/ranges/range.adaptors/range.copy.wrap/ctor.default.pass.cpp
The file was modifiedlibcxx/test/libcxx/ranges/range.adaptors/range.copy.wrap/no_unique_address.pass.cpp
The file was modifiedlibcxx/test/libcxx/ranges/range.adaptors/range.copy.wrap/deref.pass.cpp
The file was modifiedlibcxx/test/std/thread/thread.mutex/thread.lock/thread.lock.shared/types.pass.cpp
The file was modifiedlibcxx/test/std/thread/thread.mutex/thread.lock/thread.lock.shared/thread.lock.shared.cons/mutex_defer_lock.pass.cpp
The file was modifiedlibcxx/test/std/containers/views/span.sub/last.fail.cpp
The file was modifiedlibcxx/test/libcxx/ranges/range.adaptors/range.copy.wrap/ctor.in_place.pass.cpp
The file was modifiedlibcxx/test/std/thread/thread.mutex/thread.lock/thread.lock.shared/thread.lock.shared.locking/unlock.pass.cpp
The file was modifiedlibcxx/include/__ranges/drop_view.h
The file was modifiedlibcxx/test/libcxx/ranges/range.adaptors/range.copy.wrap/properties.compile.pass.cpp
The file was modifiedlibcxx/test/std/thread/thread.mutex/thread.lock/thread.lock.shared/thread.lock.shared.cons/mutex_adopt_lock.pass.cpp
Commit 1a7cddb0ea63a8413504c8ebdd3a65ba03343d0f by Madhur.Amilkanthwar
[NFC] Fix typo intrinisic

Differential Revision: https://reviews.llvm.org/D106161
The file was modifiedllvm/include/llvm/IR/Intrinsics.td
Commit 4d188a6524083ef79dae910215d4b34fad595358 by nikita.ppv
[Verifier] Require same signature for intrinsic calls

As suggested on D105733, this adds a verifier rule that calls to
intrinsics must match the signature of the intrinsic.

Without opaque pointers this is automatically enforced for all
calls, because the pointer types need to match. If the signatures
don't match, a pointer bitcast has to be inserted. For intrinsics
in particular, such bitcasts are not legal, because the address of
intrinsics cannot be taken.

With opaque pointers, there are no more pointer bitcasts, so it's
generally possible for the call and the callee signature to differ.
However, for intrinsics we still want to enforce that the signatures
must match, the same as was done before through the address taken
check.

We can't enforce this more generally for non-intrinsics, because
calls with mismatched signatures at the very least can legally
occur in unreachable code, and might also be valid in some other
cases, depending on how exactly the signatures differ.

Differential Revision: https://reviews.llvm.org/D106013
The file was modifiedllvm/lib/IR/Verifier.cpp
The file was addedllvm/test/Verifier/force-opaque-ptr.ll
Commit 0ce13f92b7c6b368c0d1862d9e76540aad9629a6 by craig.topper
[RISCV] Add curly braces around a case body that declares variables. NFC

This is at the end of the switch so doesn't cause any issues now,
but if a new case is added it will break.
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.cpp
Commit 4dbb78806871b158c9ec23196f075c070baa2909 by craig.topper
[RISCV] Teach constant materialization that it can use zext.w at the end with Zba to reduce number of instructions.

If the upper 32 bits are zero and bit 31 is set, we might be able to
use zext.w to fill in the zeros after using an lui and/or addi.

Most of this patch is plumbing the subtarget features into the constant
materialization.

Reviewed By: luismarques

Differential Revision: https://reviews.llvm.org/D105509
The file was modifiedllvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.cpp
The file was modifiedllvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.h
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfo.cpp
The file was modifiedllvm/test/CodeGen/RISCV/xaluo.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
The file was modifiedllvm/test/CodeGen/RISCV/rv64zba.ll
The file was modifiedllvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
The file was modifiedllvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
The file was modifiedllvm/test/CodeGen/RISCV/rv64zbb-zbp.ll
The file was modifiedllvm/test/MC/RISCV/rv64b-aliases-valid.s
Commit dd57ba1a17b93dbe211d04cb2d4de5f6dc898d60 by jonathan_roelofs
[MachineVerifier] Diagnose invalid INSERT_SUBREGs

Differential revision: https://reviews.llvm.org/D105953
The file was modifiedllvm/test/CodeGen/X86/domain-reassignment.mir
The file was addedllvm/test/MachineVerifier/test_insert_subreg.mir
The file was modifiedllvm/lib/CodeGen/MachineVerifier.cpp
Commit 95995673d1babee5731146f45ad3ce79c32f06d4 by llvm-dev
[DAG] SelectionDAG::MaskedElementsAreZero - assert we're calling with a vector. NFCI.

Add an assertion that we've calling MaskedElementsAreZero with a vector op and that the DemandedElts arg is a matching width.

Makes the error a lot easier to grok when something else accidentally gets used.
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
Commit 52cd0c5a8d8db57349385f72b4ea0fa8d71d5b63 by llvm-dev
[X86] Regenerate twoaddr-lea.ll test checks.
The file was modifiedllvm/test/CodeGen/X86/twoaddr-lea.ll
Commit 6c40abb6fe055c8a4063567430656dd4e35d338f by jonathan_roelofs
Revert "[MachineVerifier] Diagnose invalid INSERT_SUBREGs"

This reverts commit dd57ba1a17b93dbe211d04cb2d4de5f6dc898d60.

It broke some tests: http://45.33.8.238/linux/51314/step_12.txt
The file was removedllvm/test/MachineVerifier/test_insert_subreg.mir
The file was modifiedllvm/lib/CodeGen/MachineVerifier.cpp
The file was modifiedllvm/test/CodeGen/X86/domain-reassignment.mir
Commit 3c9d86f9515e2cdc57dd76095ab9099aa399f652 by i
[ELF][test] Avoid llvm-readelf/llvm-readobj one-dash long options
The file was modifiedlld/test/ELF/weak-shared-gc.s
The file was modifiedlld/test/ELF/gdb-index.s
The file was modifiedlld/test/ELF/linkerscript/at3.test
The file was modifiedlld/test/ELF/linkerscript/memory-loc-counter.test
The file was modifiedlld/test/ELF/linkerscript/at6.test
The file was modifiedlld/test/ELF/relocatable-many-sections.s
The file was modifiedlld/test/ELF/linkerscript/at7.test
The file was modifiedlld/test/ELF/linkerscript/orphan-discard.s
The file was modifiedlld/test/ELF/arm-v4bx.test
The file was modifiedlld/test/ELF/as-needed-weak.s
The file was modifiedlld/test/ELF/dynamic-list-archive.s
The file was modifiedlld/test/ELF/just-symbols.s
The file was modifiedlld/test/ELF/ppc64-rel-so-local-calls.s
The file was modifiedlld/test/ELF/linkerscript/at8.test
The file was modifiedlld/test/ELF/linkerscript/target.s
The file was modifiedlld/test/ELF/linkerscript/merge-header-load.s
Commit 6dad7a51f8b60a6691ec75fcb753bb51bd145068 by listmail
[SCEV] Add tests for known negative strides in trip count logic
The file was addedllvm/test/Analysis/ScalarEvolution/trip-count-negative-stride.ll
Commit 5609c8b60730519eeb7bc95b61d2c09879dff44b by carrot
[X86FixupLEAs] Try again to transform the sequence LEA/SUB to SUB/SUB

This patch transforms the sequence
    lea (reg1, reg2), reg3
    sub reg3, reg4
to two sub instructions
    sub reg1, reg4
    sub reg2, reg4

Similar optimization can also be applied to LEA/ADD sequence.

The modifications to TwoAddressInstructionPass is to ensure the operands of ADD
instruction has expected order (the dest register of LEA should be src register
of ADD).

Differential Revision: https://reviews.llvm.org/D104684
The file was modifiedllvm/lib/CodeGen/TwoAddressInstructionPass.cpp
The file was modifiedllvm/lib/Target/X86/X86FixupLEAs.cpp
The file was modifiedllvm/test/CodeGen/X86/vp2intersect_multiple_pairs.ll
The file was modifiedllvm/include/llvm/CodeGen/TargetInstrInfo.h
The file was modifiedllvm/test/CodeGen/X86/lea-opt2.ll
The file was modifiedllvm/lib/Target/X86/X86InstrInfo.h
The file was modifiedllvm/lib/Target/X86/X86InstrInfo.cpp
The file was modifiedllvm/test/CodeGen/X86/2009-03-23-MultiUseSched.ll
Commit 2b3a4c7d72be4fd6792ea6bba59cfd11d34c8f88 by listmail
[test] Extend negative stride backedge tests to cover signed comparisons
The file was modifiedllvm/test/Analysis/ScalarEvolution/trip-count-negative-stride.ll
Commit 6a4054ef060ba9cd6fac1b68f226f5b142f0a543 by dvyukov
sanitizer_common: add Semaphore

Semaphore is a portable way to park/unpark threads.
The plan is to use it to implement a portable blocking
mutex in subsequent changes. Semaphore can also be used
to efficiently wait for other things (e.g. we currently
spin to synchronize thread creation and start).

Reviewed By: vitalybuka, melver

Differential Revision: https://reviews.llvm.org/D106071
The file was modifiedcompiler-rt/lib/sanitizer_common/CMakeLists.txt
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_fuchsia.cpp
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_mac.cpp
The file was modifiedcompiler-rt/lib/sanitizer_common/tests/sanitizer_mutex_test.cpp
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_linux.cpp
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_mutex.h
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_win.cpp
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_solaris.cpp
The file was addedcompiler-rt/lib/sanitizer_common/sanitizer_mutex.cpp
The file was modifiedcompiler-rt/lib/tsan/go/buildgo.sh
The file was modifiedcompiler-rt/lib/tsan/go/build.bat
Commit ca012627cd9352d5ff5eccfadeaeabc083c8f704 by i
[docs] Update llvm-readelf supported options after D105532
The file was modifiedllvm/docs/CommandGuide/llvm-readelf.rst
Commit d634ec8d298b1a274987ca039be03e6b4c6dad80 by craig.topper
[RISCV] Refactor where in the multiclass hierarchy we add commutable VFMADD/VFMACC instructions. NFC

I'm preparing to add tail agnostic versions of VWMACC and VFWMACC
so this will make them more consistent.
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
Commit 8f0343cc9c1625e2a1560a2b2553ccb81ff605f9 by craig.topper
[RISCV] Use tail agnostic policy for fixed vector vwmacc(u).

This adds new pseudoinstructions with ForceTailAgnostic set. This
matches what we did for non-widening VMACC. We should move to a
tail policy operand on the pseudos when we expand the intrinsic
interface to include the tail policy.
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwacc.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
The file was modifiedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwaccu.ll
Commit 2e65ec10104bac8449cfc2a2c633753b6c3527b9 by craig.topper
[RISCV] Rename the fixed vector vwmacc tests to have the 'm' in their filenames. NFC
The file was addedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmacc.ll
The file was addedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmaccu.ll
The file was removedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwaccu.ll
The file was removedllvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwacc.ll
Commit 0bf4b81d57b0b4d1ecc2752be3e4ad1504ee1eb3 by stefanp
[Clang] Add an empty builtins.h file.

On Power PC some legacy compilers included a number of builtins in a
builtins.h header file. While this header file is not required to hold
builtins for clang some legacy code does try to include this file and so
this patch provides an empty version of that file.

Differential Revision: https://reviews.llvm.org/D106065
The file was modifiedclang/lib/Headers/CMakeLists.txt
The file was addedclang/test/Headers/builtins-header.c
The file was addedclang/lib/Headers/builtins.h
Commit 8fe65972cb9cbdf133131d30fb0f67ab9381ae1e by ajcbik
[mlir][sparse] minor cleanup of Merger

Removed inconsistent name prefixes, added consistency checks
on debug strings, added more assertions to verify assumptions
that may be lifted in the future.

Reviewed By: gussmith23

Differential Revision: https://reviews.llvm.org/D106108
The file was modifiedmlir/lib/Dialect/SparseTensor/Utils/Merger.cpp
Commit 5c57600b934ac9b64cd557b90560de7d9df66a1d by listmail
[tests] Precommit test for D104140
The file was modifiedllvm/test/Analysis/ScalarEvolution/trip-count-negative-stride.ll
Commit cfa4d112da8da97480c3018c68389aa06cb3efb8 by code
[compiler-rt] change write order of frexpl & frexpf so it doesn't corrupt stack ids

This was fixed in the past for `frexp`, but was not made for `frexpl` & `frexpf` https://github.com/google/sanitizers/issues/321
This patch copies the fix over to `frexpl` because it caused `frexp_interceptor.cpp` test to fail on iPhone and `frexpf` for consistency.

rdar://79652161

Reviewed By: delcypher, vitalybuka

Differential Revision: https://reviews.llvm.org/D104948
The file was addedcompiler-rt/test/asan/TestCases/frexpl_interceptor.cpp
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_common_interceptors.inc
The file was addedcompiler-rt/test/asan/TestCases/frexpf_interceptor.cpp
Commit db29c030dfea83bbdaa05408bf37d46461adf008 by dvyukov
sanitizer_common: link Synchronization.lib on Windows

Windows bot failed with:
sanitizer_win.cpp.obj : error LNK2019: unresolved external symbol WaitOnAddress referenced in function "void __cdecl __sanitizer::FutexWait(struct __sanitizer::atomic_uint32_t *,unsigned int)" (?FutexWait@__sanitizer@@YAXPEAUatomic_uint32_t@1@I@Z)
sanitizer_win.cpp.obj : error LNK2019: unresolved external symbol WakeByAddressSingle referenced in function "void __cdecl __sanitizer::FutexWake(struct __sanitizer::atomic_uint32_t *,unsigned int)" (?FutexWake@__sanitizer@@YAXPEAUatomic_uint32_t@1@I@Z)
sanitizer_win.cpp.obj : error LNK2019: unresolved external symbol WakeByAddressAll referenced in function "void __cdecl __sanitizer::FutexWake(struct __sanitizer::atomic_uint32_t *,unsigned int)" (?FutexWake@__sanitizer@@YAXPEAUatomic_uint32_t@1@I@Z)
https://lab.llvm.org/buildbot/#/builders/127/builds/14046

According to MSDN we need to link Synchronization.lib:
https://docs.microsoft.com/en-us/windows/win32/api/synchapi/nf-synchapi-waitonaddress

Differential Revision: https://reviews.llvm.org/D106167
The file was modifiedcompiler-rt/lib/sanitizer_common/sanitizer_win.cpp
Commit eef6601b0fb6d5fee32627e07be4acbf769e5c0f by huberjn
[OpenMP] Rework OpenMP remarks

This patch rewrites and reworks a few of the existing remarks to make the mmore
concise and consistent prior to writing the documentation for them.

Reviewed By: jdoerfert

Differential Revision: https://reviews.llvm.org/D105898
The file was modifiedllvm/lib/Transforms/IPO/AttributorAttributes.cpp
The file was modifiedllvm/test/Transforms/OpenMP/remove_globalization.ll
The file was modifiedllvm/test/Transforms/OpenMP/globalization_remarks.ll
The file was modifiedclang/test/OpenMP/remarks_parallel_in_multiple_target_state_machines.c
The file was modifiedllvm/test/Transforms/OpenMP/parallel_deletion_remarks.ll
The file was modifiedllvm/test/Transforms/OpenMP/custom_state_machines_remarks.ll
The file was modifiedllvm/test/Transforms/OpenMP/deduplication_remarks.ll
The file was modifiedllvm/test/Transforms/OpenMP/spmdization_remarks.ll
The file was modifiedllvm/lib/Transforms/IPO/OpenMPOpt.cpp
The file was modifiedclang/test/OpenMP/remarks_parallel_in_target_state_machine.c
Commit 2c31d5ebfbbb36de37d41b6945d0c45efa512790 by huberjn
[OpenMP] Add IDs to OpenMP remarks

This patch adds unique idenfitiers to the existing OpenMP remarks. This makes
it easier to identify the corresponding documentation for each remark that will
be hosted in the OpenMP webpage.

Depends on D105898

Reviewed By: jdoerfert

Differential Revision: https://reviews.llvm.org/D105939
The file was modifiedclang/test/OpenMP/remarks_parallel_in_multiple_target_state_machines.c
The file was modifiedllvm/include/llvm/Transforms/IPO/Attributor.h
The file was modifiedllvm/lib/Transforms/IPO/OpenMPOpt.cpp
The file was modifiedclang/test/OpenMP/remarks_parallel_in_target_state_machine.c
The file was modifiedllvm/lib/Transforms/IPO/AttributorAttributes.cpp
Commit 16164079213ded81706a9c6d00874805e2dccbdd by jhuber6
[OpenMP] Add remark documentation to the OpenMP webpage

This patch begins adding documentation for each remark emitted by
`openmp-opt`. This builds on the IDs introduced in D105939 so that users
can more easily identify each remark in the webpage.

Depends on D105939.

Reviewed By: jdoerfert

Differential Revision: https://reviews.llvm.org/D106018
The file was addedopenmp/docs/remarks/OMP101.rst
The file was addedopenmp/docs/remarks/OMP112.rst
The file was addedopenmp/docs/remarks/OMP113.rst
The file was addedopenmp/docs/remarks/OMP133.rst
The file was addedopenmp/docs/remarks/OMP121.rst
The file was addedopenmp/docs/remarks/OMP150.rst
The file was addedopenmp/docs/remarks/OMP100.rst
The file was addedopenmp/docs/remarks/OMP111.rst
The file was addedopenmp/docs/remarks/OMP132.rst
The file was addedopenmp/docs/remarks/OMP102.rst
The file was addedopenmp/docs/remarks/OMP140.rst
The file was addedopenmp/docs/remarks/OMP160.rst
The file was addedopenmp/docs/remarks/OMP130.rst
The file was addedopenmp/docs/remarks/OMP170.rst
The file was addedopenmp/docs/remarks/OMP120.rst
The file was addedopenmp/docs/remarks/OMP110.rst
The file was addedopenmp/docs/remarks/OMP131.rst
The file was modifiedopenmp/docs/remarks/OptimizationRemarks.rst
Commit b910a109f87014bfa469cf14ddcce4622bcfb552 by huberjn
[OpenMP][NFC] Update the comment header for optimizations.
The file was modifiedllvm/lib/Transforms/IPO/OpenMPOpt.cpp
Commit c8937b6cb9751807de1e69f0f0f70a9a58f8f5dc by lei
[PowerPC] Implement XL compact math builtins

Implement a subset of builtins required for compatiblilty with AIX XL compiler.

Reviewed By: nemanjai

Differential Revision: https://reviews.llvm.org/D105930
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrInfo.td
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrVSX.td
The file was modifiedclang/lib/Sema/SemaChecking.cpp
The file was modifiedllvm/include/llvm/IR/IntrinsicsPowerPC.td
The file was addedclang/test/CodeGen/builtins-ppc-xlcompat-math.c
The file was modifiedclang/test/CodeGen/builtins-ppc-xlcompat-error.c
The file was addedllvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9-64bit.ll
The file was modifiedclang/test/CodeGen/builtins-ppc-xlcompat-pwr9-64bit.c
The file was addedllvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-math.ll
The file was modifiedclang/test/CodeGen/builtins-ppc-xlcompat-pwr9.c
The file was modifiedclang/lib/Basic/Targets/PPC.cpp
The file was addedllvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9.ll
The file was modifiedclang/include/clang/Basic/BuiltinsPPC.def
Commit d2458bcdc664a469c2198dcb65b94bcc445b1028 by llvm-dev
[X86][SSE] combineX86ShufflesRecursively - bail if constant folding fails due to oneuse limits.

Fixes issue reported on D105827 where a single shuffle of a constant (with multiple uses) was caught in an infinite loop where one shuffle (UNPCKL) used an undef arg but then that got recombined to SHUFPS as the constant value had its own undef that confused matching.....
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was modifiedllvm/test/CodeGen/X86/vector-shuffle-combining.ll
Commit 58e5e504f533c369938aebd7700b5fec31e40918 by david.green
[ARM] Extra MLA vecreduce tests. NFC
The file was modifiedllvm/test/CodeGen/Thumb2/mve-vecreduce-mla.ll
The file was modifiedllvm/test/CodeGen/Thumb2/mve-vecreduce-mlapred.ll
Commit 8f806d5f5203e1e022eeaafc81f778717c62d250 by i
[test] Avoid llvm-readelf/llvm-readobj one-dash long options
The file was modifiedcompiler-rt/test/asan/TestCases/Windows/delay_dbghelp.cpp
The file was modifiedlld/test/ELF/ppc64-toc-addis-nop-lqsq.s
Commit 3f9004c19c9b790afa58bc5ae22e9c854d2afed0 by i
[llvm-readelf/llvm-readobj] Remove one-dash long options

llvm-readelf is a user-facing tool which emulates GNU readelf. Remove one-dash
long options which are not recognized by GNU style `getopt_long`. This ensures
long options cannot collide with grouped short options.

Note: the documentation (D63719)/help messages have recommended the double-dash
forms since LLVM 9.0.0.
llvm-readobj is intended as an internal tool which has some flexibility.
llvm-readelf/llvm-readobj use the same option parsing code and llvm-readobj's
one-dash long options aren't used after test migration.

Differential Revision: https://reviews.llvm.org/D106037
The file was modifiedllvm/tools/llvm-readobj/Opts.td
Commit d0f1ae6eb6eab82d2f67c61260087353a46d48ec by leairmark
Add a scalar argument case for the Fortran spread intrinsic unit test.
The file was modifiedflang/unittests/RuntimeGTest/Transformational.cpp
Commit 15267595fda5db224470134ff8c611379bf0a2af by jonathan_roelofs
[RISCV] Compose vector subregs hierarchically

This fixes the test I broke in: https://reviews.llvm.org/D105953#2883579

Differential revision: https://reviews.llvm.org/D106168
The file was modifiedllvm/lib/Target/RISCV/RISCVRegisterInfo.td
Commit 304293d85ddfaefdf02e3adb7150ffcadcc0a09a by thakis
[gn build] (semi-manually) port 6a4054ef060b
The file was modifiedllvm/utils/gn/secondary/compiler-rt/lib/sanitizer_common/BUILD.gn
Commit 1b18e9ab67cdba6bc1f99b1a91c7793371098220 by a.bataev
[PATCH] D105827: [SLP]Workaround for InsertSubVector cost.

The cost of the InsertSubvector shuffle kind cost is not complete and
may end up with just extracts + inserts costs in many cases. Added
a workaround to represent it as a generic PermuteSingleSrc, which is
still pessimistic but better than InsertSubvector.

Differential Revision: https://reviews.llvm.org/D105827
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/pr47629-inseltpoison.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/AArch64/accelerate-vector-functions.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/alternate-int-inseltpoison.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/vec_list_bias.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/vec_list_bias-inseltpoison.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/AArch64/accelerate-vector-functions-inseltpoison.ll
The file was modifiedllvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/cmp_commute-inseltpoison.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/alternate-calls.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/pr47629.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/alternate-calls-inseltpoison.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/cmp_commute.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/resched.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/alternate-int.ll
Commit f23f299c046ca017a7cddc6fc290f26f9fe09064 by martin
[libcxx] [test] Fix experimental/memory.resource.adaptor.mem/db_deallocate on Windows

The checks within the libc++experimental memory_resource class uses this
limit:

     _MaxAlign = _LIBCPP_ALIGNOF(max_align_t);

Therefore, only use max_align_t for this limit instead of using
`__STDCPP_DEFAULT_NEW_ALIGNMENT__` if available.

Differential Revision: https://reviews.llvm.org/D105905
The file was modifiedlibcxx/test/libcxx/experimental/memory/memory.resource.adaptor/memory.resource.adaptor.mem/db_deallocate.pass.cpp
Commit df1c3aaa17432461f796b1747459e61bebcba736 by code
[NFC][compiler-rt][test] pass through MallocNanoZone to iossim env

This is required for no-fd.cpp test

rdar://79354597

Differential Revision: https://reviews.llvm.org/D106174
The file was modifiedcompiler-rt/test/sanitizer_common/ios_commands/iossim_run.py
Commit fa3231eb1810500a4d34d9daa6403dae4f5921b8 by i
[COFF][test] Fix llvm-readobj tests
The file was modifiedlld/test/COFF/secidx-absolute.s
The file was modifiedlld/test/COFF/secrel-common.s
Commit 9637848f51af0e770c6d19b6aa020250bf1d0c0f by Amara Emerson
[GlobalISel] Fix non-pow-2 legalization of s56 stores.

s56 stores are broken down into s32 + s24 stores. During this step
both of those new stores use an anyextended s64 value, resulting in
truncating stores. With s56, the s24 requires another lower step to
make it legal, and we were crashing because we didn't expect non-pow-2
stores to also be truncating as well.

Differential Revision: https://reviews.llvm.org/D106183
The file was modifiedllvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/legalize-non-pow2-load-store.mir
Commit 1daaf1df56ce86968d863c749cc7f5b31c553c4a by llvmgnsyncbot
[gn build] Port 0bf4b81d57b0
The file was modifiedllvm/utils/gn/secondary/clang/lib/Headers/BUILD.gn
Commit da3dbfcacf9abb40d482bff5ed61be9ebfb058b5 by a.bataev
[SLP]Improve calculations of the cost for reused/reordered scalars.

Part of D105020. Also, fixed FIXMEs that need to use wider vector type
when trying to calculate the cost of reused scalars. This may cause
regressions unless D100486 is landed to improve the cost estimations
for long vectors shuffling.

Differential Revision: https://reviews.llvm.org/D106060
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/tiny-tree.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/reduction-logical.ll
The file was modifiedllvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Commit 8b86b3a846eea066a11583a3316cd461311cfecd by gcmn
[Bazel] Use bazel_skylib paths for paths munging

We do a lot of path munging and bazel_sklyib is a pretty reasonable dep.

Reviewed By: jpienaar

Differential Revision: https://reviews.llvm.org/D106175
The file was modifiedutils/bazel/examples/submodule/WORKSPACE
The file was modifiedutils/bazel/llvm_configs/BUILD.bazel
The file was modifiedutils/bazel/configure.bzl
The file was modifiedutils/bazel/examples/http_archive/WORKSPACE
The file was modifiedutils/bazel/WORKSPACE
The file was modifiedutils/bazel/llvm-project-overlay/mlir/tblgen.bzl
Commit 9c5b73fef44b42973cd0cf08242e7144d24030e8 by gcmn
[Bazel] Make gentbl_test compatible with coverage

Add explicit coverage provider. Also remove output_to_genfiles which
isn't necessary for this test (it's just copy-pasta from gentbl_rule,
which needs it for output C++ header files).

Reviewed By: jpienaar

Differential Revision: https://reviews.llvm.org/D106115
The file was modifiedutils/bazel/llvm-project-overlay/mlir/tblgen.bzl
Commit b92f28cc4347372517bf756fe4d392aed167699a by gcmn
[Bazel] Add examples to bazelignore

This avoids Bazel recursing into these directories when overlayed, which
will break if someone has run Bazel in these dirs (which would only be
successful with the http_archive example) because of the Bazel directory
symlinks (already gitignored).

Reviewed By: jpienaar

Differential Revision: https://reviews.llvm.org/D105357
The file was modifiedutils/bazel/.bazelignore
Commit 68ec4aa63b4ba762a634485b51b25b21257e5882 by joker.eph
Add `lli` as dependency of MLIR integration tests

This fixes running `ninja check-mlir` from a clean build when
the integration tests are enabled.
The file was modifiedmlir/test/CMakeLists.txt
Commit 35a18a981f6b0f67899baec46be0086dc1aad757 by lei
[PowerPC] Implement intrinsics for mtfsf[i]

This provides intrinsics for emitting instructions that set the FPSCR (`mtfsf/mtfsfi`).

The patch also conservatively marks the rounding mode as an implicit def for both since they both may set the rounding mode depending on the operands.

Reviewed By: #powerpc, qiucf

Differential Revision: https://reviews.llvm.org/D105957
The file was modifiedllvm/lib/Target/PowerPC/P9InstrResources.td
The file was modifiedllvm/include/llvm/IR/IntrinsicsPowerPC.td
The file was modifiedclang/lib/CodeGen/CGBuiltin.cpp
The file was modifiedclang/test/CodeGen/builtins-ppc-xlcompat-math.c
The file was addedllvm/test/CodeGen/PowerPC/fpscr-intrinsics.ll
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrInfo.td
The file was modifiedllvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-math.ll
Commit 8e3b5cb39eef462943ed7556469604ce25c07a1d by samitolvanen
ThinLTO: Fix inline assembly references to static functions with CFI

Create an internal alias with the original name for static functions
that are renamed in promoteInternals to avoid breaking inline
assembly references to them. This version uses module inline assembly
to avoid issues with LowerTypeTestsModule.

Link: https://github.com/ClangBuiltLinux/linux/issues/1354

Reviewed By: nickdesaulniers, pcc

Differential Revision: https://reviews.llvm.org/D104058
The file was modifiedllvm/test/Transforms/ThinLTOBitcodeWriter/split-vfunc-internal.ll
The file was modifiedllvm/lib/Transforms/IPO/ThinLTOBitcodeWriter.cpp
The file was modifiedllvm/test/Transforms/ThinLTOBitcodeWriter/split-internal2.ll
The file was modifiedllvm/test/ThinLTO/X86/devirt2.ll
The file was addedllvm/test/Transforms/ThinLTOBitcodeWriter/cfi-icall-static-inline-asm.ll
Commit 0ad1d9fdf22dad41312e02b8bc990bf58ce1744c by samitolvanen
Revert "ThinLTO: Fix inline assembly references to static functions with CFI"

This reverts commit 8e3b5cb39eef462943ed7556469604ce25c07a1d.

Reverting to investigate test failures.
The file was modifiedllvm/test/ThinLTO/X86/devirt2.ll
The file was modifiedllvm/test/Transforms/ThinLTOBitcodeWriter/split-internal2.ll
The file was modifiedllvm/lib/Transforms/IPO/ThinLTOBitcodeWriter.cpp
The file was modifiedllvm/test/Transforms/ThinLTOBitcodeWriter/split-vfunc-internal.ll
The file was removedllvm/test/Transforms/ThinLTOBitcodeWriter/cfi-icall-static-inline-asm.ll
Commit ad8e75caa2ebface54c92d7e4d7dc21c3166b6c6 by david.green
[ARM] Fix for matching reductions that are both sext and zext.

Fix a silly mistake that was not making sure that _both_ operands were
the correct extend code.
The file was modifiedllvm/test/CodeGen/Thumb2/mve-vecreduce-mla.ll
The file was modifiedllvm/lib/Target/ARM/ARMISelLowering.cpp
The file was modifiedllvm/test/CodeGen/Thumb2/mve-vecreduce-mlapred.ll
Commit 1f71bcabb77df482cc0dc7bab90a73e15f3e347b by joker.eph
Build libSupport with -Werror=global-constructors (NFC)

Ensure that libSupport does not carry any static global initializer.
libSupport can be embedded in use cases where we don't want to load all
cl::opt unless we want to parse the command line.
ManagedStatic can be used to enable lazy-initialization of globals.
The file was modifiedllvm/lib/Support/CMakeLists.txt
Commit c14f26846e75fa851edcb1ecd9ecc66e22442e36 by Vitaly Buka
[sanitizer] Fix test build on Windows
The file was modifiedcompiler-rt/lib/sanitizer_common/tests/sanitizer_mutex_test.cpp
Commit 263fe133ed2e7a12d1b478cfd18c7698f2007706 by i
[Bazel] Delete blank line to make buildifier happy
The file was modifiedutils/bazel/llvm-project-overlay/mlir/tblgen.bzl
Commit e37bbfe59ccd4ea0da95c02e9f36172239f4f0c3 by cjdb
[libcxx][modules] protects users from relying on libc++ detail headers (1/n)

libc++ has started splicing standard library headers into much more
fine-grained content for maintainability. It's very likely that outdated
and naive tooling (some of which is outside of LLVM's scope) will
suggest users include things such as `<__algorithm/find.h>` instead of
`<algorithm>`, and Hyrum's law suggests that users will eventually begin
to rely on this without the help of tooling. As such, this commit
intends to protect users from themselves, by making it a hard error for
anyone outside of the standard library to include libc++ detail headers.

This is the first of four patches. Patch #2 will solve the problem for
pre-processor `#include`s; patches #3 and #4 will solve the problem for
`<__tree>` and `<__hash_table>` (since I've never touched the test cases
that are failing for these two, I want to split them out into their own
commits to be extra careful). Patch #5 will concern itself with
`<__threading_support>`, which intersects with libcxxabi (which I know
even less about).

Differential Revision: https://reviews.llvm.org/D105932
The file was addedlibcxx/test/libcxx/diagnostics/detail.headers/iterator/istreambuf_iterator.module.verify.cpp
The file was modifiedlibcxx/include/module.modulemap
The file was addedlibcxx/test/libcxx/diagnostics/detail.headers/algorithm/remove_copy_if.module.verify.cpp
The file was addedlibcxx/test/libcxx/diagnostics/detail.headers/algorithm/partition_point.module.verify.cpp
The file was addedlibcxx/test/libcxx/diagnostics/detail.headers/memory/pointer_traits.module.verify.cpp
The file was addedlibcxx/test/libcxx/diagnostics/detail.headers/functional/weak_result_type.module.verify.cpp
The file was addedlibcxx/test/libcxx/diagnostics/detail.headers/algorithm/find_if.module.verify.cpp
The file was addedlibcxx/test/libcxx/diagnostics/detail.headers/iterator/move_iterator.module.verify.cpp
The file was addedlibcxx/test/libcxx/diagnostics/detail.headers/algorithm/copy_if.module.verify.cpp
The file was addedlibcxx/test/libcxx/diagnostics/detail.headers/iterator/back_insert_iterator.module.verify.cpp
The file was addedlibcxx/test/libcxx/diagnostics/detail.headers/iterator/reverse_iterator.module.verify.cpp
The file was addedlibcxx/test/libcxx/diagnostics/detail.headers/algorithm/search_n.module.verify.cpp
The file was addedlibcxx/test/libcxx/diagnostics/detail.headers/algorithm/shuffle.module.verify.cpp
The file was addedlibcxx/test/libcxx/diagnostics/detail.headers/memory/allocator_arg_t.module.verify.cpp
The file was addedlibcxx/test/libcxx/diagnostics/detail.headers/algorithm/is_partitioned.module.verify.cpp
The file was addedlibcxx/test/libcxx/diagnostics/detail.headers/algorithm/set_symmetric_difference.module.verify.cpp
The file was addedlibcxx/test/libcxx/diagnostics/detail.headers/functional/perfect_forward.module.verify.cpp
The file was addedlibcxx/test/libcxx/diagnostics/detail.headers/algorithm/stable_sort.module.verify.cpp
The file was addedlibcxx/test/libcxx/diagnostics/detail.headers/algorithm/nth_element.module.verify.cpp
The file was addedlibcxx/test/libcxx/diagnostics/detail.headers/node_handle.module.verify.cpp
The file was addedlibcxx/test/libcxx/diagnostics/detail.headers/algorithm/sort.module.verify.cpp
The file was addedlibcxx/test/libcxx/diagnostics/detail.headers/memory/allocator.module.verify.cpp
The file was addedlibcxx/test/libcxx/diagnostics/detail.headers/memory/raw_storage_iterator.module.verify.cpp
The file was addedlibcxx/test/libcxx/diagnostics/detail.headers/utility/as_const.module.verify.cpp
The file was addedlibcxx/test/libcxx/diagnostics/detail.headers/memory/uninitialized_algorithms.module.verify.cpp
The file was addedlibcxx/test/libcxx/diagnostics/detail.headers/algorithm/count_if.module.verify.cpp
The file was addedlibcxx/test/libcxx/diagnostics/detail.headers/utility/piecewise_construct.module.verify.cpp
The file was addedlibcxx/test/libcxx/diagnostics/detail.headers/functional/unary_function.module.verify.cpp
The file was addedlibcxx/test/libcxx/diagnostics/detail.headers/utility/pair.module.verify.cpp
The file was addedlibcxx/test/libcxx/diagnostics/detail.headers/algorithm/transform.module.verify.cpp
The file was addedlibcxx/test/libcxx/diagnostics/detail.headers/functional/pointer_to_binary_function.module.verify.cpp
The file was addedlibcxx/test/libcxx/diagnostics/detail.headers/ranges/enable_view.module.verify.cpp
The file was addedlibcxx/test/libcxx/diagnostics/detail.headers/iterator/reverse_access.module.verify.cpp
The file was addedlibcxx/test/libcxx/diagnostics/detail.headers/algorithm/find_if_not.module.verify.cpp
The file was addedlibcxx/test/libcxx/diagnostics/detail.headers/utility/exchange.module.verify.cpp
The file was addedlibcxx/test/libcxx/diagnostics/detail.headers/functional/binder2nd.module.verify.cpp
The file was addedlibcxx/test/libcxx/diagnostics/detail.headers/ranges/drop_view.module.verify.cpp
The file was addedlibcxx/test/libcxx/diagnostics/detail.headers/algorithm/fill_n.module.verify.cpp
The file was addedlibcxx/test/libcxx/diagnostics/detail.headers/functional/binary_negate.module.verify.cpp
The file was addedlibcxx/test/libcxx/diagnostics/detail.headers/algorithm/comp.module.verify.cpp
The file was addedlibcxx/test/libcxx/diagnostics/detail.headers/algorithm/for_each.module.verify.cpp
The file was addedlibcxx/test/libcxx/diagnostics/detail.headers/algorithm/half_positive.module.verify.cpp