Progress:
In progressChanges

Changes from Git (git http://labmaster3.local/git/llvm-project.git)

Summary

  1. [NFC] Change VFShape so it contains an ElementCount rather than seperate VF and IsScalable properties. (details)
  2. [SLP]Fix costs calculations. (details)
  3. [mlir] split type conversion to two lines for GCC's sake (details)
  4. [AArch65][SVE] Remove vector_splice from AddedComplexity pattern (details)
  5. Revert "[SLP]Fix costs calculations." (details)
  6. [SVE] Fix casts to <FixedVectorType> in truncateToMinimalBitwidths (details)
  7. [SimplifyCFG] Improve store speculation check (details)
  8. AArch64: support i128 (& larger) returns in GlobalISel (details)
  9. [ARM] Ensure correct regclass in distributing postinc (details)
  10. [AMDGPU] Fix MMO for raw/struct buffer access with non-constant offset (details)
  11. [AMDGPU] Pre-commit global-isel test case for D106451 (details)
  12. [AMDGPU][GISel] Fix MMO for raw/struct buffer access with non-constant offset (details)
  13. [llvm-readobj] Display multiple function names for stack size entries (details)
  14. [OpenCL] Change default standard version to CL1.2 (details)
  15. [SLP]Fix costs calculations. (details)
  16. [LV] Add test to store a first-order rec via interleave group. (details)
  17. [InstrRef][AArch64][1/4] Accept constant physreg variable locations (details)
  18. [Analyzer][solver][NFC] print constraints deterministically (ordered by their string representation) (details)
  19. Simplify away some SmallVector copies. NFCI. (details)
  20. [IR] Consider non-willreturn as side effect (PR50511) (details)
  21. [libc++][ci] Detect not committed generated files. (details)
  22. Recommit "[VPlan] Add recipe for first-order rec phis, make splicing explicit." (details)
  23. [SystemZ] Add support for new cpu architecture - arch14 (details)
Commit 8a8d01d58c14c65d6b1a40bf3335c72f6fcd1388 by paul.walker
[NFC] Change VFShape so it contains an ElementCount rather than seperate VF and IsScalable properties.

Differential Revision: https://reviews.llvm.org/D106750
The file was modifiedllvm/include/llvm/Analysis/VectorUtils.h
The file was modifiedllvm/lib/Analysis/VFABIDemangling.cpp
The file was modifiedllvm/unittests/Analysis/VectorFunctionABITest.cpp
The file was modifiedllvm/unittests/Analysis/VectorUtilsTest.cpp
Commit a053afed49897aa34e08287f91c5255efa4e5131 by a.bataev
[SLP]Fix costs calculations.

Need to fix several cost-related problems. The final type may be defined
incorrectly because of to early definition (we may end up with the wider
type), the CommonCost should not be redefined in ExtractElements
cost related calculations and the shuffle of the final insertelements
vectors should be calculated as a cost of single vector permutations
+ costs of two vector permutations for other n-1 incoming vectors.

Differential Revision: https://reviews.llvm.org/D106578
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/vec_list_bias-inseltpoison.ll
The file was modifiedllvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/vec_list_bias.ll
Commit 539437e288f2395288a46a550c4c3070c4b16101 by tpopp
[mlir] split type conversion to two lines for GCC's sake
The file was modifiedmlir/lib/Transforms/BufferDeallocation.cpp
Commit bf28111ebdb760f46f168c867f7e8453c23814ed by caroline.concatto
[AArch65][SVE] Remove vector_splice from AddedComplexity pattern

The pattern for vector_splice with Index equal or bigger than
zero was misplaced in the AddedComplexity = 1 pattern in the AArch64
tablegen file. This patch fixes it by removing vector_splice pattern
from inside AddedComplexity = 1.
The file was modifiedllvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
Commit d7cb2a07967791867c245a6e2e8e4214d69140f7 by a.bataev
Revert "[SLP]Fix costs calculations."

This reverts commit a053afed49897aa34e08287f91c5255efa4e5131 to fix
buildbots.
The file was modifiedllvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/vec_list_bias.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/vec_list_bias-inseltpoison.ll
Commit e484e1ae03325823c469684d7d1532f2aadbe98d by kerry.mclaughlin
[SVE] Fix casts to <FixedVectorType> in truncateToMinimalBitwidths

Fixes more casts to `<FixedVectorType>` for the cases where the
instruction is a Insert/ExtractElementInst.

For fixed-width, this part of truncateToMinimalBitWidths is tested by
AArch64/type-shrinkage-insertelt.ll. I attempted to write a test case for this part
of truncateToMinimalBitWidths which uses scalable vectors, but was unable to add
one. The tests in type-shrinkage-insertelt.ll rely on scalarization to create extract
element instructions for instance, which is not possible for scalable vectors.

Reviewed By: david-arm

Differential Revision: https://reviews.llvm.org/D106163
The file was modifiedllvm/lib/Transforms/Vectorize/LoopVectorize.cpp
Commit ffb3277b0036909a8e622d5758a1e2850eabfd19 by nikita.ppv
[SimplifyCFG] Improve store speculation check

isSafeToSpeculateStore() looks for a preceding store to the same
location to make sure that introducing a new store of the same
value is safe. It currently bails on intervening mayHaveSideEffect()
instructions. However, I believe just checking mayWriteToMemory()
is sufficient there -- we just need to make sure that we know which
value was stored, we don't care if we can unwind in the meantime.

While looking into this, I started having some doubts about the
correctness of the transform with regard to thread safety. While
we don't try to hoist non-simple stores, I believe we also need
to make sure that the preceding store is simple as well. Otherwise
we could introduce a spurious non-atomic write after an atomic write
-- under our memory model this would result in a subsequent undef
atomic read, even if the second write stores the same value as the
first.

Example: https://alive2.llvm.org/ce/z/q_3YAL

Differential Revision: https://reviews.llvm.org/D106742
The file was modifiedllvm/lib/Transforms/Utils/SimplifyCFG.cpp
The file was modifiedllvm/test/Transforms/SimplifyCFG/speculate-store.ll
Commit a487a49acc5a172909d706ffc43240ced1ac0693 by Tim Northover
AArch64: support i128 (& larger) returns in GlobalISel
The file was addedllvm/test/CodeGen/AArch64/GlobalISel/translate-ret.ll
The file was modifiedllvm/test/CodeGen/AArch64/arm64-subvector-extend.ll
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
Commit 010f8e305705acb5128f409256e7f22ff3adc780 by david.green
[ARM] Ensure correct regclass in distributing postinc

The register class required for some MVE loads/stores is more
constrained than the register we use when creating postinc. Make sure we
constrain the register class to keep the code correct.
The file was modifiedllvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
The file was modifiedllvm/test/CodeGen/Thumb2/mve-postinc-distribute.mir
Commit 9ac10658aeda44d8a90ae372c1478610d143c8bb by jay.foad
[AMDGPU] Fix MMO for raw/struct buffer access with non-constant offset

Codegen for the raw/struct buffer access intrinsics would update the
offset in the MMO to reflect the combined offset, if it was known to be
constant. If the combined offset was not known to be constant, or if
there was an index, it would set the offset in the MMO to 0. This is
unsafe because it makes it look like the access does not alias with
another access with a fixed non-zero offset.

Fix these cases by setting the pointer in the MMO to null, to reflect
the fact that we do not have any known IR value pointer + constant
offset for the access.

Differential Revision: https://reviews.llvm.org/D106284
The file was modifiedllvm/test/CodeGen/AMDGPU/buffer-schedule.ll
The file was modifiedllvm/lib/Target/AMDGPU/SIISelLowering.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/buffer-intrinsics-mmo-offsets.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/extract_subvector_vec4_vec3.ll
Commit 683b9ed0d593f249e992bed63768986b37b49dbb by jay.foad
[AMDGPU] Pre-commit global-isel test case for D106451

This test case shows the scheduler wrongly reordering two buffer
accesses that might alias.
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/buffer-schedule.ll
Commit 59f6865231ff7d233e3728b21de2e5aa35189eb3 by jay.foad
[AMDGPU][GISel] Fix MMO for raw/struct buffer access with non-constant offset

Codegen for the raw/struct buffer access intrinsics would update the
offset in the MMO to reflect the combined offset, if it was known to be
constant. If the combined offset was not known to be constant, or if
there was an index, it would set the offset in the MMO to 0. This is
unsafe because it makes it look like the access does not alias with
another access with a fixed non-zero offset.

Fix these cases by setting the pointer in the MMO to null, to reflect
the fact that we do not have any known IR value pointer + constant
offset for the access.

D106284 did this for SelectionDAG. This is the corresponding fix for
GlobalISel.

Differential Revision: https://reviews.llvm.org/D106451
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.add.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.format.f16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buffer.load.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.load.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.format.f32.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.cmpswap.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/buffer-schedule.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.format.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buffer.store.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.fadd.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.load.f16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.cmpswap.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.tbuffer.load.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.fadd.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.tbuffer.load.f16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.raw.buffer.load.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.store.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.store.format.f32.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.add.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.f16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.store.format.f16.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.format.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.i8.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.format.f16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.format.f16.ll
Commit 87ed73fe6e01591998eed0dd769353f88919d056 by gbreynoo
[llvm-readobj] Display multiple function names for stack size entries

The current implementation of displaying .stack_size information
presumes that each entry represents a single function but this is not
always the case. For example with the use of ICF multiple functions can
be represented with the same code, meaning that the address found in a
.stack_size entry corresponds to multiple function symbols.
This change allows multiple function names to be displayed when
appropriate.

Differential Revision: https://reviews.llvm.org/D105884
The file was modifiedllvm/tools/llvm-readobj/ELFDumper.cpp
The file was modifiedllvm/test/Object/BPF/yaml2obj-elf-bpf-rel.yaml
The file was modifiedllvm/test/tools/llvm-readobj/ELF/stack-sizes.test
Commit 81600160b3f926746d02c52003d81180941fe9d0 by anastasia.stulova
[OpenCL] Change default standard version to CL1.2

Set default version for OpenCL C to 1.2. This means that the
absence of any standard flag will be equivalent to passing
'-cl-std=CL1.2'.

Note that this patch also fixes incorrect version check for
the pointer to pointer kernel arguments diagnostic and
atomic test.

Differential Revision: https://reviews.llvm.org/D106504
The file was modifiedclang/test/SemaOpenCL/fp64-fp16-options.cl
The file was modifiedclang/lib/Frontend/CompilerInvocation.cpp
The file was modifiedclang/test/SemaOpenCL/func.cl
The file was modifiedclang/test/Parser/opencl-cl20.cl
The file was modifiedclang/lib/Sema/SemaDecl.cpp
The file was modifiedclang/test/Parser/opencl-atomics-cl20.cl
The file was modifiedclang/test/Parser/opencl-storage-class.cl
The file was modifiedclang/test/CodeGenOpenCL/spir_version.cl
The file was modifiedclang/test/Preprocessor/predefined-macros.c
Commit 6ca48efcf6e16adfcf33688d86de7bd2bb75a49a by a.bataev
[SLP]Fix costs calculations.

Need to fix several cost-related problems. The final type may be defined
incorrectly because of to early definition (we may end up with the wider
type), the CommonCost should not be redefined in ExtractElements
cost related calculations and the shuffle of the final insertelements
vectors should be calculated as a cost of single vector permutations
+ costs of two vector permutations for other n-1 incoming vectors.

Differential Revision: https://reviews.llvm.org/D106578
The file was modifiedllvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/vec_list_bias.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/vec_list_bias-inseltpoison.ll
Commit 93664503be6b3f47269cf617f8c46b6ce95f8076 by flo
[LV] Add test to store a first-order rec via interleave group.

This is a reduced version of the reproducer from
https://bugs.chromium.org/p/chromium/issues/detail?id=1232798#c2
The file was addedllvm/test/Transforms/LoopVectorize/AArch64/interleaved-store-of-first-order-recurrence.ll
Commit f86694cb808f22253e00742ccd279760ef0c688d by jeremy.morse
[InstrRef][AArch64][1/4] Accept constant physreg variable locations

Late in SelectionDAG we join up instruction numbers with their defining
instructions, if it couldn't be done during the main part of SelectionDAG.
One exception is function arguments, where we have to point a DBG_PHI
instruction at the incoming live register, as they don't have a defining
instruction. This patch adds another exception, for constant physregs, like
aarch64 has.

It may seem wasteful to use two instructions where we could use a single
DBG_VALUE, however the whole point of instruction referencing is to
decouple the identification of values from the specification of where
variable location ranges start.

(Part of my aarch64 work to ease adoption of  instruction referencing, as
in the meta comment on D104520)

Differential Revision: https://reviews.llvm.org/D104520
The file was addedllvm/test/DebugInfo/AArch64/instr-ref-const-physreg.ll
The file was modifiedllvm/lib/CodeGen/MachineFunction.cpp
Commit 4761321d49db01dce1e308f900add033cc26fb47 by gabor.marton
[Analyzer][solver][NFC] print constraints deterministically (ordered by their string representation)

This change is an extension to D103967 where I added dump methods for
(dis)equality classes of the State. There, the (dis)equality classes and their
contents are dumped in an ordered fashion, they are ordered based on their
string representation. This is very useful once we start to use FileCheck to
test the State dump in certain tests.

Differential Revision: https://reviews.llvm.org/D106642
The file was modifiedclang/lib/StaticAnalyzer/Core/RangeConstraintManager.cpp
Commit 404f0d4f7cc7b7497c9725c6c6f20b21df8611bb by benny.kra
Simplify away some SmallVector copies. NFCI.

The lifetime of the initializer list is the full expression, so we can
skip storing it in a temporary vector.
The file was modifiedllvm/include/llvm/IR/DerivedTypes.h
The file was modifiedllvm/include/llvm/IR/Constants.h
Commit 33146857e9840a92840d48bbc3483e34ea545fc7 by nikita.ppv
[IR] Consider non-willreturn as side effect (PR50511)

This adjusts mayHaveSideEffect() to return true for !willReturn()
instructions. Just like other side-effects, non-willreturn calls
(aka "divergence") cannot be removed and cannot be reordered relative
to other side effects. This fixes a number of bugs where
non-willreturn calls are either incorrectly dropped or moved. In
particular, it also fixes the last open problem in
https://bugs.llvm.org/show_bug.cgi?id=50511.

I performed a cursory review of all current mayHaveSideEffect()
uses, which convinced me that these are indeed the desired default
semantics. Places that do not want to consider non-willreturn as a
sideeffect generally do not want mayHaveSideEffect() semantics at
all. I identified two such cases, which are addressed by D106591
and D106742. Finally, there is a use in SCEV for which we don't
really have an appropriate API right now -- what it wants is
basically "would this be considered forward progress". I've just
spelled out the previous semantics there.

Differential Revision: https://reviews.llvm.org/D106749
The file was modifiedllvm/test/Transforms/LICM/sinking.ll
The file was modifiedllvm/test/Transforms/SCCP/calltest.ll
The file was modifiedllvm/include/llvm/IR/Instruction.h
The file was modifiedllvm/lib/Transforms/Scalar/ADCE.cpp
The file was modifiedllvm/lib/Analysis/DemandedBits.cpp
The file was modifiedllvm/test/Transforms/LoopDeletion/noop-loops-with-subloops.ll
The file was modifiedllvm/lib/Analysis/ScalarEvolution.cpp
The file was modifiedllvm/lib/IR/Instruction.cpp
Commit 1139fd4270c7462a4bce8e1e91e6be174dcae88f by koraq
[libc++][ci] Detect not committed generated files.

The Generated output CI job only tests for modified files. This job
should also fail the generated output contains new files.

It would be possible to test modified and untracked files in one
execution of `git ls-files`. However the diff is stored as an artifact
so the execution of `git diff` would still be required.

Discussion: Would it be better to do `git ls-files -om` and remove the
excution of
`! grep -q '^--- a' ${BUILD_DIR}/generated_output.patch || false` ?
(Obviously then the name `generated_output.untracked` should change to
something like `generated_output.status`)

Reviewed By: #libc, ldionne

Differential Revision: https://reviews.llvm.org/D106534
The file was modifiedlibcxx/utils/ci/buildkite-pipeline.yml
The file was modifiedlibcxx/utils/ci/run-buildbot
Commit 7a1e73f0b9fcfec0e90aff735f0ac4cfb6b9ec41 by flo
Recommit "[VPlan] Add recipe for first-order rec phis, make splicing explicit."

This reverts the revert commit b1777b04dc4b1a9fee0e7effa7e177892ab32ef0.

The patch originally got reverted due to a crash:
https://bugs.chromium.org/p/chromium/issues/detail?id=1232798#c2

The underlying issue was that we were not using the stored values from
the modified memory recipes, but the out-of-date values directly from
the IR (accessed via the VPlan). This should be fixed in d995d6376. A
reduced version of the reproducer has been added in 93664503be6b.
The file was modifiedllvm/lib/Transforms/Vectorize/VPlan.h
The file was modifiedllvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
The file was modifiedllvm/test/Transforms/LoopVectorize/first-order-recurrence-sink-replicate-region.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/first-order-recurrence.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/induction.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/interleaved-accesses.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/first-order-recurrence-complex.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/vplan-sink-scalars-and-merge.ll
The file was modifiedllvm/lib/Transforms/Vectorize/VPlanValue.h
The file was modifiedllvm/test/Transforms/LoopVectorize/scalable-first-order-recurrence.ll
The file was modifiedllvm/lib/Transforms/Vectorize/LoopVectorize.cpp
The file was modifiedllvm/lib/Transforms/Vectorize/VPlan.cpp
Commit 8cd8120a7b5d4c6f7674679b53477b51fd054a27 by ulrich.weigand
[SystemZ] Add support for new cpu architecture - arch14

This patch adds support for the next-generation arch14
CPU architecture to the SystemZ backend.

This includes:
- Basic support for the new processor and its features.
- Detection of arch14 as host processor.
- Assembler/disassembler support for new instructions.
- New LLVM intrinsics for certain new instructions.
- Support for low-level builtins mapped to new LLVM intrinsics.
- New high-level intrinsics in vecintrin.h.
- Indicate support by defining  __VEC__ == 10304.

Note: No currently available Z system supports the arch14
architecture.  Once new systems become available, the
official system name will be added as supported -march name.
The file was modifiedllvm/test/MC/SystemZ/insn-bad-z15.s
The file was addedclang/test/CodeGen/SystemZ/builtins-systemz-vector4-error.c
The file was modifiedclang/test/Preprocessor/predefined-arch-macros.c
The file was modifiedclang/lib/Basic/Targets/SystemZ.h
The file was modifiedllvm/lib/Target/SystemZ/SystemZInstrInfo.td
The file was modifiedclang/lib/Headers/vecintrin.h
The file was addedllvm/test/MC/SystemZ/insn-bad-arch14.s
The file was modifiedllvm/lib/Target/SystemZ/SystemZProcessors.td
The file was modifiedclang/test/CodeGen/SystemZ/systemz-abi-vector.c
The file was addedclang/test/CodeGen/SystemZ/builtins-systemz-zvector4-error.c
The file was modifiedllvm/lib/Target/SystemZ/SystemZFeatures.td
The file was modifiedclang/lib/Basic/Targets/SystemZ.cpp
The file was addedllvm/test/MC/SystemZ/insn-good-arch14.s
The file was modifiedllvm/unittests/Support/Host.cpp
The file was modifiedclang/test/CodeGen/target-data.c
The file was modifiedllvm/lib/Target/SystemZ/SystemZSubtarget.cpp
The file was modifiedclang/lib/Sema/SemaChecking.cpp
The file was modifiedllvm/lib/Target/SystemZ/SystemZSubtarget.h
The file was addedclang/test/CodeGen/SystemZ/builtins-systemz-zvector4.c
The file was modifiedclang/test/Misc/target-invalid-cpu-note.c
The file was modifiedllvm/include/llvm/IR/IntrinsicsSystemZ.td
The file was modifiedllvm/lib/Target/SystemZ/SystemZInstrSystem.td
The file was addedllvm/test/CodeGen/SystemZ/vec-intrinsics-04.ll
The file was modifiedllvm/lib/Target/SystemZ/SystemZInstrFormats.td
The file was modifiedllvm/lib/Target/SystemZ/SystemZInstrVector.td
The file was modifiedclang/test/CodeGen/SystemZ/systemz-abi.c
The file was addedllvm/test/MC/Disassembler/SystemZ/insns-arch14.txt
The file was modifiedclang/test/Driver/systemz-march.c
The file was addedclang/test/CodeGen/SystemZ/builtins-systemz-vector4.c
The file was modifiedclang/include/clang/Basic/BuiltinsSystemZ.def
The file was modifiedllvm/lib/Support/Host.cpp