Started 2 mo 24 days ago
Took 10 hr on green-dragon-06

Build #7995 (Jul 31, 2021 4:13:10 AM)

Changes

Git (git http://labmaster3.local/git/llvm-project.git)

  1. [builtins] Try to ensure single copy of emulated TLS state (detail)
  2. [libomptarget][nfc] Only set cuda-path for nvptx tests (detail)
  3. [mlir][spirv] Fix storing bool with proper storage capabilities (detail)
  4. [mlir][spirv] Fix loading bool with proper storage capabilities (detail)
  5. [mlir][spirv] Add support for i8 serialization (detail)
  6. [libcxx][docs] Take locks on the last three views. (detail)
  7. [flang] Produce proper "preprocessor output" for -E option (detail)
  8. [sanitizer] Remove cpplint (detail)
  9. [libc] Move FPExceptMatcher out of TestHelpers.h (detail)
  10. [vscode-mlir] Update package.json in preparation for publishing (detail)
  11. [mlir-vscode] Create a proper output channel for the MLIRContext (detail)
  12. [profile] Fix profile merging with binary IDs (detail)
  13. [vscode-mlir] Fix the package repo url. (detail)
  14. [sanitizer] Remove cpplint annotations (detail)
  15. [libc] Add trigonometric and exponential functions to the windows config. (detail)
  16. Revert "[lldb] [DWARF-5] Be lazier about loading .dwo files" (detail)
  17. Revert "[profile] Fix profile merging with binary IDs" (detail)
  18. [profile] Fix profile merging with binary IDs (detail)
  19. Revert "[clang][cache] Update Fuchsia-stage2.cmake to create hwasan multilibs" (detail)
  20. [NFC][sanitizer] clang-format few files (detail)
  21. tsan: always setup sigaction signal handler (detail)
  22. tsan: remove "expected" races (detail)
  23. sanitizers: build tests with -g (detail)
  24. tsan: introduce Tid and StackID typedefs (detail)
  25. tsan: prevent insertion of memset into BenignRaceImpl (detail)
  26. [profile][test] Delete --path-equivalence=/tmp,%S (detail)
  27. [lldb] [DWARF-5] Be lazier about loading .dwo files (detail)
  28. [Clang][AArch64] Inline assembly support for the ACLE type 'data512_t' (detail)
  29. [AArch64] Add a Machine Value Type for 8 consecutive registers (detail)
  30. [AArch64] Legalize MVT::i64x8 in DAG isel lowering (detail)

Started by upstream project clang-stage2-cmake-RgSan_relay build number 3658
originally caused by:

This run spent:

  • 59 min waiting;
  • 10 hr build duration;
  • 11 hr total from scheduled to completion.
Revision: 7d940432c46be83b8fcb5dbefee439585fa820cd
Repository: http://labmaster3.local/git/llvm-project.git
  • detached
Revision: 855fdb4cdc09e306370533c0715897e6ac7f3027
Repository: http://labmaster3.local/git/llvm-zorg.git
  • refs/remotes/origin/main
LLVM/Clang Warnings: 1 warning.
    Test Result (5 failures / ±0)Show all failed tests >>>

    Identified problems

    Regression test failed

    This build failed because a regression test in the test suite FAILed. See the test report for details.
    Indication 1

    Compile Error

    This build failed because of a compile error. Below is a list of all errors in the build log:
    Indication 2

    Ninja target failed

    Below is a link to the first failed ninja target.
    Indication 3