SuccessChanges

Summary

  1. Add support for STRICT_FSETCC promotion (details)
  2. [test] Merge parallel_region_merging{,_legacy_pm}.ll (details)
  3. Clear NewGEPBases after finish using them in CodeGenPrep pass (details)
  4. [NFC][tests] Replace non-portable grep with FileCheck (details)
  5. [libc++] NFC: Fix confusing indentation in <numeric> (details)
  6. [mlir] Add Tosa dialect const folder for tosa.const. (details)
  7. [PowerPC][PCRelative] Add new pseudo instructions for PCRel TLS to fix R2 clobber issue (details)
  8. [ThinLTO/WPD] Enable -wholeprogramdevirt-skip in ThinLTO backends (details)
  9. Fix CalibratedQuantizedType's print function to match parser (details)
  10. [AMDGPU] Add a TRANS bit to TSFlags. NFC. (details)
  11. [Driver] Default Generic_GCC aarch64 to -fasynchronous-unwind-tables (details)
  12. [mlir][Python] Fix the last remaining instance of PYTHON_EXECUTABLE. (details)
  13. [clangd] AddUsing: Used spelled text instead of type name. (details)
  14. [HardwareLoops] Change order of SCEV expression construction for InitLoopCount. (details)
  15. [test] Fix rtf_type_checking.ll under NPM (details)
  16. [DSE] Precommit test case for PR48279. (details)
  17. [test] Pin parallel_deletion_cg_update.ll to legacy PM (details)
  18. [LoopVec] Add a minor clarifying comment (details)
  19. [InstCombine] add tests for gep math; NFC (details)
  20. [InstCombine] add tests for sub of muls; NFC (details)
  21. [InstCombine] try difference-of-shifts factorization before negator (details)
  22. [clangd] Add more trace spans for rename, NFC. (details)
  23. [mlir][Python] Sync Python bindings with C API MlirStringRef modification. (details)
  24. [mlir] NFC - Refactor and expose a parsing helper for OffsetSizeAndStrideInterface (details)
  25. [test] Clean up ppc-features.cpp and improve tests (details)
  26. [mlir] NFC - Refactor and expose a helper printOffsetSizesAndStrides helper function. (details)
  27. Avoid redundant work when computing vtable vcall visibility (details)
  28. [libc++] [P0482] [C++20] Implement missing bits for atomic (details)
  29. [mlir] Add conversion from SCF parallel loops to OpenMP (details)
  30. [PowerPC] Don't reuse an illegal typed load for int_to_fp conversion. (details)
  31. [mlir][sparse] generalize invariant expression handling in sparse compiler (details)
  32. [mlir] Remove SameOperandsAndResultShape when redundant with ElementwiseMappable (details)
  33. [RISCV] Add GHC calling convention (details)
  34. [clangd] Addusing tweak: find insertion point after definition (details)
  35. [OpenMP50][DOCS] Mark target data non-contiguous as done, NFC. (details)
  36. [SelectionDAG] Avoid aliasing analysis if the object size is unknown. (details)
  37. [gn build] Port 8d06a678a5c (details)
  38. Revert "[RISCV] Add GHC calling convention" (details)
  39. [RISCV] Add GHC calling convention (details)
Commit 9c8af93c93d0eec980cd58c194ad964e14d245ac by thomasp
Add support for STRICT_FSETCC promotion

Add missing handling of STRICT_FSETCC promotion. This prevents assert
failure in llvm::TargetLoweringBase::getTypeToPromoteTo().

Reviewed By: uweigand

Differential Revision: https://reviews.llvm.org/D91962
The file was modifiedllvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Commit 25777080549bb62b6e46a1809f93257969f5dd53 by aeubanks
[test] Merge parallel_region_merging{,_legacy_pm}.ll

These are identical except for the RUN lines.
Also pin legacy RUN line to legacy PM.
The file was removedllvm/test/Transforms/OpenMP/parallel_region_merging_legacy_pm.ll
The file was modifiedllvm/test/Transforms/OpenMP/parallel_region_merging.ll
Commit a248eca6659779116a6fb348117d74a0b8a05316 by yyc1992
Clear NewGEPBases after finish using them in CodeGenPrep pass

AFAICT all other set/map are correctly cleared in `runOnFunction`.

With assertion enabled this causes a crash when the module is freed and potentially if a later pass delete the instruction (not observed in real world though). Without assertion this can potentially cause confusing result when running on a new Function/Module.

Reviewed By: loladiro

Differential Revision: https://reviews.llvm.org/D84031
The file was modifiedllvm/lib/CodeGen/CodeGenPrepare.cpp
Commit 44174b3d518ed70482ff5df2879523a4e26f92cc by hubert.reinterpretcast
[NFC][tests] Replace non-portable grep with FileCheck

After commit 2482648a795afbe12774168bbbf70dc14c031267, a GNU grep option
is just passed unconditionally to `grep` in general. This patch fixes
the test for platforms where `grep` is not GNU grep.
The file was modifiedclang/test/CodeGen/thinlto_embed_bitcode.ll
Commit 0ec73a61cca6cddf3255338c24fb5398fe45b74d by Louis Dionne
[libc++] NFC: Fix confusing indentation in <numeric>
The file was modifiedlibcxx/include/numeric
Commit db9713cd776ac5963efc502a5db6b315335aad9a by stellaraccident
[mlir] Add Tosa dialect const folder for tosa.const.

* Was missed in the initial submission and is required for a ConstantLike op.
* Also adds a materializeConstant hook to preserve it.
* Tightens up the argument constraint on tosa.const to match what is actually legal.

Differential Revision: https://reviews.llvm.org/D92040
The file was modifiedmlir/lib/Dialect/Tosa/IR/TosaOps.cpp
The file was modifiedmlir/include/mlir/Dialect/Tosa/IR/TosaOps.td
The file was modifiedmlir/include/mlir/Dialect/Tosa/IR/TosaOpBase.td
The file was addedmlir/test/Dialect/Tosa/constant_folding.mlir
Commit 1f5c4a0d04ac0384218bf56e78e3c1d9c3c2f53f by wei.huang
[PowerPC][PCRelative] Add new pseudo instructions for PCRel TLS to fix R2 clobber issue

New pseudo instructions GETtlsADDRPCREL and GETtlsldADDRPCREL are added for properly
setting REGMASK for tls_get_addr function when using PCRelative address.

Differential Revisien: https://reviews.llvm.org/D91420
Reviewed by: bsaleil
The file was modifiedllvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
The file was modifiedllvm/lib/Target/PowerPC/PPCTLSDynamicCall.cpp
The file was modifiedllvm/lib/Target/PowerPC/PPCInstr64Bit.td
The file was addedllvm/test/CodeGen/PowerPC/pcrel-tls_get_addr_clobbers.ll
Commit 6e4c1cf2938842ceefc2712f0007843369dd16ca by tejohnson
[ThinLTO/WPD] Enable -wholeprogramdevirt-skip in ThinLTO backends

Previously this option could be used to skip devirtualizations of the
given functions in regular LTO and in the ThinLTO indexing step. This
change allows them to be skipped in the backend as well, which is useful
when debugging WPD in a distributed ThinLTO backend.

Differential Revision: https://reviews.llvm.org/D91812
The file was modifiedllvm/lib/Transforms/IPO/WholeProgramDevirt.cpp
The file was modifiedclang/test/CodeGen/thinlto-distributed-cfi-devirt.ll
Commit 760063267c462c21cfdeafb0d5fe63ecfa2f2c30 by liufeng.ee
Fix CalibratedQuantizedType's print function to match parser

Reviewed By: liufengdb

Differential Revision: https://reviews.llvm.org/D92034
The file was modifiedmlir/test/Dialect/Quant/parse-calibrated.mlir
The file was modifiedmlir/lib/Dialect/Quant/IR/TypeParser.cpp
Commit 4926eed59c77bb452539d88a0a8ba3f3c21c4016 by jay.foad
[AMDGPU] Add a TRANS bit to TSFlags. NFC.

This is used to mark transcendental instructions that execute on a
separate pipeline from the normal VALU pipeline.

Differential Revision: https://reviews.llvm.org/D92042
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrFormats.td
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.h
The file was modifiedllvm/lib/Target/AMDGPU/VOPInstructions.td
The file was modifiedllvm/lib/Target/AMDGPU/SIDefines.h
The file was modifiedllvm/lib/Target/AMDGPU/VOP1Instructions.td
Commit f96fef89b5eca29f2dc41e97829c20bf742cdcd9 by i
[Driver] Default Generic_GCC aarch64 to -fasynchronous-unwind-tables

In GCC, `aarch64-*-linux` and `aarch64-*-freebsd` made the switch in 2018
(https://gcc.gnu.org/pipermail/gcc-patches/2018-March/495549.html).
In Clang, FreeBSD/Fuchsia/NetBSD/MinGW aarch64 default to -fasynchronous-unwind-tables.

This patch defaults Generic_GCC aarch64 (which affects Linux) to use -fasynchronous-unwind-tables.

Reviewed By: nickdesaulniers

Differential Revision: https://reviews.llvm.org/D91760
The file was modifiedclang/lib/Driver/ToolChains/Gnu.cpp
The file was modifiedclang/test/Driver/aarch64-features.c
Commit 15481bba1ff2c03ff969cba8e0e7c37888f966a3 by stellaraccident
[mlir][Python] Fix the last remaining instance of PYTHON_EXECUTABLE.

* Was causing auto-detect of pybind11 to fail on clean configure.

Differential Revision: https://reviews.llvm.org/D92043
The file was modifiedmlir/cmake/modules/MLIRDetectPythonEnv.cmake
The file was modifiedmlir/CMakeLists.txt
Commit f6e59294b63e1fd0b25720f24111cd17865004be by adamcz
[clangd] AddUsing: Used spelled text instead of type name.

This improves the behavior related to type aliases, as well as cases of
typo correction.

Differential Revision: https://reviews.llvm.org/D91966
The file was modifiedclang-tools-extra/clangd/refactor/tweaks/AddUsing.cpp
The file was modifiedclang-tools-extra/clangd/unittests/TweakTests.cpp
Commit 42eaf4fe0adef3344adfd9fbccd49f325cb549ef by thomasp
[HardwareLoops] Change order of SCEV expression construction for InitLoopCount.

Putting the +1 before the zero-extend will allow scalar evolution to fold the expression in some cases such as the one shown in PowerPC's `shrink-wrap.ll` test.

Reviewed By: samparker

Differential Revision: https://reviews.llvm.org/D91724
The file was modifiedllvm/include/llvm/Analysis/TargetTransformInfo.h
The file was modifiedllvm/lib/Analysis/TargetTransformInfo.cpp
The file was modifiedllvm/lib/CodeGen/HardwareLoops.cpp
The file was modifiedllvm/test/CodeGen/PowerPC/shrink-wrap.ll
Commit e3bb78293a13b0c85ee774615d1cf490e6f175d9 by aeubanks
[test] Fix rtf_type_checking.ll under NPM
The file was modifiedllvm/test/Transforms/OpenMP/rtf_type_checking.ll
Commit 785a2552550a3e2ddc83bbad95f987ad350477b6 by flo
[DSE] Precommit test case for PR48279.
The file was addedllvm/test/Transforms/DeadStoreElimination/MSSA/out-of-bounds-stores.ll
Commit 116660257f789150e6c2f896ccc8cd605e153cd9 by aeubanks
[test] Pin parallel_deletion_cg_update.ll to legacy PM

This tests legacy PM-specific code.
The file was modifiedllvm/test/Transforms/OpenMP/parallel_deletion_cg_update.ll
Commit 075468621c0f4569f4c91d4f3097b3a60812cfcc by listmail
[LoopVec] Add a minor clarifying comment
The file was modifiedllvm/lib/Transforms/Vectorize/LoopVectorize.cpp
Commit a991d5334045d1e7f3c7e292245aecbce66184b0 by spatel
[InstCombine] add tests for gep math; NFC
The file was modifiedllvm/test/Transforms/InstCombine/sub-gep.ll
Commit ccf6f15bc62b7c17c82a8cc2010eeaae470a1563 by spatel
[InstCombine] add tests for sub of muls; NFC
The file was modifiedllvm/test/Transforms/InstCombine/sub.ll
Commit 678b9c5dde0d119e91f5f905c3d9101cf8c514f9 by spatel
[InstCombine] try difference-of-shifts factorization before negator

We need to preserve wrapping flags to allow better folds.
The cases with geps may be non-intuitive, but that appears to agree with Alive2:
https://alive2.llvm.org/ce/z/JQcqw7
We create 'nsw' ops independent from the original wrapping on the sub.
The file was modifiedllvm/test/Transforms/InstCombine/sub-gep.ll
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
The file was modifiedllvm/test/Transforms/InstCombine/sub.ll
Commit 1e821217cb3619449d536978bae7c9f05bdf0fa5 by hokein.wu
[clangd] Add more trace spans for rename, NFC.
The file was modifiedclang-tools-extra/clangd/refactor/Rename.cpp
Commit 5f0c1e380661f5a28fb8e87d70a68fa31e923436 by stellaraccident
[mlir][Python] Sync Python bindings with C API MlirStringRef modification.

MLIR C API use the `MlirStringRef` instead of `const char *` for the string type now. This patch sync the Python bindings with the C API modification.

Differential Revision: https://reviews.llvm.org/D92007
The file was modifiedmlir/lib/Bindings/Python/PybindUtils.h
The file was modifiedmlir/lib/Bindings/Python/IRModules.cpp
Commit b6c71c13a38b76942c9561575837c94215f23c9e by nicolas.vasilache
[mlir] NFC - Refactor and expose a parsing helper for OffsetSizeAndStrideInterface

Parse trailing part of an op of the form:
```
  <optional-offset-prefix>`[` offset-list `]`
  <optional-size-prefix>`[` size-list `]`
  <optional-stride-prefix>[` stride-list `]`
```
Each entry in the offset, size and stride list either resolves to an integer
constant or an operand of index type.
Constants are added to the `result` as named integer array attributes with
name `OffsetSizeAndStrideOpInterface::getStaticOffsetsAttrName()` (resp.
`getStaticSizesAttrName()`, `getStaticStridesAttrName()`).

Append the number of offset, size and stride operands to `segmentSizes`
before adding it to `result` as the named attribute:
`OpTrait::AttrSizedOperandSegments<void>::getOperandSegmentSizeAttr()`.
Offset, size and stride operands resolution occurs after `preResolutionFn`
to give a chance to leading operands to resolve first, after parsing the
types.
```
ParseResult parseOffsetsSizesAndStrides(
    OpAsmParser &parser, OperationState &result, ArrayRef<int> segmentSizes,
    llvm::function_ref<ParseResult(OpAsmParser &, OperationState &)>
        preResolutionFn = nullptr,
    llvm::function_ref<ParseResult(OpAsmParser &)> parseOptionalOffsetPrefix =
        nullptr,
    llvm::function_ref<ParseResult(OpAsmParser &)> parseOptionalSizePrefix =
        nullptr,
    llvm::function_ref<ParseResult(OpAsmParser &)> parseOptionalStridePrefix =
        nullptr);
```

Differential revision: https://reviews.llvm.org/D92030
The file was modifiedmlir/include/mlir/Interfaces/ViewLikeInterface.h
The file was modifiedmlir/lib/Interfaces/ViewLikeInterface.cpp
The file was modifiedmlir/lib/Dialect/StandardOps/IR/Ops.cpp
Commit 8f8bbf98dae1c513b70614a9640b861e6e240b5f by i
[test] Clean up ppc-features.cpp and improve tests

And add ppc-cpus.cpp for -mcpu= specific tests.
The file was modifiedclang/test/Driver/ppc-features.cpp
The file was addedclang/test/Driver/ppc-cpus.c
Commit c24708102501115efae27f82c24d5991059a5770 by nicolas.vasilache
[mlir] NFC - Refactor and expose a helper printOffsetSizesAndStrides helper function.

Print part of an op of the form:
```
  <optional-offset-prefix>`[` offset-list `]`
  <optional-size-prefix>`[` size-list `]`
  <optional-stride-prefix>[` stride-list `]`
```

Also address some leftover nits.

Differential revision: https://reviews.llvm.org/D92031
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/Fusion.cpp
The file was modifiedmlir/include/mlir/Dialect/StandardOps/IR/Ops.td
The file was modifiedmlir/include/mlir/Interfaces/ViewLikeInterface.h
The file was modifiedmlir/include/mlir/Interfaces/ViewLikeInterface.td
The file was modifiedmlir/lib/Interfaces/ViewLikeInterface.cpp
The file was modifiedmlir/lib/Dialect/StandardOps/IR/Ops.cpp
Commit 0768b0576a938b6a4832884384fcb02cd2f74e09 by tejohnson
Avoid redundant work when computing vtable vcall visibility

Add a Visited set to avoid repeatedly processing the same base classes
in complex class hierarchies. This cut down the compile time of one
source file from >12min to ~1min.

Differential Revision: https://reviews.llvm.org/D91676
The file was modifiedclang/lib/CodeGen/CodeGenModule.h
The file was modifiedclang/lib/CodeGen/CGVTables.cpp
The file was modifiedclang/lib/CodeGen/MicrosoftCXXABI.cpp
Commit 9c97e4ef4529ee2b518af6c1f2f68d2634946b3a by marek.kurdej
[libc++] [P0482] [C++20] Implement missing bits for atomic

Added: ATOMIC_CHAR8_T_LOCK_FREE, atomic<char8_t>, atomic_char8_t.
http://wg21.link/P0482

Reviewed By: ldionne, #libc

Differential Revision: https://reviews.llvm.org/D91706
The file was modifiedlibcxx/test/std/atomics/atomics.lockfree/isalwayslockfree.pass.cpp
The file was modifiedlibcxx/test/std/atomics/atomics.lockfree/lockfree.pass.cpp
The file was modifiedlibcxx/test/std/atomics/types.pass.cpp
The file was modifiedlibcxx/test/std/atomics/atomics.types.generic/integral.pass.cpp
The file was modifiedlibcxx/test/std/atomics/atomics.types.operations/atomics.types.operations.req/atomic_helpers.h
The file was modifiedlibcxx/test/std/atomics/atomics.types.generic/integral_typedefs.pass.cpp
The file was modifiedlibcxx/include/atomic
Commit 119545f4338efacabf99e06eeca965913f6617f2 by zinenko
[mlir] Add conversion from SCF parallel loops to OpenMP

Introduce a conversion pass from SCF parallel loops to OpenMP dialect
constructs - parallel region and workshare loop. Loops with reductions are not
supported because the OpenMP dialect cannot model them yet.

The conversion currently targets only one level of parallelism, i.e. only
one top-level `omp.parallel` operation is produced even if there are nested
`scf.parallel` operations that could be mapped to `omp.wsloop`. Nested
parallelism support is left for future work.

Reviewed By: kiranchandramohan

Differential Revision: https://reviews.llvm.org/D91982
The file was modifiedmlir/include/mlir/Conversion/Passes.td
The file was modifiedmlir/lib/Conversion/PassDetail.h
The file was modifiedmlir/include/mlir/Conversion/Passes.h
The file was modifiedmlir/include/mlir/Dialect/OpenMP/OpenMPOps.td
The file was addedmlir/lib/Conversion/SCFToOpenMP/SCFToOpenMP.cpp
The file was addedmlir/test/Conversion/SCFToOpenMP/scf-to-openmp.mlir
The file was modifiedmlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp
The file was modifiedmlir/lib/Conversion/CMakeLists.txt
The file was addedmlir/include/mlir/Conversion/SCFToOpenMP/SCFToOpenMP.h
The file was addedmlir/lib/Conversion/SCFToOpenMP/CMakeLists.txt
Commit 4f5355ee73626f8b8fe6bf0dd6d167fea7628a2c by sd.fertile
[PowerPC] Don't reuse an illegal typed load for int_to_fp conversion.

When the operand to an (s/u)int_to_fp node is an illegally typed load we
cannot reuse the load address since we can not build a proper dependancy
chain. The legalized loads will use a different chain output then the
illegal load. If we reuse the load address then we will build a
conversion node that uses the chain of the illegal load and operations
which modify the memory address in the other dependancy chain can be
scheduled before the floating point load which feeds the conversion.

Differential Revision: https://reviews.llvm.org/D91265
The file was modifiedllvm/lib/Target/PowerPC/PPCISelLowering.cpp
The file was addedllvm/test/CodeGen/PowerPC/cvt_i64_to_fp.ll
Commit b228e2bd92a7959b6a48ac208871ad0cb5c09ebf by ajcbik
[mlir][sparse] generalize invariant expression handling in sparse compiler

Generalizes invariant handling to anything defined outside the Linalg op
(parameters and SSA computations). Fixes bug that was using parameter number
as tensor number.

Reviewed By: penpornk

Differential Revision: https://reviews.llvm.org/D91985
The file was modifiedmlir/lib/Dialect/Linalg/Transforms/Sparsification.cpp
The file was modifiedmlir/test/Dialect/Linalg/sparse_2d.mlir
Commit dfbb5a087e20ea1c14300eef600e52360320b390 by silvasean
[mlir] Remove SameOperandsAndResultShape when redundant with ElementwiseMappable

SameOperandsAndResultShape and ElementwiseMappable have similar
verification, but in general neither is strictly redundant with the
other.

Examples:
- SameOperandsAndResultShape allows
  `"foo"(%0) : tensor<2xf32> -> tensor<?xf32> but ElementwiseMappable
  does not.
- ElementwiseMappable allows
  `select %scalar_pred, %true_tensor, %false_tensor` but
  SameOperandsAndResultShape does not.

SameOperandsAndResultShape is redundant with ElementwiseMappable when
we can prove that the mixed scalar/non-scalar case cannot happen. In
those situations, `ElementwiseMappable & SameOperandsAndResultShape ==
ElementwiseMappable`:
- Ops with 1 operand: the case of mixed scalar and non-scalar operands
  cannot happen since there is only one operand.
- When SameTypeOperands is also present, the mixed scalar/non-scalar
  operand case cannot happen.

Differential Revision: https://reviews.llvm.org/D91396
The file was modifiedmlir/include/mlir/Dialect/StandardOps/IR/Ops.td
The file was modifiedmlir/test/IR/invalid-ops.mlir
Commit f8317bb256be2cd8ed81ebc567f0fa626b645f63 by luismarques
[RISCV] Add GHC calling convention

This is a special calling convention to be used by the GHC compiler.

Differential Revision: https://reviews.llvm.org/D89788
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.cpp
The file was addedllvm/test/CodeGen/RISCV/ghccc-rv32.ll
The file was addedllvm/test/CodeGen/RISCV/ghccc-rv64.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVFrameLowering.cpp
The file was modifiedllvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
Commit a200501bca4dc7f3292d824f249fa21a479e9873 by adamcz
[clangd] Addusing tweak: find insertion point after definition

When type/function is defined in the middle of the file, previuosly we
would sometimes insert a "using" line before that definition, leading to
a compilation error. With this fix, we pick a point after such
definition in translation unit.

This is not a perfect solution. For example, it still doesn't handle
"using namespace" directives. It is, however, a significant improvement.

Differential Revision: https://reviews.llvm.org/D92053
The file was modifiedclang-tools-extra/clangd/refactor/tweaks/AddUsing.cpp
The file was modifiedclang-tools-extra/clangd/unittests/TweakTests.cpp
Commit 77e98eaee2e8d4b9b297b66fda5b1e51e2a69999 by cchen
[OpenMP50][DOCS] Mark target data non-contiguous as done, NFC.
The file was modifiedclang/docs/OpenMPSupport.rst
Commit 8d06a678a5c24e98034f6d48a19e734b2c87d22e by kai.wang
[SelectionDAG] Avoid aliasing analysis if the object size is unknown.

If the size of memory access is unknown, do not use it to analysis. One
example of unknown size memory access is to load/store scalable vector
objects on the stack.

Differential Revision: https://reviews.llvm.org/D91833
The file was addedllvm/unittests/CodeGen/SelectionDAGAddressAnalysisTest.cpp
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAGAddressAnalysis.cpp
The file was modifiedllvm/unittests/CodeGen/CMakeLists.txt
Commit 73c181cf3ab3dd8cfe48a97d71dffceec8e00af7 by llvmgnsyncbot
[gn build] Port 8d06a678a5c
The file was modifiedllvm/utils/gn/secondary/llvm/unittests/CodeGen/BUILD.gn
Commit e4d9380245518ee8dcb765eb2e5f4f2788b53cc6 by luismarques
Revert "[RISCV] Add GHC calling convention"

This reverts commit f8317bb256be2cd8ed81ebc567f0fa626b645f63 due to lack of
proper attribution.
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.cpp
The file was removedllvm/test/CodeGen/RISCV/ghccc-rv64.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
The file was modifiedllvm/lib/Target/RISCV/RISCVFrameLowering.cpp
The file was removedllvm/test/CodeGen/RISCV/ghccc-rv32.ll
Commit a8dc2110cd4dd69212a204bc1074729f95d5402a by luismarques
[RISCV] Add GHC calling convention

This is a special calling convention to be used by the GHC compiler.

Patch by Andreas Schwab (schwab)

Differential Revision: https://reviews.llvm.org/D89788
The file was addedllvm/test/CodeGen/RISCV/ghccc-rv32.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
The file was addedllvm/test/CodeGen/RISCV/ghccc-rv64.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.cpp
The file was modifiedllvm/lib/Target/RISCV/RISCVFrameLowering.cpp