FailedChanges

Summary

  1. Add missing closing quote to SVE 2 stage cmake options (details)
  2. [Zorg] Use ccache instead incremental build for openmp-offload-cuda-runtime. (details)
Commit 0b9e49366d6c3c39fabf7a20123cb37eac6297ca by david.spickett
Add missing closing quote to SVE 2 stage cmake options

Missing from 24c07902d058abcee3bcf908676bacaae1f3d448.
The file was modifiedbuildbot/osuosl/master/config/builders.py (diff)
Commit 2afbc972a9ca914efa903d3ffc987b5da80ec836 by llvm-project
[Zorg] Use ccache instead incremental build for openmp-offload-cuda-runtime.

Building with `LLVM_ENABLE_RUNTIMES=openmp` has the disadvantage that if clang changes, the runtime that was built with the previous clang is not rebuilt. That is, if the runtime is miscompiling due to a change in clang, this will only be detected in the next clean build.

For instance, commit rG1100e4aafea233bc8bbc307c5758a7d287ad3bae caused the libomptarget device runtime to miscompile, but the [[ https://lab.llvm.org/staging/#/builders/154/builds/1421 | openmp-offload-cuda-runtime builder ]] shows it as green. Tests only started failing with the [[ https://lab.llvm.org/staging/#/builders/154/builds/1427 | next clean build ]]. In production, this would have blamed the wrong commit.

In contrast, the openmp-offload-cuda-project builder started failing with the [[ https://lab.llvm.org/staging/#/builders/155/builds/1803 | expected commit ]].

Instead of building incrementally, use ccache to avoid this problem.

Reviewed By: gkistanova, tianshilei1992

Differential Revision: https://reviews.llvm.org/D106781
The file was modifiedbuildbot/osuosl/master/config/builders.py (diff)

Summary

  1. [ORC][ORC-RT] Add initial Objective-C and Swift support to MachOPlatform. (details)
  2. [libc] fix LibcUnitTestMain when building with shared libraries (details)
  3. [mlir] Fix RankedTensorType::walkImmediateSubElements method (details)
  4. [libomptarget][nfc] Squash unused variable warning (details)
  5. [libomptarget] Build amdgpu plugin without hsa (details)
  6. Revert "Revert D106562 "[clangd] Get rid of arg adjusters in CommandMangler"" (details)
  7. [SelectionDAG] Support scalable-vector splats in yet more cases (details)
  8. [Analysis] Add simple cost model for strict (in-order) reductions (details)
  9. [AArch64][AsmParser] NFC: Parser.getTok().getLoc() -> getLoc() (details)
  10. Revert "[clangd] Avoid range-loop init-list lifetime subtleties." (details)
  11. [X86][SSE] Don't scrub address math from interleaved shuffle tests (details)
  12. [X86][AVX] Prefer vinsertf128 to vperm2f128 on AVX1 targets (details)
  13. [AArch64][SVE] Improve code generation for vector_splice for Imm == -1 (details)
  14. Fix test failures caused by 0aff1798b5721d5f95d16f465b99d357012bb8d1 (details)
  15. [SVE][AArch64] Improve code generation for vector_splice for Imm > 0 (details)
  16. [SVE] Add support for folding for select + masked loads (details)
  17. [VPlan] Use stored value from recipes for interleave groups. (details)
  18. [Inliner] Make the CallPenalty configurable (details)
  19. [NFC] Change VFShape so it contains an ElementCount rather than seperate VF and IsScalable properties. (details)
  20. [SLP]Fix costs calculations. (details)
  21. [mlir] split type conversion to two lines for GCC's sake (details)
  22. [AArch65][SVE] Remove vector_splice from AddedComplexity pattern (details)
  23. Revert "[SLP]Fix costs calculations." (details)
  24. [SVE] Fix casts to <FixedVectorType> in truncateToMinimalBitwidths (details)
  25. [SimplifyCFG] Improve store speculation check (details)
  26. AArch64: support i128 (& larger) returns in GlobalISel (details)
  27. [ARM] Ensure correct regclass in distributing postinc (details)
  28. [AMDGPU] Fix MMO for raw/struct buffer access with non-constant offset (details)
  29. [AMDGPU] Pre-commit global-isel test case for D106451 (details)
  30. [AMDGPU][GISel] Fix MMO for raw/struct buffer access with non-constant offset (details)
  31. [llvm-readobj] Display multiple function names for stack size entries (details)
  32. [OpenCL] Change default standard version to CL1.2 (details)
  33. [SLP]Fix costs calculations. (details)
  34. [LV] Add test to store a first-order rec via interleave group. (details)
  35. [InstrRef][AArch64][1/4] Accept constant physreg variable locations (details)
  36. [Analyzer][solver][NFC] print constraints deterministically (ordered by their string representation) (details)
  37. Simplify away some SmallVector copies. NFCI. (details)
  38. [IR] Consider non-willreturn as side effect (PR50511) (details)
  39. [libc++][ci] Detect not committed generated files. (details)
  40. Recommit "[VPlan] Add recipe for first-order rec phis, make splicing explicit." (details)
  41. [SystemZ] Add support for new cpu architecture - arch14 (details)
  42. [Clang][OpenMP] Remove the mandatory flush for capture for OpenMP 5.1 (details)
  43. [AArch64][SVE] Break false dependencies for inactive lanes of unary operations (details)
  44. [LV] Don't assume isScalarAfterVectorization if one of the uses needs widening. (details)
  45. [MergeICmps] Separate out BCECmp and use Optional (NFC) (details)
  46. [SimplifyLibCalls] reduce code duplication; NFC (details)
  47. [SimplifyLibCalls] avoid crash on pointer math (details)
  48. [libc++][NFC] Change a few instances of > > to >> in C++20 code (details)
  49. [SVE] Use reg+reg addressing mode for immediate offsets. (details)
  50. [AsmParser] Remove MDRef (NFC) (details)
  51. [MergeICmps] Try to fix MSVC build failure (details)
  52. [yaml2obj][MachO] Rename PayloadString to Content (details)
  53. [llvm-objcopy] Drop GRP_COMDAT if the group signature is localized (details)
  54. [MergeICmps] Collect block instructions once (NFC) (details)
  55. [clang][pp] adds '#pragma include_instead' (details)
  56. [LV] Remove assert that VF cannot be scalable in setCostBasedWideningDecision. (details)
  57. [Analysis] Fix getOrderedReductionCost to call target's getArithmeticInstrCost implementation (details)
  58. [libc++] Add range_size_t (details)
  59. [PowerPC] Change altivec indexed load/store builtins argument type (details)
  60. [DebugInfo] Correctly update debug users of SSA values in tail duplication (details)
  61. [LAA] Remove RuntimeCheckingPtrGroup::RtCheck member (NFC). (details)
  62. [X86][AVX] Add PR50053 test case (details)
  63. [test] Fix PayloadString: in lldb tests (details)
  64. [mlir][tosa] Disable tosa shape verification between operands/results (details)
  65. [WebAssembly] Improve pseudocode in LowerEmscriptenEHSjLj (details)
  66. [libc] add scudo wrappers to llvm libc (details)
  67. [GlobalISel] Add combine for merge(unmerge) and use AArch64 postlegal-combiner. (details)
  68. [AArch64][GlobalISel] Enable some select combines after legalization. (details)
  69. [LLVM IR] Allow volatile stores to trap. (details)
  70. [AArch4][GlobalISel] Post-legalize combine s64 = G_MERGE s32, 0 -> G_ZEXT. (details)
  71. [LLDB][GUI] Resolve paths in file/directory fields (details)
  72. [FPEnv][InstSimplify] Enable more folds for constrained fadd (details)
  73. [lld][WebAssembly] Do not remove name section with --strip-debug (details)
  74. [PowerPC] Implement partial vector ld/st builtins for XL compatibility (details)
  75. [compiler-rt][CMake][arm64] Use a custom target for symlinking LSE sources (details)
  76. [TypePromotion] Remove redundant if. NFC (details)
  77. [amdgpu] Add 64-bit PC support when expanding unconditional branches. (details)
  78. Fix clang regression test after 5c486ce0 (details)
  79. [libc++] Set the target triple by default in the standalone build (details)
  80. [libc++] Implement the output_iterator and output_range concepts (details)
  81. [OpenMP][NFC] Remove unncessary capture in RAII struct (details)
  82. [PowerPC] Add implicit-def RM to instructions mtfsb[01] (details)
  83. Fix clang debug info irgen of i128 enums (details)
  84. [SimplifyCFG] Remove stale comment after d7378259aa, NFC (details)
  85. [lldb][NFC] Delete unused and commented out DWARF constants (details)
  86. [AArch64] NFC: Make some AArch64-SVE LoopVectorize tests generic. (details)
  87. [LV] Don't let ForceTargetInstructionCost override Invalid cost. (details)
  88. [PowerPC]Add addex instruction definition and MC tests (details)
  89. [ARM] Fixup vst4 test. NFC (details)
  90. [OpenMP][NFC] Fix a few typos in OpenMP documentation (details)
  91. [CodeView] Saturate values bigger than supported by APInt. (details)
  92. [clang] P2266 implicit moves STL workaround (details)
  93. [SimplifyCFG] Drop support for duplicating ret's into uncond predecessors (details)
  94. [SimplifyCFG] Drop support for simplifying cond branch to two (different) ret's (details)
  95. [SimplifyCFG] SwitchToLookupTable(): don't increase ret count (details)
  96. [flang][msvc] Fix external-io unittest. (details)
  97. [OpenMP] Add a driver flag to enable the new device runtime library (details)
  98. [libc++abi/unwind] NFC: Normalize how we set target properties (details)
  99. [libc++] Remove "pass by const value" in <random>. NFCI. (details)
  100. [libc++] Fix signed overflow inside ranges::advance. (details)
  101. [WebAssembly] Make Emscripten EH work with Emscripten SjLj (details)
  102. [LLDB][GUI] Expand selected thread tree item by default (details)
  103. [LLDB][GUI] Add Arch Field (details)
  104. [OpenMP] Always inline the OpenMP outlined function (details)
  105. [WebAssembly] Remove dominator dependency in WasmEHPrepare (NFC) (details)
  106. [GlobalISel] Add a constant folding combine. (details)
  107. [flang] Disallow BOZ literal constants as arguments of implicit interfaces (details)
  108. [llvm-objcopy] Fix section group flag read/write when operating on a cross-endian object file (details)
  109. [AArch64][GlobalISel] Add identity combines to post-legal combiner. (details)
  110. [libc++] Fix spacing in <vector>. NFCI. (details)
  111. [MLIR][SCF][NFC] Fix typo in documentation of scf.while (details)
  112. [compiler-rt][hwasan][fuchsia] Define shadow bound globals (details)
  113. [lldb] [gdb-remote client] Avoid zero padding PID/TID in H packet (details)
  114. Disable the new enum i128 test under ASan, it uncovers an existing leak (details)
  115. [compiler-rt][hwasan][fuchsia] Implement InitializeOsSupport (details)
  116. Build libSupport with -Werror=global-constructors (NFC) (details)
  117. [DebugInfo] Use per-enumerator signedness for DIEnumerator (details)
  118. [PowerPC] Add pwr7 and pwr10 support to IBM MASSV pass on AIX (details)
  119. [compiler-rt][hwasan][fuchsia] Implement TagMemoryAligned for fuchsia (details)
  120. [AArch64][GlobalISel] Legalize ctpop s128 (details)
  121. libclang.so: Make SONAME independent from LLVM version (details)
  122. [SCEV] Add a comment about invariant in howManyLessThans (details)
  123. [PowerPC] Changed sema checking range for tdw td builtin (details)
  124. libclang.so: Fix version script to work with gold (details)
  125. [GlobalISel] Add scalar widening for G_MERGE_VALUES destination (details)
  126. libclang: Add missing export to python script that generates export list (details)
  127. Revert "[AArch64][GlobalISel] Legalize ctpop s128" (details)
  128. [mlir] Make ValueShapeRange a new class (details)
  129. [MLIR][NFC] Rework some comments. (details)
  130. [dfsan][NFC] Add compile flags and environment variables to doc (details)
  131. [DebugInfo] Switch to using constructor homing (-debug-info-kind=constructor) by default when debug info is enabled (details)
  132. [dfsan] Fix doc build errors (details)
  133. [PowerPC] Fix materialization of SP float values on Power10 (details)
  134. [trace] Add the definition of a TraceExporter plugin (details)
  135. Revert "Build libSupport with -Werror=global-constructors (NFC)" (details)
  136. [libcxx][NFC] adjusts 41b17c44 so it meets requested feedback (details)
  137. [AMDGPU] Add SelectionDAG support for insert_subvector on v4f64 (details)
  138. libclang: Fixes for the python script that generates the export list (details)
  139. [dfsan][NFC] Fix doc format (details)
  140. [gn build] Kind of port c7b3a91017d2 (libclang version script) (details)
  141. Define the namespace for the Affine dialect in ODS (NFC) (details)
  142. [Attributor][FIX] Track change status for AAIsDead properly (details)
  143. [Attributor][FIX] Do not return CHANGED unconditionally (details)
  144. [OpenMP] Run rewriteDeviceCodeStateMachine in the Module not CGSCC pass (details)
  145. [AbstractAttributor] Fold __kmpc_parallel_level if possible (details)
  146. Revert "[GlobalISel] Add scalar widening for G_MERGE_VALUES destination" (details)
  147. [llvm-jitlink] Don't hardcode LLVM version number into the runtime path. (details)
  148. [NFC][InstCombine] Fix typo (details)
  149. [AArch64] Fix -Wparentheses warning with gcc 5.4. NFC (details)
  150. [dfsan][NFC] Fix doc format (details)
  151. Build libSupport with -Werror=global-constructors (NFC) (details)
  152. [Attributor] Introduce getPotentialCopiesOfStoredValue and use it (details)
  153. [Attributor] Delete dead stores (details)
  154. [Local] Do not introduce a new `llvm.trap` before `unreachable` (details)
  155. [CSSPGO] Tweak ICP threshold in top-down inliner (details)
  156. Merge all the llvm-exegesis unit tests into a single binary (details)
  157. [Coroutine] Record the elided coroutines (details)
  158. [Attributor][FIX] Update AMDGPU attributor test (details)
  159. [Attributor] Update check lines for all AMDGPU attributor tests (details)
  160. [OpenMP] Prototype opt-in new GPU device RTL (details)
  161. [InstSimplify] Expose generic interface for replaced operand simplification (details)
  162. [Attributor] Utilize the InstSimplify interface to simplify instructions (details)
  163. [Attributor][FIX] Copy all members in the assignment operator (details)
  164. [OpenMP] Try to simplify all loads in device code (details)
  165. [ORC] Require ExecutorProcessControl when constructing an ExecutionSession. (details)
  166. [gn build] Port 2487db1f2862 (details)
  167. [clang][driver] NFC: Move InputInfo.h from lib to include (details)
  168. [clang][driver] NFC: Expose InputInfo in Job instead of plain filenames (details)
  169. [Debug-Info][llvm-dwarfdump] Don't try to dump location (details)
Commit cdcc35476833eca4f4996256e3ca0b21ecc26ad8 by Lang Hames
[ORC][ORC-RT] Add initial Objective-C and Swift support to MachOPlatform.

This allows ORC to execute code containing Objective-C and Swift classes and
methods (provided that the language runtime is loaded into the executor).
The file was modifiedcompiler-rt/lib/orc/macho_platform.h
The file was addedcompiler-rt/test/orc/TestCases/Darwin/x86-64/trivial-objc-methods.S
The file was modifiedllvm/lib/ExecutionEngine/Orc/MachOPlatform.cpp
The file was modifiedllvm/include/llvm/ExecutionEngine/Orc/MachOPlatform.h
The file was modifiedllvm/lib/ExecutionEngine/Orc/Mangling.cpp
The file was modifiedcompiler-rt/lib/orc/macho_platform.cpp
Commit 47afd43eaa9b6f713402aeca8c95f31d13ca5f3c by gchatelet
[libc] fix LibcUnitTestMain when building with shared libraries
The file was modifiedlibc/utils/UnitTest/CMakeLists.txt
Commit eb6c63cb0b6e6ead346f68e438f90ee0451906a3 by vlad.vinogradov
[mlir] Fix RankedTensorType::walkImmediateSubElements method

Add 'enconding' attribute visitor.
Without it ASM printer doesn't use attribute aliases for 'enconding'.

Reviewed By: rriddle

Differential Revision: https://reviews.llvm.org/D105554
The file was modifiedmlir/lib/IR/BuiltinTypes.cpp
The file was modifiedmlir/test/lib/Dialect/Test/TestDialect.cpp
The file was modifiedmlir/test/IR/print-attr-type-aliases.mlir
Commit 93fe84d32fea8e1213bf7207b45e66667d3217f3 by jonathanchesterfield
[libomptarget][nfc] Squash unused variable warning

Suppress only current warning on openmp-clang-x86_64-linux-debian

Reviewed By: jdoerfert

Differential Revision: https://reviews.llvm.org/D106777
The file was modifiedopenmp/libomptarget/src/device.cpp
Commit 2a613a77904467c77c4961cab60fcf6174a0856c by jonathanchesterfield
[libomptarget] Build amdgpu plugin without hsa

Default to building the amdgpu plugin to use dlopen when hsa is
not found instead of disabling it.

Reviewed By: jdoerfert

Differential Revision: https://reviews.llvm.org/D106600
The file was modifiedopenmp/libomptarget/plugins/amdgpu/CMakeLists.txt
Commit 0a3c7960cba15b57f679159c2bb4d20d10b86a5c by kadircet
Revert "Revert D106562 "[clangd] Get rid of arg adjusters in CommandMangler""

This reverts commit 2aa0cf19e7fe17c9eb5eb2555e10184061b933f1.
Get rid of reference to the temporary.
The file was modifiedclang-tools-extra/clangd/CompileCommands.cpp
The file was modifiedclang-tools-extra/clangd/CompileCommands.h
The file was modifiedclang-tools-extra/clangd/Compiler.cpp
The file was modifiedclang-tools-extra/clangd/unittests/CompilerTests.cpp
The file was modifiedclang-tools-extra/clangd/unittests/CompileCommandsTests.cpp
Commit f924a3d47492b7b586ccfd1333ca086a7e2d88b2 by fraser
[SelectionDAG] Support scalable-vector splats in yet more cases

This patch extends support for (scalable-vector) splats in the
DAGCombiner via the `ISD::matchBinaryPredicate` function, which enable a
variety of simple combines of constants.

Users of this function may now have to distinguish between
`BUILD_VECTOR` and `SPLAT_VECTOR` vector operands. The way of dealing
with this in-tree follows the approach added for
`ISD::matchUnaryPredicate` implemented in D94501.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D106575
The file was modifiedllvm/test/CodeGen/RISCV/rvv/urem-seteq-vec.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/combine-splats.ll
The file was modifiedllvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
The file was modifiedllvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
Commit 0aff1798b5721d5f95d16f465b99d357012bb8d1 by david.sherwood
[Analysis] Add simple cost model for strict (in-order) reductions

I have added a new FastMathFlags parameter to getArithmeticReductionCost
to indicate what type of reduction we are performing:

  1. Tree-wise. This is the typical fast-math reduction that involves
  continually splitting a vector up into halves and adding each
  half together until we get a scalar result. This is the default
  behaviour for integers, whereas for floating point we only do this
  if reassociation is allowed.
  2. Ordered. This now allows us to estimate the cost of performing
  a strict vector reduction by treating it as a series of scalar
  operations in lane order. This is the case when FP reassociation
  is not permitted. For scalable vectors this is more difficult
  because at compile time we do not know how many lanes there are,
  and so we use the worst case maximum vscale value.

I have also fixed getTypeBasedIntrinsicInstrCost to pass in the
FastMathFlags, which meant fixing up some X86 tests where we always
assumed the vector.reduce.fadd/mul intrinsics were 'fast'.

New tests have been added here:

  Analysis/CostModel/AArch64/reduce-fadd.ll
  Analysis/CostModel/AArch64/sve-intrinsics.ll
  Transforms/LoopVectorize/AArch64/strict-fadd-cost.ll
  Transforms/LoopVectorize/AArch64/sve-strict-fadd-cost.ll

Differential Revision: https://reviews.llvm.org/D105432
The file was addedllvm/test/Analysis/CostModel/AArch64/reduce-fadd.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/reduce-fmul.ll
The file was modifiedllvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
The file was modifiedllvm/include/llvm/Analysis/TargetTransformInfoImpl.h
The file was modifiedllvm/test/Analysis/CostModel/AArch64/sve-intrinsics.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
The file was modifiedllvm/test/Analysis/CostModel/X86/reduce-fadd.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h
The file was modifiedllvm/include/llvm/CodeGen/BasicTTIImpl.h
The file was modifiedllvm/test/Analysis/CostModel/X86/intrinsic-cost-kinds.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
The file was modifiedllvm/lib/Analysis/TargetTransformInfo.cpp
The file was modifiedllvm/lib/Target/ARM/ARMTargetTransformInfo.h
The file was addedllvm/test/Transforms/LoopVectorize/AArch64/strict-fadd-cost.ll
The file was modifiedllvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
The file was addedllvm/test/Transforms/LoopVectorize/AArch64/sve-strict-fadd-cost.ll
The file was modifiedllvm/lib/Target/X86/X86TargetTransformInfo.h
The file was modifiedllvm/include/llvm/Analysis/TargetTransformInfo.h
The file was modifiedllvm/lib/Target/X86/X86TargetTransformInfo.cpp
The file was modifiedllvm/lib/Transforms/Vectorize/LoopVectorize.cpp
Commit e6ff9179cee48096e7b2e739c9a79db62fa884bb by cullen.rhodes
[AArch64][AsmParser] NFC: Parser.getTok().getLoc() -> getLoc()

Reviewed By: tmatheson

Differential Revision: https://reviews.llvm.org/D106635
The file was modifiedllvm/test/MC/AArch64/shift_extend_op_w_symbol.s
The file was modifiedllvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
Commit e9274af7189333d1f50e47098d9ae30522d7193f by sam.mccall
Revert "[clangd] Avoid range-loop init-list lifetime subtleties."

This reverts commit 253b8145dedbe8d10792f44b4af7f52dbecd527f.

This doesn't actually fix anything - I should stop guessing.
See https://github.com/clangd/clangd/issues/800 for update
The file was modifiedclang-tools-extra/clangd/GlobalCompilationDatabase.cpp
Commit f64e251560203adf0258c96440c0cd637d3a43fc by llvm-dev
[X86][SSE] Don't scrub address math from interleaved shuffle tests
The file was modifiedllvm/test/CodeGen/X86/vector-interleave.ll
The file was modifiedllvm/test/CodeGen/X86/x86-interleaved-access.ll
Commit c8472db0a88701e8c1b183d6568028fefc3406c0 by llvm-dev
[X86][AVX] Prefer vinsertf128 to vperm2f128 on AVX1 targets

Splatting the lower xmm with vinsertf128 is at least as quick as vperm2f128, and a lot faster on some AMD targets.

First step towards PR50053
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was modifiedllvm/test/CodeGen/X86/vector-interleave.ll
The file was modifiedllvm/test/CodeGen/X86/var-permute-128.ll
The file was modifiedllvm/test/CodeGen/X86/vector-shuffle-256-v8.ll
The file was modifiedllvm/test/CodeGen/X86/x86-interleaved-access.ll
Commit 73e4e9cd007a71fb7186933abdcae024fe65cea7 by caroline.concatto
[AArch64][SVE] Improve code generation for vector_splice for Imm == -1

This patch implements vector_splice in tablegen for:
  a) when the immediate is equal to -1 (Imm==1) and uses:
       INSR  +  LASTB
For instance :
@llvm.experimental.vector.splice(Vector_1, Vector_2, -1)
@llvm.experimental.vector.splice(<A,B,C,D>, <E,F,G,H>, 1) ==> <D, E, F, G>
    LAST   RegLast, Vector_1                 // RegLast = D
    INSR   Res, (Vector_1 >> 1), RegLast     // Res = D + E, F, G

Differential Revision: https://reviews.llvm.org/D105633
The file was modifiedllvm/test/CodeGen/AArch64/named-vector-shuffles-sve.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.h
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
Commit b2a5f0029f278dadb62f9e98dec12b1840020324 by david.sherwood
Fix test failures caused by 0aff1798b5721d5f95d16f465b99d357012bb8d1
The file was modifiedllvm/test/Transforms/LoopVectorize/AArch64/sve-strict-fadd-cost.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/AArch64/strict-fadd-cost.ll
Commit 0bfc26e3a4bf291f1d64610fe422c82789d752bc by caroline.concatto
[SVE][AArch64] Improve code generation for vector_splice for Imm > 0

This patch implements vector_splice in tablegen for all cases when the
Immediate is positive and lower than the known minimum value of
a scalable vector.
Vector_splice can be implemented using SVE instruction EXT.
For instance :
    @llvm.experimental.vector.splice(Vector_1, Vector_2, Imm)
    @llvm.experimental.vector.splice(<A,B,C,D>, <E,F,G,H>, 1) ==> <B, C, D, E>
        EXT  Vector_1, Vector_2, Imm              // Vector_1 = B, C, D + Vector_2 = E

Depends on D105633

Differential Revision: https://reviews.llvm.org/D106273
The file was modifiedllvm/test/CodeGen/AArch64/named-vector-shuffles-sve.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp
The file was modifiedllvm/lib/Target/AArch64/SVEInstrFormats.td
The file was modifiedllvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
Commit 20b0fa91c9eebc7501e280049b61e8de352f3c94 by Dylan.Fleming
[SVE] Add support for folding for select + masked loads

Add folds to instcombine to support the removal of select instruction when the masked_load is guaranteed to zero the same lanes, i.e. select(mask, mload(,,mask,0), 0) -> mload(,,mask,0).

Patch originally authored by @paulwalker-arm

Reviewed By: david-arm

Differential Revision: https://reviews.llvm.org/D106376
The file was modifiedllvm/include/llvm/IR/PatternMatch.h
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
The file was addedllvm/test/Transforms/InstCombine/select-masked_load.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/ARM/mve-reductions.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/ARM/mve-reduction-predselect.ll
Commit d995d63767624a60a5d3276f9f16d7b995435af1 by flo
[VPlan] Use stored value from recipes for interleave groups.

Instead of getting the VPValue for the stored IR values through the
current plan, use the stored value of the recipes directly.

This way, the correct VPValues are used if the store recipes have been
modified in the VPlan and the IR value is not correct any longer. This
can happen, e.g. due to D105008.
The file was modifiedllvm/lib/Transforms/Vectorize/LoopVectorize.cpp
Commit 46c03668774c27877bd96957931fafae24383e3f by simon.cook
[Inliner] Make the CallPenalty configurable

Tests with multiple benchmarks, like Embench [1], showed that the
CallPenalty magic number has the most influence on inlining decisions
when optimizing for size.

On the other hand, there was no good default value for this parameter.
Some benchmarks profited strongly from a reduced call penalty. On
example is the picojpeg benchmark compiled for RISC-V, which got 6%
smaller with a CallPenalty of 10 instead of 12. Other benchmarks
increased in size, like matmult.

This commit makes the compromise of turning the magic number constant of
CallPenalty into a configurable value. This introduces the flag
`--inline-call-penalty`. With that flag users can fine tune the inliner
to their needs.

The CallPenalty constant was also used for loops. This commit replaces
the CallPenalty constant with a new LoopPenalty constant that is now
used instead.

This is a slimmed down version of https://reviews.llvm.org/D30899

[1]: https://github.com/embench/embench-iot

Differential Revision: https://reviews.llvm.org/D105976
The file was modifiedllvm/include/llvm/Analysis/InlineCost.h
The file was modifiedllvm/lib/Analysis/InlineCost.cpp
The file was addedllvm/test/Transforms/Inline/inline-call-penalty-option.ll
Commit 8a8d01d58c14c65d6b1a40bf3335c72f6fcd1388 by paul.walker
[NFC] Change VFShape so it contains an ElementCount rather than seperate VF and IsScalable properties.

Differential Revision: https://reviews.llvm.org/D106750
The file was modifiedllvm/lib/Analysis/VFABIDemangling.cpp
The file was modifiedllvm/unittests/Analysis/VectorFunctionABITest.cpp
The file was modifiedllvm/include/llvm/Analysis/VectorUtils.h
The file was modifiedllvm/unittests/Analysis/VectorUtilsTest.cpp
Commit a053afed49897aa34e08287f91c5255efa4e5131 by a.bataev
[SLP]Fix costs calculations.

Need to fix several cost-related problems. The final type may be defined
incorrectly because of to early definition (we may end up with the wider
type), the CommonCost should not be redefined in ExtractElements
cost related calculations and the shuffle of the final insertelements
vectors should be calculated as a cost of single vector permutations
+ costs of two vector permutations for other n-1 incoming vectors.

Differential Revision: https://reviews.llvm.org/D106578
The file was modifiedllvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/vec_list_bias.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/vec_list_bias-inseltpoison.ll
Commit 539437e288f2395288a46a550c4c3070c4b16101 by tpopp
[mlir] split type conversion to two lines for GCC's sake
The file was modifiedmlir/lib/Transforms/BufferDeallocation.cpp
Commit bf28111ebdb760f46f168c867f7e8453c23814ed by caroline.concatto
[AArch65][SVE] Remove vector_splice from AddedComplexity pattern

The pattern for vector_splice with Index equal or bigger than
zero was misplaced in the AddedComplexity = 1 pattern in the AArch64
tablegen file. This patch fixes it by removing vector_splice pattern
from inside AddedComplexity = 1.
The file was modifiedllvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
Commit d7cb2a07967791867c245a6e2e8e4214d69140f7 by a.bataev
Revert "[SLP]Fix costs calculations."

This reverts commit a053afed49897aa34e08287f91c5255efa4e5131 to fix
buildbots.
The file was modifiedllvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/vec_list_bias-inseltpoison.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/vec_list_bias.ll
Commit e484e1ae03325823c469684d7d1532f2aadbe98d by kerry.mclaughlin
[SVE] Fix casts to <FixedVectorType> in truncateToMinimalBitwidths

Fixes more casts to `<FixedVectorType>` for the cases where the
instruction is a Insert/ExtractElementInst.

For fixed-width, this part of truncateToMinimalBitWidths is tested by
AArch64/type-shrinkage-insertelt.ll. I attempted to write a test case for this part
of truncateToMinimalBitWidths which uses scalable vectors, but was unable to add
one. The tests in type-shrinkage-insertelt.ll rely on scalarization to create extract
element instructions for instance, which is not possible for scalable vectors.

Reviewed By: david-arm

Differential Revision: https://reviews.llvm.org/D106163
The file was modifiedllvm/lib/Transforms/Vectorize/LoopVectorize.cpp
Commit ffb3277b0036909a8e622d5758a1e2850eabfd19 by nikita.ppv
[SimplifyCFG] Improve store speculation check

isSafeToSpeculateStore() looks for a preceding store to the same
location to make sure that introducing a new store of the same
value is safe. It currently bails on intervening mayHaveSideEffect()
instructions. However, I believe just checking mayWriteToMemory()
is sufficient there -- we just need to make sure that we know which
value was stored, we don't care if we can unwind in the meantime.

While looking into this, I started having some doubts about the
correctness of the transform with regard to thread safety. While
we don't try to hoist non-simple stores, I believe we also need
to make sure that the preceding store is simple as well. Otherwise
we could introduce a spurious non-atomic write after an atomic write
-- under our memory model this would result in a subsequent undef
atomic read, even if the second write stores the same value as the
first.

Example: https://alive2.llvm.org/ce/z/q_3YAL

Differential Revision: https://reviews.llvm.org/D106742
The file was modifiedllvm/test/Transforms/SimplifyCFG/speculate-store.ll
The file was modifiedllvm/lib/Transforms/Utils/SimplifyCFG.cpp
Commit a487a49acc5a172909d706ffc43240ced1ac0693 by Tim Northover
AArch64: support i128 (& larger) returns in GlobalISel
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll
The file was addedllvm/test/CodeGen/AArch64/GlobalISel/translate-ret.ll
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
The file was modifiedllvm/test/CodeGen/AArch64/arm64-subvector-extend.ll
Commit 010f8e305705acb5128f409256e7f22ff3adc780 by david.green
[ARM] Ensure correct regclass in distributing postinc

The register class required for some MVE loads/stores is more
constrained than the register we use when creating postinc. Make sure we
constrain the register class to keep the code correct.
The file was modifiedllvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
The file was modifiedllvm/test/CodeGen/Thumb2/mve-postinc-distribute.mir
Commit 9ac10658aeda44d8a90ae372c1478610d143c8bb by jay.foad
[AMDGPU] Fix MMO for raw/struct buffer access with non-constant offset

Codegen for the raw/struct buffer access intrinsics would update the
offset in the MMO to reflect the combined offset, if it was known to be
constant. If the combined offset was not known to be constant, or if
there was an index, it would set the offset in the MMO to 0. This is
unsafe because it makes it look like the access does not alias with
another access with a fixed non-zero offset.

Fix these cases by setting the pointer in the MMO to null, to reflect
the fact that we do not have any known IR value pointer + constant
offset for the access.

Differential Revision: https://reviews.llvm.org/D106284
The file was modifiedllvm/test/CodeGen/AMDGPU/extract_subvector_vec4_vec3.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/buffer-intrinsics-mmo-offsets.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/buffer-schedule.ll
The file was modifiedllvm/lib/Target/AMDGPU/SIISelLowering.cpp
Commit 683b9ed0d593f249e992bed63768986b37b49dbb by jay.foad
[AMDGPU] Pre-commit global-isel test case for D106451

This test case shows the scheduler wrongly reordering two buffer
accesses that might alias.
The file was addedllvm/test/CodeGen/AMDGPU/GlobalISel/buffer-schedule.ll
Commit 59f6865231ff7d233e3728b21de2e5aa35189eb3 by jay.foad
[AMDGPU][GISel] Fix MMO for raw/struct buffer access with non-constant offset

Codegen for the raw/struct buffer access intrinsics would update the
offset in the MMO to reflect the combined offset, if it was known to be
constant. If the combined offset was not known to be constant, or if
there was an index, it would set the offset in the MMO to 0. This is
unsafe because it makes it look like the access does not alias with
another access with a fixed non-zero offset.

Fix these cases by setting the pointer in the MMO to null, to reflect
the fact that we do not have any known IR value pointer + constant
offset for the access.

D106284 did this for SelectionDAG. This is the corresponding fix for
GlobalISel.

Differential Revision: https://reviews.llvm.org/D106451
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.cmpswap.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.format.f16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buffer.load.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.fadd.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.f16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.fadd.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.store.format.f16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.add.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.load.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.store.format.f32.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.load.f16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.format.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.raw.buffer.load.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/buffer-schedule.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.cmpswap.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.tbuffer.load.f16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.format.f32.ll
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buffer.store.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.i8.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.format.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.store.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.format.f16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.add.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.format.f16.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.tbuffer.load.ll
Commit 87ed73fe6e01591998eed0dd769353f88919d056 by gbreynoo
[llvm-readobj] Display multiple function names for stack size entries

The current implementation of displaying .stack_size information
presumes that each entry represents a single function but this is not
always the case. For example with the use of ICF multiple functions can
be represented with the same code, meaning that the address found in a
.stack_size entry corresponds to multiple function symbols.
This change allows multiple function names to be displayed when
appropriate.

Differential Revision: https://reviews.llvm.org/D105884
The file was modifiedllvm/test/Object/BPF/yaml2obj-elf-bpf-rel.yaml
The file was modifiedllvm/test/tools/llvm-readobj/ELF/stack-sizes.test
The file was modifiedllvm/tools/llvm-readobj/ELFDumper.cpp
Commit 81600160b3f926746d02c52003d81180941fe9d0 by anastasia.stulova
[OpenCL] Change default standard version to CL1.2

Set default version for OpenCL C to 1.2. This means that the
absence of any standard flag will be equivalent to passing
'-cl-std=CL1.2'.

Note that this patch also fixes incorrect version check for
the pointer to pointer kernel arguments diagnostic and
atomic test.

Differential Revision: https://reviews.llvm.org/D106504
The file was modifiedclang/test/Parser/opencl-cl20.cl
The file was modifiedclang/test/SemaOpenCL/fp64-fp16-options.cl
The file was modifiedclang/test/Parser/opencl-storage-class.cl
The file was modifiedclang/lib/Sema/SemaDecl.cpp
The file was modifiedclang/test/Preprocessor/predefined-macros.c
The file was modifiedclang/test/Parser/opencl-atomics-cl20.cl
The file was modifiedclang/test/SemaOpenCL/func.cl
The file was modifiedclang/test/CodeGenOpenCL/spir_version.cl
The file was modifiedclang/lib/Frontend/CompilerInvocation.cpp
Commit 6ca48efcf6e16adfcf33688d86de7bd2bb75a49a by a.bataev
[SLP]Fix costs calculations.

Need to fix several cost-related problems. The final type may be defined
incorrectly because of to early definition (we may end up with the wider
type), the CommonCost should not be redefined in ExtractElements
cost related calculations and the shuffle of the final insertelements
vectors should be calculated as a cost of single vector permutations
+ costs of two vector permutations for other n-1 incoming vectors.

Differential Revision: https://reviews.llvm.org/D106578
The file was modifiedllvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/vec_list_bias.ll
The file was modifiedllvm/test/Transforms/SLPVectorizer/X86/vec_list_bias-inseltpoison.ll
Commit 93664503be6b3f47269cf617f8c46b6ce95f8076 by flo
[LV] Add test to store a first-order rec via interleave group.

This is a reduced version of the reproducer from
https://bugs.chromium.org/p/chromium/issues/detail?id=1232798#c2
The file was addedllvm/test/Transforms/LoopVectorize/AArch64/interleaved-store-of-first-order-recurrence.ll
Commit f86694cb808f22253e00742ccd279760ef0c688d by jeremy.morse
[InstrRef][AArch64][1/4] Accept constant physreg variable locations

Late in SelectionDAG we join up instruction numbers with their defining
instructions, if it couldn't be done during the main part of SelectionDAG.
One exception is function arguments, where we have to point a DBG_PHI
instruction at the incoming live register, as they don't have a defining
instruction. This patch adds another exception, for constant physregs, like
aarch64 has.

It may seem wasteful to use two instructions where we could use a single
DBG_VALUE, however the whole point of instruction referencing is to
decouple the identification of values from the specification of where
variable location ranges start.

(Part of my aarch64 work to ease adoption of  instruction referencing, as
in the meta comment on D104520)

Differential Revision: https://reviews.llvm.org/D104520
The file was addedllvm/test/DebugInfo/AArch64/instr-ref-const-physreg.ll
The file was modifiedllvm/lib/CodeGen/MachineFunction.cpp
Commit 4761321d49db01dce1e308f900add033cc26fb47 by gabor.marton
[Analyzer][solver][NFC] print constraints deterministically (ordered by their string representation)

This change is an extension to D103967 where I added dump methods for
(dis)equality classes of the State. There, the (dis)equality classes and their
contents are dumped in an ordered fashion, they are ordered based on their
string representation. This is very useful once we start to use FileCheck to
test the State dump in certain tests.

Differential Revision: https://reviews.llvm.org/D106642
The file was modifiedclang/lib/StaticAnalyzer/Core/RangeConstraintManager.cpp
Commit 404f0d4f7cc7b7497c9725c6c6f20b21df8611bb by benny.kra
Simplify away some SmallVector copies. NFCI.

The lifetime of the initializer list is the full expression, so we can
skip storing it in a temporary vector.
The file was modifiedllvm/include/llvm/IR/DerivedTypes.h
The file was modifiedllvm/include/llvm/IR/Constants.h
Commit 33146857e9840a92840d48bbc3483e34ea545fc7 by nikita.ppv
[IR] Consider non-willreturn as side effect (PR50511)

This adjusts mayHaveSideEffect() to return true for !willReturn()
instructions. Just like other side-effects, non-willreturn calls
(aka "divergence") cannot be removed and cannot be reordered relative
to other side effects. This fixes a number of bugs where
non-willreturn calls are either incorrectly dropped or moved. In
particular, it also fixes the last open problem in
https://bugs.llvm.org/show_bug.cgi?id=50511.

I performed a cursory review of all current mayHaveSideEffect()
uses, which convinced me that these are indeed the desired default
semantics. Places that do not want to consider non-willreturn as a
sideeffect generally do not want mayHaveSideEffect() semantics at
all. I identified two such cases, which are addressed by D106591
and D106742. Finally, there is a use in SCEV for which we don't
really have an appropriate API right now -- what it wants is
basically "would this be considered forward progress". I've just
spelled out the previous semantics there.

Differential Revision: https://reviews.llvm.org/D106749
The file was modifiedllvm/test/Transforms/LoopDeletion/noop-loops-with-subloops.ll
The file was modifiedllvm/lib/Analysis/ScalarEvolution.cpp
The file was modifiedllvm/test/Transforms/SCCP/calltest.ll
The file was modifiedllvm/lib/Analysis/DemandedBits.cpp
The file was modifiedllvm/include/llvm/IR/Instruction.h
The file was modifiedllvm/test/Transforms/LICM/sinking.ll
The file was modifiedllvm/lib/Transforms/Scalar/ADCE.cpp
The file was modifiedllvm/lib/IR/Instruction.cpp
Commit 1139fd4270c7462a4bce8e1e91e6be174dcae88f by koraq
[libc++][ci] Detect not committed generated files.

The Generated output CI job only tests for modified files. This job
should also fail the generated output contains new files.

It would be possible to test modified and untracked files in one
execution of `git ls-files`. However the diff is stored as an artifact
so the execution of `git diff` would still be required.

Discussion: Would it be better to do `git ls-files -om` and remove the
excution of
`! grep -q '^--- a' ${BUILD_DIR}/generated_output.patch || false` ?
(Obviously then the name `generated_output.untracked` should change to
something like `generated_output.status`)

Reviewed By: #libc, ldionne

Differential Revision: https://reviews.llvm.org/D106534
The file was modifiedlibcxx/utils/ci/run-buildbot
The file was modifiedlibcxx/utils/ci/buildkite-pipeline.yml
Commit 7a1e73f0b9fcfec0e90aff735f0ac4cfb6b9ec41 by flo
Recommit "[VPlan] Add recipe for first-order rec phis, make splicing explicit."

This reverts the revert commit b1777b04dc4b1a9fee0e7effa7e177892ab32ef0.

The patch originally got reverted due to a crash:
https://bugs.chromium.org/p/chromium/issues/detail?id=1232798#c2

The underlying issue was that we were not using the stored values from
the modified memory recipes, but the out-of-date values directly from
the IR (accessed via the VPlan). This should be fixed in d995d6376. A
reduced version of the reproducer has been added in 93664503be6b.
The file was modifiedllvm/lib/Transforms/Vectorize/VPlan.cpp
The file was modifiedllvm/test/Transforms/LoopVectorize/interleaved-accesses.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/scalable-first-order-recurrence.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/first-order-recurrence.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/first-order-recurrence-complex.ll
The file was modifiedllvm/lib/Transforms/Vectorize/VPlan.h
The file was modifiedllvm/test/Transforms/LoopVectorize/induction.ll
The file was modifiedllvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
The file was modifiedllvm/test/Transforms/LoopVectorize/first-order-recurrence-sink-replicate-region.ll
The file was modifiedllvm/lib/Transforms/Vectorize/LoopVectorize.cpp
The file was modifiedllvm/lib/Transforms/Vectorize/VPlanValue.h
The file was modifiedllvm/test/Transforms/LoopVectorize/vplan-sink-scalars-and-merge.ll
Commit 8cd8120a7b5d4c6f7674679b53477b51fd054a27 by ulrich.weigand
[SystemZ] Add support for new cpu architecture - arch14

This patch adds support for the next-generation arch14
CPU architecture to the SystemZ backend.

This includes:
- Basic support for the new processor and its features.
- Detection of arch14 as host processor.
- Assembler/disassembler support for new instructions.
- New LLVM intrinsics for certain new instructions.
- Support for low-level builtins mapped to new LLVM intrinsics.
- New high-level intrinsics in vecintrin.h.
- Indicate support by defining  __VEC__ == 10304.

Note: No currently available Z system supports the arch14
architecture.  Once new systems become available, the
official system name will be added as supported -march name.
The file was modifiedllvm/lib/Target/SystemZ/SystemZSubtarget.h
The file was addedllvm/test/MC/Disassembler/SystemZ/insns-arch14.txt
The file was modifiedclang/lib/Headers/vecintrin.h
The file was modifiedclang/test/Preprocessor/predefined-arch-macros.c
The file was addedclang/test/CodeGen/SystemZ/builtins-systemz-vector4.c
The file was modifiedllvm/lib/Target/SystemZ/SystemZProcessors.td
The file was modifiedllvm/test/MC/SystemZ/insn-bad-z15.s
The file was modifiedllvm/lib/Support/Host.cpp
The file was addedclang/test/CodeGen/SystemZ/builtins-systemz-vector4-error.c
The file was modifiedclang/test/CodeGen/SystemZ/systemz-abi-vector.c
The file was modifiedclang/test/Misc/target-invalid-cpu-note.c
The file was modifiedllvm/lib/Target/SystemZ/SystemZInstrInfo.td
The file was modifiedllvm/lib/Target/SystemZ/SystemZInstrSystem.td
The file was modifiedllvm/lib/Target/SystemZ/SystemZInstrVector.td
The file was modifiedclang/include/clang/Basic/BuiltinsSystemZ.def
The file was modifiedclang/lib/Basic/Targets/SystemZ.h
The file was modifiedclang/lib/Sema/SemaChecking.cpp
The file was addedclang/test/CodeGen/SystemZ/builtins-systemz-zvector4-error.c
The file was modifiedllvm/include/llvm/IR/IntrinsicsSystemZ.td
The file was modifiedllvm/lib/Target/SystemZ/SystemZSubtarget.cpp
The file was addedllvm/test/MC/SystemZ/insn-bad-arch14.s
The file was modifiedllvm/lib/Target/SystemZ/SystemZInstrFormats.td
The file was modifiedclang/lib/Basic/Targets/SystemZ.cpp
The file was addedllvm/test/CodeGen/SystemZ/vec-intrinsics-04.ll
The file was addedllvm/test/MC/SystemZ/insn-good-arch14.s
The file was modifiedclang/test/CodeGen/SystemZ/systemz-abi.c
The file was modifiedclang/test/CodeGen/target-data.c
The file was addedclang/test/CodeGen/SystemZ/builtins-systemz-zvector4.c
The file was modifiedllvm/lib/Target/SystemZ/SystemZFeatures.td
The file was modifiedllvm/unittests/Support/Host.cpp
The file was modifiedclang/test/Driver/systemz-march.c
Commit 3274cdc83ecdf2af569ad4f564d55d0e43b1072e by tianshilei1992
[Clang][OpenMP] Remove the mandatory flush for capture for OpenMP 5.1

In OpenMP 5.1:
> If the `write` or `update` clause is specifieded, the atomic operation is not an atomic conditional update for which the comparison fails, and the effective memory ordering is `release`, `acq_rel`, or `seq_cst`, the strong flush on entry to the atomic operation is also a release flush. If the `read` or `update` clause is specified and the effective memory ordering is `acquire`, `acq_rel`, or `seq_cst` then the strong flush on exit from the atomic operation is also an acquire flush.

In OpenMP 5.0:
> If the `write`, `update`, or **`capture`** clause is specified and the `release`, `acq_rel`, or `seq_cst` clause is specified then the strong flush on entry to the atomic operation is also a release flush. If the `read` or `capture` clause is specified and the `acquire`, `acq_rel`, or `seq_cst` clause is specified then the strong flush on exit from the atomic operation is also an acquire flush.

From my understanding, in OpenMP 5.1, `capture` is removed from the requirement for flush, therefore we don't have to enforce it.

Reviewed By: ABataev

Differential Revision: https://reviews.llvm.org/D100768
The file was modifiedclang/lib/CodeGen/CGStmtOpenMP.cpp
The file was modifiedclang/test/OpenMP/atomic_capture_codegen.cpp
Commit 81eafb8a37c9f0eecd3b73642d94eee3bae490bf by bradley.smith
[AArch64][SVE] Break false dependencies for inactive lanes of unary operations

Differential Revision: https://reviews.llvm.org/D105889
The file was modifiedllvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrFormats.td
The file was addedllvm/test/CodeGen/AArch64/sve-unary-movprfx.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
The file was modifiedllvm/test/CodeGen/AArch64/sve-forward-st-to-ld.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrInfo.h
The file was modifiedllvm/lib/Target/AArch64/SVEInstrFormats.td
The file was addedllvm/test/CodeGen/AArch64/sve2-unary-movprfx.ll
The file was modifiedllvm/test/CodeGen/AArch64/sve-gather-scatter-dag-combine.ll
The file was modifiedllvm/test/CodeGen/AArch64/sve-masked-gather-legalize.ll
Commit 981e9dce548277eaf3f6725bf5ffe84e03f658b1 by sander.desmalen
[LV] Don't assume isScalarAfterVectorization if one of the uses needs widening.

This fixes an issue that was found in D105199, where a GEP instruction
is used both as the address of a store, as well as the value of a store.
For the former, the value is scalar after vectorization, but the latter
(as value) requires widening.

Other code in that function seems to prevent similar cases from happening,
but it seems this case was missed.

Reviewed By: david-arm

Differential Revision: https://reviews.llvm.org/D106164
The file was modifiedllvm/test/Transforms/LoopVectorize/AArch64/predication_costs.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/pointer-induction.ll
The file was addedllvm/test/Transforms/LoopVectorize/AArch64/sve-widen-gep.ll
The file was modifiedllvm/lib/Transforms/Vectorize/LoopVectorize.cpp
Commit 0d3807b365e5aeee34a3c3887813996907eb7ddb by nikita.ppv
[MergeICmps] Separate out BCECmp and use Optional (NFC)

Separate out the BCECmp part from BCECmpBlock, which just stores
the comparison atoms without the branch instruction. At the same
time switch the code to return Optional<> rather than objects in
invalid state and partially constructed objects.
The file was modifiedllvm/lib/Transforms/Scalar/MergeICmps.cpp
Commit d8260269c32c1c1140c8061ba469e28a75ccc159 by spatel
[SimplifyLibCalls] reduce code duplication; NFC
The file was modifiedllvm/lib/Transforms/Utils/SimplifyLibCalls.cpp
Commit 87d604ffe494fcf66e469e2758c289f18b0e7ce9 by spatel
[SimplifyLibCalls] avoid crash on pointer math

We could try harder to screen out libcalls by
function signature (and that would be a much larger
change than for sprintf alone), but that might make
the transition to type-less pointers more difficult.

https://llvm.org/PR51200
The file was modifiedllvm/test/Transforms/InstCombine/stpcpy-1.ll
The file was modifiedllvm/lib/Transforms/Utils/SimplifyLibCalls.cpp
Commit 3ca6dea05dec44680f29a40de7481aede09cae8a by Louis Dionne
[libc++][NFC] Change a few instances of > > to >> in C++20 code
The file was modifiedlibcxx/include/__ranges/concepts.h
The file was modifiedlibcxx/include/__iterator/concepts.h
Commit 3b77e2737c8545aa628e1d2cff5799db033f7081 by paul.walker
[SVE] Use reg+reg addressing mode for immediate offsets.

For reg+imm SVE addressing mode imm is implictly scaled by VL,
making them impractical for truely immediate offsets.  However, if
the offset can be unscaled based on the storage element type we
can use the reg+reg SVE addressing mode and thus either reduce the
number of generate add instructions or replace them with a mov
instruction that can be hoisted from the hot code path.

Differential Revision: https://reviews.llvm.org/D106744
The file was modifiedllvm/test/CodeGen/AArch64/sve-fixed-length-float-compares.ll
The file was modifiedllvm/test/CodeGen/AArch64/sve-fixed-length-int-shifts.ll
The file was modifiedllvm/test/CodeGen/AArch64/sve-fixed-length-int-to-fp.ll
The file was modifiedllvm/test/CodeGen/AArch64/sve-fixed-length-trunc-stores.ll
The file was modifiedllvm/test/CodeGen/AArch64/sve-fixed-length-log-reduce.ll
The file was modifiedllvm/test/CodeGen/AArch64/sve-fixed-length-int-reduce.ll
The file was modifiedllvm/test/CodeGen/AArch64/sve-fixed-length-fp-rounding.ll
The file was modifiedllvm/test/CodeGen/AArch64/sve-fixed-length-fp-extend-trunc.ll
The file was modifiedllvm/test/CodeGen/AArch64/sve-fixed-length-fp-reduce.ll
The file was modifiedllvm/test/CodeGen/AArch64/sve-fixed-length-fp-to-int.ll
The file was modifiedllvm/test/CodeGen/AArch64/sve-fixed-length-stores.ll
The file was modifiedllvm/test/CodeGen/AArch64/sve-fixed-length-vector-shuffle.ll
The file was modifiedllvm/test/CodeGen/AArch64/sve-intrinsics-ld1ro-addressing-mode-reg-imm.ll
The file was modifiedllvm/test/CodeGen/AArch64/sve-fixed-length-fp-arith.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
The file was modifiedllvm/test/CodeGen/AArch64/sve-fixed-length-loads.ll
The file was modifiedllvm/test/CodeGen/AArch64/sve-fixed-length-rev.ll
The file was modifiedllvm/test/CodeGen/AArch64/sve-fixed-length-int-compares.ll
The file was modifiedllvm/test/CodeGen/AArch64/sve-fixed-length-int-extends.ll
The file was modifiedllvm/test/CodeGen/AArch64/sve-vscale-attr.ll
The file was modifiedllvm/test/CodeGen/AArch64/named-vector-shuffles-sve.ll
The file was modifiedllvm/test/CodeGen/AArch64/sve-fixed-length-masked-gather.ll
The file was modifiedllvm/test/CodeGen/AArch64/sve-fixed-length-int-minmax.ll
The file was modifiedllvm/test/CodeGen/AArch64/sve-fixed-length-masked-scatter.ll
The file was modifiedllvm/test/CodeGen/AArch64/sve-fixed-length-splat-vector.ll
The file was modifiedllvm/test/CodeGen/AArch64/sve-fixed-length-fp-minmax.ll
The file was modifiedllvm/test/CodeGen/AArch64/sve-fixed-length-bit-counting.ll
Commit 0c9978473e53833211669920370e2909303f0b49 by kazu
[AsmParser] Remove MDRef (NFC)

The last use was removed on Jan 12, 2015 in commit
ab617d597708fcf3c4b829bf595e9d990ca66c07.
The file was modifiedllvm/include/llvm/AsmParser/LLParser.h
Commit c691651c53485a07db5b529e5a465eee397b7987 by nikita.ppv
[MergeICmps] Try to fix MSVC build failure

Apparently this fails to line up the types -- try to sidestep the
issue entirely by writing the code in a more reasonable way: Walk
over the operands and perform a set lookup, rather than walking
over the set and performing an operand scan.
The file was modifiedllvm/lib/Transforms/Scalar/MergeICmps.cpp
Commit c0da287c30c9f511ccb07fdd42c997be2caea9ec by i
[yaml2obj][MachO] Rename PayloadString to Content

The new name is conciser and matches yaml2obj ELF & DWARF.

Reviewed By: #lld-macho, thakis

Differential Revision: https://reviews.llvm.org/D106759
The file was modifiedllvm/test/ObjectYAML/MachO/export_trie.yaml
The file was modifiedllvm/test/tools/llvm-objcopy/MachO/install-name-tool-rpath.test
The file was modifiedllvm/test/tools/llvm-objcopy/MachO/install-name-tool-id.test
The file was modifiedllvm/test/tools/llvm-dwarfdump/uuid.yaml
The file was modifiedllvm/test/tools/llvm-objcopy/MachO/lc-load-weak-dylib.test
The file was modifiedllvm/test/tools/llvm-objcopy/MachO/install-name-tool-delete-rpath.test
The file was modifiedlld/test/MachO/zippered.yaml
The file was modifiedllvm/lib/ObjectYAML/MachOYAML.cpp
The file was modifiedlld/test/MachO/dylib-stub.yaml
The file was modifiedllvm/test/ObjectYAML/MachO/symtab.yaml
The file was modifiedllvm/test/tools/llvm-objcopy/MachO/basic-executable-copy.test
The file was modifiedllvm/lib/ObjectYAML/MachOEmitter.cpp
The file was modifiedllvm/tools/obj2yaml/macho2yaml.cpp
The file was modifiedllvm/test/tools/llvm-objcopy/MachO/segment-size-alignment.test
The file was modifiedllvm/test/tools/llvm-lipo/Inputs/armv7-slice-big.yaml
The file was modifiedllvm/test/tools/llvm-objcopy/MachO/Inputs/strip-all.yaml
The file was modifiedllvm/test/tools/llvm-dwarfdump/uuid32.yaml
The file was modifiedllvm/test/tools/llvm-objcopy/MachO/segments-vmsize.test
The file was modifiedllvm/test/ObjectYAML/MachO/dylib_dylinker_command.yaml
The file was modifiedllvm/test/tools/llvm-lipo/Inputs/CPU10-slice.yaml
The file was modifiedllvm/test/ObjectYAML/MachO/null_string_entries.yaml
The file was modifiedllvm/test/ObjectYAML/MachO/out_of_order_linkedit.yaml
The file was modifiedllvm/include/llvm/ObjectYAML/MachOYAML.h
The file was modifiedllvm/test/tools/llvm-objcopy/MachO/remove-lc-index-update.test
The file was modifiedllvm/test/tools/llvm-objcopy/MachO/install-name-tool-change.test
The file was modifiedllvm/test/tools/llvm-tapi-diff/Inputs/macho.yaml
The file was modifiedllvm/test/tools/llvm-readobj/MachO/needed-libs.test
Commit 792c206e2b63c16075d759d3abc3eb5399ed74fe by i
[llvm-objcopy] Drop GRP_COMDAT if the group signature is localized

See [GRP_COMDAT group with STB_LOCAL signature](https://groups.google.com/g/generic-abi/c/2X6mR-s2zoc)
objcopy PR: https://sourceware.org/bugzilla/show_bug.cgi?id=27931

GRP_COMDAT deduplication is purely based on the signature symbol name in
ld.lld/GNU ld/gold. The local/global status is not part of the equation.

If the signature symbol is localized by --localize-hidden or
--keep-global-symbol, the intention is likely to make the group fully
localized. Drop GRP_COMDAT to suppress deduplication.

Reviewed By: jhenderson

Differential Revision: https://reviews.llvm.org/D106782
The file was modifiedllvm/test/tools/llvm-objcopy/ELF/group-reorder.test
The file was modifiedllvm/test/tools/llvm-objcopy/ELF/group.test
The file was modifiedllvm/tools/llvm-objcopy/ELF/Object.cpp
The file was modifiedllvm/test/tools/llvm-objcopy/ELF/strip-dwo-groups.test
The file was modifiedllvm/test/tools/llvm-objcopy/ELF/remove-section-in-group.test
Commit f921bf6049df6cb8b8a030fedd15351d003f91a9 by nikita.ppv
[MergeICmps] Collect block instructions once (NFC)

Collect the relevant instructions for a given BCECmpBlock once
on construction, rather than repeating this logic in multiple
places.
The file was modifiedllvm/lib/Transforms/Scalar/MergeICmps.cpp
Commit e8a64e5491260714c79dab65d1aa73245931d314 by cjdb
[clang][pp] adds '#pragma include_instead'

`#pragma clang include_instead(<header>)` is a pragma that can be used
by system headers (and only system headers) to indicate to a tool that
the file containing said pragma is an implementation-detail header and
should not be directly included by user code.

The library alternative is very messy code that can be seen in the first
diff of D106124, and we'd rather avoid that with something more
universal.

This patch takes the first step by warning a user when they include a
detail header in their code, and suggests alternative headers that the
user should include instead. Future work will involve adding a fixit to
automate the process, as well as cleaning up modules diagnostics to not
suggest said detail headers. Other tools, such as clangd can also take
advantage of this pragma to add the correct user headers.

Differential Revision: https://reviews.llvm.org/D106394
The file was addedclang/test/Preprocessor/Inputs/include_instead/public-before.h
The file was addedclang/test/Preprocessor/Inputs/include_instead/file-not-found.h
The file was modifiedclang/lib/Lex/PPLexerChange.cpp
The file was addedclang/test/Preprocessor/Inputs/include_instead/non-system-header.h
The file was modifiedclang/lib/Lex/Lexer.cpp
The file was addedclang/test/Preprocessor/Inputs/include_instead/bad-syntax.h
The file was addedclang/test/Preprocessor/Inputs/include_instead/private3.h
The file was addedclang/test/Preprocessor/Inputs/include_instead/public-empty.h
The file was addedclang/test/Preprocessor/Inputs/include_instead/public-after.h
The file was addedclang/test/Preprocessor/include_instead.cpp
The file was addedclang/test/Preprocessor/Inputs/include_instead/private-x.h
The file was addedclang/test/Preprocessor/include_instead_file_not_found.cpp
The file was modifiedclang/include/clang/Lex/Preprocessor.h
The file was modifiedclang/lib/Lex/PPDirectives.cpp
The file was modifiedclang/include/clang/Lex/PreprocessorLexer.h
The file was modifiedclang/lib/Lex/Pragma.cpp
The file was addedclang/test/Preprocessor/Inputs/include_instead/private2.h
The file was modifiedclang/include/clang/Lex/HeaderSearch.h
The file was modifiedclang/include/clang/Basic/DiagnosticLexKinds.td
The file was addedclang/test/Preprocessor/Inputs/include_instead/private1.h
Commit b9051ba84836f6c2a3b008638de14b588e58fa9f by sander.desmalen
[LV] Remove assert that VF cannot be scalable in setCostBasedWideningDecision.

Scalarization for scalable vectors is not (yet) supported, so the
LV discards a VF when scalarization is chosen as the widening
decision. It should therefore not assert that the VF is not scalable
when it computes the decision to scalarize.

The code can get here when both the interleave-cost, gather/scatter cost
and scalarization-cost are all illegal. This may e.g. happen for SVE
when the VF=1, to avoid generating `<vscale x 1 x eltty>` types that
the code-generator cannot yet handle.

Reviewed By: david-arm

Differential Revision: https://reviews.llvm.org/D106656
The file was modifiedllvm/test/Transforms/LoopVectorize/AArch64/sve-gather-scatter.ll
The file was modifiedllvm/lib/Transforms/Vectorize/LoopVectorize.cpp
Commit 77c5e6ba900a167909873d2364d55b6a19df8994 by llvm-dev
[Analysis] Fix getOrderedReductionCost to call target's getArithmeticInstrCost implementation

The getOrderedReductionCost implementation introduced in D105432 calls the CRTP base version getArithmeticInstrCost instead of the redirecting to the target version.

Differential Revision: https://reviews.llvm.org/D106795
The file was modifiedllvm/include/llvm/CodeGen/BasicTTIImpl.h
The file was modifiedllvm/test/Analysis/CostModel/X86/reduce-fadd.ll
The file was modifiedllvm/test/Analysis/CostModel/X86/reduce-fmul.ll
Commit fbaf7f0bc768bb236db49a2fea79169f91c10720 by Louis Dionne
[libc++] Add range_size_t

Differential Revision: https://reviews.llvm.org/D106708
The file was modifiedlibcxx/include/ranges
The file was addedlibcxx/test/std/ranges/range.req/range.range/range_size_t.compile.pass.cpp
The file was modifiedlibcxx/include/__ranges/concepts.h
The file was modifiedlibcxx/docs/Status/RangesPaper.csv
Commit 240dde948252ab9ef0428c46ca578c06127d3799 by qiucofan
[PowerPC] Change altivec indexed load/store builtins argument type

This patch changes the index argument of lvxl?/lve[bhw]x and
stvxl?/stve[bhw]x builtins from int to long. Because on 64-bit
subtargets, an extra extsw will always been generated, which is
incorrect.

Reviewed By: nemanjai

Differential Revision: https://reviews.llvm.org/D106530
The file was modifiedclang/test/CodeGen/ppc-xmmintrin.c
The file was modifiedclang/test/CodeGen/ppc-emmintrin.c
The file was modifiedclang/lib/Headers/altivec.h
The file was modifiedclang/include/clang/Basic/BuiltinsPPC.def
Commit 31e75512174e1bdaa242ee5c7f30fe56e68c3748 by stephen.tozer
[DebugInfo] Correctly update debug users of SSA values in tail duplication

During tail duplication, SSA values may be updated and have their uses
replaced with a virtual register, and any debug instructions that use
that value are deleted. This patch fixes the implementation of the debug
instruction deletion to work correctly for debug instructions that use
the SSA value multiple times, by batching deletions so that we don't
attempt to delete the same instruction twice.

Differential Revision: https://reviews.llvm.org/D106557
The file was modifiedllvm/lib/CodeGen/TailDuplicator.cpp
The file was addedllvm/test/CodeGen/X86/tail-dup-debugvalue.mir
Commit 6d753b0751b1f4b6fb6851b69627244722c57a64 by flo
[LAA] Remove RuntimeCheckingPtrGroup::RtCheck member (NFC).

This patch removes RtCheck from RuntimeCheckingPtrGroup to make it
possible to construct RuntimeCheckingPtrGroup objects without a
RuntimePointerChecking object. This should make it easier to
re-use the code to generate runtime checks, e.g. in D102834.

RtCheck was only used to access the pointer info for a given index.
Instead, the start and end expressions can be passed directly.

For code-gen, we also need to know the address space to use. This can
also be explicitly passed at construction.

Reviewed By: efriedma

Differential Revision: https://reviews.llvm.org/D105481
The file was modifiedllvm/lib/Analysis/LoopAccessAnalysis.cpp
The file was modifiedllvm/include/llvm/Analysis/LoopAccessAnalysis.h
The file was modifiedllvm/lib/Transforms/Utils/LoopUtils.cpp
Commit fbe6eac8bd65e6e144a647a40df0192ab482129b by llvm-dev
[X86][AVX] Add PR50053 test case
The file was modifiedllvm/test/CodeGen/X86/avx-vperm2x128.ll
Commit b71b25008f2a746d11ed1db1f49a6461b387cc8a by i
[test] Fix PayloadString: in lldb tests
The file was modifiedlldb/test/Shell/ObjectFile/MachO/lc_version_min.yaml
The file was modifiedlldb/test/API/macosx/version_zero/libDylib.dylib.yaml
The file was modifiedlldb/test/Shell/ObjectFile/MachO/lc_build_version_notools.yaml
The file was modifiedlldb/test/Shell/ObjectFile/MachO/symtab.yaml
The file was modifiedlldb/test/Shell/ObjectFile/MachO/lc_build_version.yaml
Commit 055fa446fd4412c2006e9bc56b31da5afcc5da62 by rob.suderman
[mlir][tosa] Disable tosa shape verification between operands/results

Tosa shape verification prevent shape propagation when coming from a dialect
of known shape. Relax this constraint to allow ingestion / shape propagation
from these other dialects.

Differential Revision: https://reviews.llvm.org/D106610
The file was modifiedmlir/include/mlir/Dialect/Tosa/IR/TosaOps.td
The file was modifiedmlir/include/mlir/IR/OpBase.td
The file was modifiedmlir/include/mlir/Dialect/Tosa/IR/TosaTypesBase.td
Commit 6b9aba43a2392c307694229261c2be66557b6e88 by aheejin
[WebAssembly] Improve pseudocode in LowerEmscriptenEHSjLj

Both `__THREW__` and `__threwValue` are global variables, and we have
been distinguishing the global variable `__THREW__` and the loaded value
`%__THREW__.val` in comments but not doing it for `__threwValue`. Made
the pseudocode comments consistent for both variables.

Reviewed By: dschuff

Differential Revision: https://reviews.llvm.org/D106524
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyLowerEmscriptenEHSjLj.cpp
Commit 016ae7df95f2d30bc8e44d5e06571e7510770379 by michaelrj
[libc] add scudo wrappers to llvm libc

The previous patch included the implementations for the scudo allocator,
but not the wrappers. This change fixes that.

Reviewed By: sivachandra

Differential Revision: https://reviews.llvm.org/D106718
The file was modifiedlibc/lib/CMakeLists.txt
Commit dec34104bfa505f39bb81d24c9ca064a4a03c88a by Amara Emerson
[GlobalISel] Add combine for merge(unmerge) and use AArch64 postlegal-combiner.

Differential Revision: https://reviews.llvm.org/D106761
The file was modifiedllvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
The file was modifiedllvm/include/llvm/Target/GlobalISel/Combine.td
The file was addedllvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-merge.mir
The file was modifiedllvm/lib/Target/AArch64/AArch64Combine.td
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
Commit 0d41d21929d4366997e67f986689eef0253547b6 by Amara Emerson
[AArch64][GlobalISel] Enable some select combines after legalization.

The legalizer generates selects for some operations, which can have constant
condition values, resulting in lots of dead code if it's not folded away.

Differential Revision: https://reviews.llvm.org/D106762
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic-128.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64Combine.td
The file was modifiedllvm/test/CodeGen/AArch64/fold-global-offsets.ll
The file was addedllvm/test/CodeGen/AArch64/GlobalISel/postlegalizercombiner-select.mir
Commit 5c486ce04db4d33ae5be65dac4a03d1b0f46f3e2 by efriedma
[LLVM IR] Allow volatile stores to trap.

Proposed alternative to D105338.

This is ugly, but short-term I think it's the best way forward: first,
let's formalize the hacks into a coherent model. Then we can consider
extensions of that model (we could have different flavors of volatile
with different rules).

Differential Revision: https://reviews.llvm.org/D106309
The file was modifiedllvm/lib/IR/Instruction.cpp
The file was modifiedllvm/lib/Transforms/InstCombine/InstructionCombining.cpp
The file was modifiedllvm/test/Transforms/FunctionAttrs/nosync.ll
The file was modifiedllvm/docs/LangRef.rst
The file was modifiedllvm/lib/Analysis/ValueTracking.cpp
The file was modifiedllvm/lib/Transforms/Utils/SimplifyCFG.cpp
The file was modifiedllvm/test/Transforms/LICM/sink-debuginfo-preserve.ll
The file was modifiedllvm/test/Transforms/PhaseOrdering/inlining-alignment-assumptions.ll
Commit 6af8d360546e01ee2e8c8c45fb5d0cf39fcda462 by Amara Emerson
[AArch4][GlobalISel] Post-legalize combine s64 = G_MERGE s32, 0 -> G_ZEXT.

These are generated as a byproduce of legalization.

Differential Revision: https://reviews.llvm.org/D106768
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-merge.mir
The file was modifiedllvm/lib/Target/AArch64/AArch64Combine.td
Commit a98f394e81f4dd70dc2a4a3a6640b10a6144cc3f by gclayton
[LLDB][GUI] Resolve paths in file/directory fields

This patch resolves the paths in the file/directory fields before
performing checks. Those checks are applied on the file system if
m_need_to_exist is true, so remote files can set this to false to avoid
performing host-side file system checks. Additionally, methods to get
a resolved and a direct file specs were added to be used by client code.

Reviewed By: clayborg

Differential Revision: https://reviews.llvm.org/D106553
The file was modifiedlldb/source/Core/IOHandlerCursesGUI.cpp
Commit 2a7ee6b5c12444255726b9fd1b276468a7a698d9 by kevin.neal
[FPEnv][InstSimplify] Enable more folds for constrained fadd

Precommit tests, try 2. My tree is up-to-date as of this morning so this
should go better than my first try.
The file was addedllvm/test/Transforms/InstSimplify/strictfp-fadd.ll
Commit cf54424a46ffb505bd1a117a44fc30c01bbff882 by dschuff
[lld][WebAssembly] Do not remove name section with --strip-debug

Leave the name section in the output when using the --strip-debug
flag. This treats it more like ELF symbol tables, as the name
section has similar uses at runtime (e.g. wasm engines understand
it and it can be used for symbolization at runtime).

Fixes https://github.com/emscripten-core/emscripten/issues/14623

Differential Revision: https://reviews.llvm.org/D106728
The file was modifiedlld/test/wasm/weak-undefined.s
The file was modifiedlld/test/wasm/strip-debug.test
The file was modifiedlld/wasm/SyntheticSections.h
Commit 1c50a5da364fd57905ec170ed9ba64d3c7e416f3 by nemanja.i.ibm
[PowerPC] Implement partial vector ld/st builtins for XL compatibility

XL provides functions __vec_ldrmb/__vec_strmb for loading/storing a
sequence of 1 to 16 bytes in big endian order, right justified in the
vector register (regardless of target endianness).
This is equivalent to vec_xl_len_r/vec_xst_len_r which are only
available on Power9.

This patch simply uses the Power9 functions when compiled for Power9,
but provides a more general implementation for Power8.

Differential revision: https://reviews.llvm.org/D106757
The file was modifiedclang/test/CodeGen/builtins-ppc-xlcompat-pwr8.c
The file was modifiedclang/lib/CodeGen/CGBuiltin.cpp
The file was modifiedclang/lib/Sema/SemaChecking.cpp
The file was modifiedclang/include/clang/Basic/BuiltinsPPC.def
The file was addedclang/test/CodeGen/builtins-ppc-xlcompat-vec-error.c
The file was modifiedclang/lib/Headers/altivec.h
The file was addedclang/test/CodeGen/builtins-ppc-ld-st-rmb.c
Commit b31080c596246bc26d2493cfd5e07f053cf9541c by raul
[compiler-rt][CMake][arm64] Use a custom target for symlinking LSE sources

On Apple platforms the builtins may be built for both arm64 and arm64e.
With Makefile generators separate targets are built using Make sub-invocations.
This causes a race when creating the symlink which may sometimes fail.

Work around this by using a custom target that the builtin targets depend on.
This causes any sub-invocations to depend on the symlinks having been created before.

Mailing list thread: https://lists.llvm.org/pipermail/llvm-dev/2021-July/151822.html

Reviewed By: thakis, steven_wu

Differential Revision: https://reviews.llvm.org/D106305
The file was modifiedcompiler-rt/cmake/Modules/CompilerRTDarwinUtils.cmake
The file was modifiedcompiler-rt/lib/builtins/CMakeLists.txt
Commit 14e356d121cd3f49a1f78f67a5b2e605c7d063f6 by craig.topper
[TypePromotion] Remove redundant if. NFC

The same condition was checked in the previous if. Maybe this was
a bad merge resolution?
The file was modifiedllvm/lib/CodeGen/TypePromotion.cpp
Commit b0402a35fc882ad582ddf128833e531cf2b7f657 by michael.hliao
[amdgpu] Add 64-bit PC support when expanding unconditional branches.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D106445
The file was modifiedllvm/test/MC/AMDGPU/expressions.s
The file was modifiedllvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.h
The file was modifiedllvm/test/CodeGen/AMDGPU/branch-relaxation-gfx10-branch-offset-bug.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/branch-relaxation.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/branch-relaxation-debug-info.mir
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.cpp
The file was addedllvm/test/MC/AMDGPU/offset-expr.s
The file was modifiedllvm/test/CodeGen/AMDGPU/branch-relax-bundle.ll
Commit 0fb16d5ad126a14213ceee6b20b86c721ea49d4e by efriedma
Fix clang regression test after 5c486ce0
The file was modifiedclang/test/CodeGenOpenCL/convergent.cl
Commit 069428b6f73bdfb7bba13d461a2f57beb86b6aa7 by Louis Dionne
[libc++] Set the target triple by default in the standalone build

Even though the standalone build is deprecated, some people are still
relying on it (including libc++ itself for some configurations). Setting
the target triple will ensure that the build and the test suite behaves
consistently in the standalone and normal builds.

Differential Revision: https://reviews.llvm.org/D106800
The file was modifiedlibcxx/utils/libcxx/test/dsl.py
The file was modifiedlibcxx/utils/libcxx/test/params.py
The file was modifiedlibcxx/cmake/Modules/HandleOutOfTreeLLVM.cmake
Commit 7b28c5d3765c5f48a1502693331b22330d609f88 by Louis Dionne
[libc++] Implement the output_iterator and output_range concepts

Differential Revision: https://reviews.llvm.org/D106704
The file was modifiedlibcxx/include/iterator
The file was modifiedlibcxx/include/ranges
The file was addedlibcxx/test/std/iterators/iterator.requirements/iterator.concepts/iterator.concept.output/output_iterator.compile.pass.cpp
The file was addedlibcxx/test/std/ranges/range.req/range.refinements/output_range.compile.pass.cpp
The file was modifiedlibcxx/docs/Status/RangesPaper.csv
The file was modifiedlibcxx/include/__iterator/concepts.h
The file was modifiedlibcxx/include/__ranges/concepts.h
Commit e757a3b05fd99bb5b5e6460c1d59cd0a170a6033 by huberjn
[OpenMP][NFC] Remove unncessary capture in RAII struct

Summary:
There was an unnecessary variable assigned to the information cache when we
only need it in the constructor to extract the function declaration.
The file was modifiedllvm/lib/Transforms/IPO/OpenMPOpt.cpp
Commit 2d788959edda2155398ed760d19aee84259ed814 by lei
[PowerPC] Add implicit-def RM to instructions mtfsb[01]

This is a followup patch for D105930 to add implicit-def of RM for
mtfsb[01] instructions as per review comments.

Reviewed By: nemanjai

Differential Revision: https://reviews.llvm.org/D106603
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrInfo.td
The file was modifiedllvm/test/CodeGen/PowerPC/2008-10-28-f128-i32.ll
Commit 323049329939becf690adbeeff9f5f7e219075ec by rnk
Fix clang debug info irgen of i128 enums

DIEnumerator stores an APInt as of April 2020, so now we don't need to
truncate the enumerator value to 64 bits. Fixes assertions during IRGen.

Split from D105320, thanks to Matheus Izvekov for the test case and
report.

Differential Revision: https://reviews.llvm.org/D106585
The file was modifiedllvm/include/llvm/IR/DIBuilder.h
The file was addedclang/test/CodeGenCXX/debug-info-enum-i128.cpp
The file was modifiedllvm/lib/IR/DIBuilder.cpp
The file was modifiedclang/lib/CodeGen/CGDebugInfo.cpp
Commit d56e6985528bae0305c1633fd8db1658d1b28356 by rnk
[SimplifyCFG] Remove stale comment after d7378259aa, NFC
The file was modifiedllvm/lib/Transforms/Utils/SimplifyCFG.cpp
Commit e42edce4a349efeedde2ffd07a26a6335178d24b by apl
[lldb][NFC] Delete unused and commented out DWARF constants

I cannot find any users of these anywhere and they have been commented out
for years.
The file was modifiedlldb/include/lldb/Core/dwarf.h
The file was modifiedlldb/packages/Python/lldbsuite/test/lldbdwarf.py
Commit e745277012ec05d1e6f980e05f2a3ea7c827eeec by sander.desmalen
[AArch64] NFC: Make some AArch64-SVE LoopVectorize tests generic.

This change moves most of `sve-inductions.ll` to non-AArch64 specific
LV tests using the `-target-supports-scalable-vectors` flag, because they're
not explicitly AArch64-specific. One test builds on AArch64-specific
knowledge regarding masked loads/stores, and remains in sve-inductions.ll.
The file was addedllvm/test/Transforms/LoopVectorize/scalable-inductions.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/AArch64/sve-inductions.ll
Commit 13ccb097258a244498aa760b878a23de721af29f by sander.desmalen
[LV] Don't let ForceTargetInstructionCost override Invalid cost.

Invalid costs can be used to avoid vectorization with a given VF, which is
used for scalable vectors to avoid things that the code-generator cannot
handle. If we override the cost using the -force-target-instruction-cost
option of the LV, we would override this mechanism, rendering the flag useless.

This change ensures the cost is only overriden when the original cost that
was calculated is valid. That allows the flag to be used in combination
with the -scalable-vectorization option.

Reviewed By: david-arm

Differential Revision: https://reviews.llvm.org/D106677
The file was modifiedllvm/test/Transforms/LoopVectorize/AArch64/scalable-call.ll
The file was modifiedllvm/lib/Transforms/Vectorize/LoopVectorize.cpp
Commit 64a15817a01703ea2206dd02f27a166ea1890ecb by lei
[PowerPC]Add addex instruction definition and MC tests

Add td definitions and asm/disasm tests for the addex instruction introduced in
ISA 3.0.

Reviewed By: nemanjai, amyk, NeHuang

Differential Revision: https://reviews.llvm.org/D106666
The file was modifiedllvm/test/MC/Disassembler/PowerPC/ppc64le-encoding.txt
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrFormats.td
The file was modifiedllvm/lib/Target/PowerPC/P9InstrResources.td
The file was modifiedllvm/test/MC/Disassembler/PowerPC/ppc64-encoding.txt
The file was modifiedllvm/test/MC/PowerPC/ppc64-encoding.s
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrInfo.td
Commit d0c7d4d8a06679a9f306855f4abf1df0bab41dd1 by david.green
[ARM] Fixup vst4 test. NFC
The file was modifiedllvm/test/CodeGen/Thumb2/mve-vst4.ll
Commit dead50d4427cbdd5f41c02c5441270822f702730 by jhuber6
[OpenMP][NFC] Fix a few typos in OpenMP documentation

Summary:
Fixes some typos in the OpenMP documentation.
The file was modifiedopenmp/docs/remarks/OMP112.rst
The file was modifiedopenmp/docs/remarks/OMP113.rst
The file was modifiedopenmp/docs/remarks/OMP131.rst
The file was modifiedopenmp/docs/remarks/OMP120.rst
The file was modifiedopenmp/docs/remarks/OMP160.rst
The file was modifiedopenmp/docs/remarks/OMP110.rst
The file was modifiedopenmp/docs/remarks/OMP111.rst
Commit f84c70a3793909ec16b3e53a502f0f9ea99c6af3 by mizvekov
[CodeView] Saturate values bigger than supported by APInt.

This fixes an assert firing when compiling code which involves 128 bit
integrals.

This would trigger runtime checks similar to this:
```
Assertion failed: getMinSignedBits() <= 64 && "Too many bits for int64_t", file llvm/include/llvm/ADT/APInt.h, line 1646
```

To get around this, we just saturate those big values.

Reviewed By: rnk

Differential Revision: https://reviews.llvm.org/D105320
The file was modifiedllvm/include/llvm/IR/DIBuilder.h
The file was modifiedllvm/lib/CodeGen/AsmPrinter/CodeViewDebug.h
The file was modifiedllvm/lib/IR/DIBuilder.cpp
The file was modifiedllvm/lib/DebugInfo/CodeView/CodeViewRecordIO.cpp
The file was modifiedllvm/lib/CodeGen/AsmPrinter/CodeViewDebug.cpp
The file was addedllvm/test/DebugInfo/COFF/integer-128.ll
The file was modifiedllvm/include/llvm/ADT/APInt.h
Commit 20555a15a596012ef827e29b665db53a4fc0b86c by mizvekov
[clang] P2266 implicit moves STL workaround

This patch replaces the workaround for simpler implicit moves
implemented in D105518.

The Microsoft STL currently has some issues with P2266.

Where before, with -fms-compatibility, we would disable simpler
implicit moves globally, with this change, we disable it only
when the returned expression is in a context contained by
std namespace and is located within a system header.

Signed-off-by: Matheus Izvekov <mizvekov@gmail.com>

Reviewed By: aaron.ballman, mibintc

Differential Revision: https://reviews.llvm.org/D105951
The file was modifiedclang/lib/Sema/SemaCoroutine.cpp
The file was modifiedclang/test/SemaCXX/cxx2b-p2266-disable-with-msvc-compat.cpp
The file was modifiedclang/lib/Frontend/InitPreprocessor.cpp
The file was modifiedclang/include/clang/Sema/Sema.h
The file was modifiedclang/lib/Sema/SemaStmt.cpp
Commit 7c5f104e4549ed13c41a61429423ab03d958878e by lebedev.ri
[SimplifyCFG] Drop support for duplicating ret's into uncond predecessors

This functionality existed only under a default-off flag,
and simplifycfg nowadays prefers to not increase the count of ret's.
The file was removedllvm/test/Transforms/SimplifyCFG/duplicate-ret-into-uncond-br.ll
The file was modifiedllvm/test/Transforms/SimplifyCFG/merge-duplicate-conditional-ret-val.ll
The file was modifiedllvm/lib/Transforms/Utils/SimplifyCFG.cpp
The file was modifiedllvm/test/Transforms/SimplifyCFG/return-merge.ll
Commit 08efc2e68d5f9fe522fe8d70d0bd5ddf45f78848 by lebedev.ri
[SimplifyCFG] Drop support for simplifying cond branch to two (different) ret's

Nowadays, simplifycfg pass already tail-merges all the ret blocks together
before doing anything, and it should not increase the count of ret's,
so this is dead code.
The file was modifiedllvm/lib/Transforms/Utils/SimplifyCFG.cpp
Commit 1901c98dd81bded0b95b2a1c0de05d56c24e7408 by lebedev.ri
[SimplifyCFG] SwitchToLookupTable(): don't increase ret count

The very next SimplifyCFG pass invocation will tail-merge these two ret's
anyways, there is not much point in creating more work for ourselves.
The file was modifiedllvm/test/Transforms/PhaseOrdering/X86/simplifycfg-late.ll
The file was modifiedllvm/test/Transforms/SimplifyCFG/X86/switch_to_lookup_table.ll
The file was modifiedllvm/test/Transforms/SimplifyCFG/X86/disable-lookup-table.ll
The file was modifiedllvm/lib/Transforms/Utils/SimplifyCFG.cpp
The file was modifiedllvm/test/Transforms/SimplifyCFG/Hexagon/switch-to-lookup-table.ll
The file was modifiedllvm/test/Transforms/SimplifyCFG/rangereduce.ll
Commit cbad57613e769d0653e13cf877d80eae421b2314 by llvm-project
[flang][msvc] Fix external-io unittest.

Fix the external-io unittest under Windows.

In particular, fixes the following issues:

1.  When creating a temporary file, open it with read+write permissions
     using the _O_RDWR flag. _S_IREAD and _S_IWRITE are for the file
     permissions of the created file.

2. _chsize returns 0 on success (just like ftruncate).

3. To set a std::optional, use its assign-operator overload instead of
    getting a reference to its value and overwrite that. The latter is
    invalid if the std::optional has no value, and is caught by
    msvc's debug STL.

The non-GTest unittest is currently not executed under Windows because
of the added .exe extension to the output file: external-io.text.exe.
llvm-lit skips the file because .exe is not in the lists of test
suffixes (.test is). D105315 is going to change that by converting it
to a GTest-test.

Reviewed By: awarzynski

Differential Revision: https://reviews.llvm.org/D106726
The file was modifiedflang/runtime/file.cpp
The file was modifiedflang/runtime/unit.cpp
Commit d2972116923a124de71cea006eca3068bdc381ea by huberjn
[OpenMP] Add a driver flag to enable the new device runtime library

This patch adds a driver flag `-fopenmp-target-new-runtime` to optionally enable the new device runtime
bitcode library. This allows users to enable the new experimental runtime
before it becomes the default in the future.

Reviewed By: jdoerfert

Differential Revision: https://reviews.llvm.org/D106793
The file was modifiedclang/include/clang/Basic/LangOptions.def
The file was modifiedclang/include/clang/Driver/Options.td
The file was modifiedclang/lib/Driver/ToolChains/Cuda.cpp
The file was modifiedclang/test/Driver/openmp-offload-gpu.c
The file was addedclang/test/Driver/Inputs/libomptarget/libomptarget-new-nvptx-sm_35.bc
The file was modifiedclang/lib/Driver/ToolChains/AMDGPUOpenMP.cpp
Commit e95cd94f7edf50367d650410b8e534342eb0e5cb by Louis Dionne
[libc++abi/unwind] NFC: Normalize how we set target properties

This is a NFC commit to normalize how we set target properties on the
various runtime targets. A follow-up patch is going to add new properties,
and I wanted that follow-up patch to be cleaner.
The file was modifiedlibunwind/src/CMakeLists.txt
The file was modifiedlibcxxabi/src/CMakeLists.txt
Commit 25666a74c5af05ae6b189ad4f7382d351fb8698f by arthur.j.odwyer
[libc++] Remove "pass by const value" in <random>. NFCI.
The file was modifiedlibcxx/include/random
Commit 41b17c444df647ce46609d8efb57a98d35704c63 by arthur.j.odwyer
[libc++] Fix signed overflow inside ranges::advance.

See LWG reflector thread of 2021-07-23 titled
'Question on ranges::advance and "past-the-sentinel iterators"'.
Test case heavily based on one graciously provided by Casey Carter.

Differential Revision: https://reviews.llvm.org/D106735
The file was modifiedlibcxx/include/__iterator/advance.h
The file was modifiedlibcxx/test/std/iterators/iterator.primitives/range.iter.ops/range.iter.ops.advance/iterator_count_sentinel.pass.cpp
Commit c285a11efdb0821e6be9fcef695097890f44aa03 by aheejin
[WebAssembly] Make Emscripten EH work with Emscripten SjLj

When Emscripten EH mixes with Emscripten SjLj, we are not currently
handling some of them correctly. There are three cases:
1. The current function calls `setjmp` and there is an `invoke` to a
   function that can either throw or longjmp. In this case, we have to
   check both for exception and longjmp. We are currently handling this
   case correctly:
   https://github.com/llvm/llvm-project/blob/0c0eb76782d5224b8d81a5afbb9a152bcf7c94c7/llvm/lib/Target/WebAssembly/WebAssemblyLowerEmscriptenEHSjLj.cpp#L1058-L1090
   When inserting routines for functions that can longjmp, which we do
   only for setjmp-calling functions, we check if the function was
   previously an `invoke` and handle it correctly.

2. The current function does NOT call `setjmp` and there is an `invoke`
   to a function that can either throw or longjmp. Because there is no
   `setjmp` call, we haven't been doing any check for functions that can
   longjmp. But in that case, for `invoke`, we only check for an
   exception and if it is not an exception we reset `__THREW__` to 0,
   which can silently swallow the longjmp:
   https://github.com/llvm/llvm-project/blob/0c0eb76782d5224b8d81a5afbb9a152bcf7c94c7/llvm/lib/Target/WebAssembly/WebAssemblyLowerEmscriptenEHSjLj.cpp#L70-L80
   This CL fixes this.

3. The current function calls `setjmp` and there is no `invoke`. Because
   it is not an `invoke`, we haven't been doing any check for functions
   that can throw, and only insert longjmp-checking routines for
   functions that can longjmp. But in that case, if a longjmpable
   function throws, we only check for a longjmp so if it is not a
   longjmp we reset `__THREW__` to 0, which can silently swallow the
   exception:
   https://github.com/llvm/llvm-project/blob/0c0eb76782d5224b8d81a5afbb9a152bcf7c94c7/llvm/lib/Target/WebAssembly/WebAssemblyLowerEmscriptenEHSjLj.cpp#L156-L169
   This CL fixes this.

To do that, this moves around some code, so we register necessary
functions for both EH and SjLj and precompute some data (the set of
functions that contains `setjmp`) before doing actual EH or SjLj
transformation.

This CL makes 2nd and 3rd tests in
https://github.com/emscripten-core/emscripten/pull/14732 work.

Reviewed By: dschuff

Differential Revision: https://reviews.llvm.org/D106525
The file was modifiedllvm/lib/Target/WebAssembly/WebAssemblyLowerEmscriptenEHSjLj.cpp
The file was modifiedllvm/test/CodeGen/WebAssembly/lower-em-sjlj.ll
The file was modifiedllvm/lib/Target/WebAssembly/WebAssembly.h
The file was addedllvm/test/CodeGen/WebAssembly/lower-em-ehsjlj.ll
Commit fed25ddc1c3de59aa1de27e95b349f86896ccb79 by gclayton
[LLDB][GUI] Expand selected thread tree item by default

This patch expands the tree item that corresponds to the selected thread
by default in the Threads window. Additionally, the tree root item is
always expanded, which is the process in the Threads window.

Reviewed By: clayborg

Differential Revision: https://reviews.llvm.org/D100243
The file was addedlldb/test/API/commands/gui/expand-threads-tree/Makefile
The file was addedlldb/test/API/commands/gui/expand-threads-tree/TestGuiExpandThreadsTree.py
The file was modifiedlldb/source/Core/IOHandlerCursesGUI.cpp
The file was addedlldb/test/API/commands/gui/expand-threads-tree/main.c
Commit ed5b4dbd3952ffa8970ae59faa7f7505cd28aa92 by gclayton
[LLDB][GUI] Add Arch Field

This patch adds an Arch field that inputs and validates an arch spec.

Differential Revision: https://reviews.llvm.org/D106564
The file was modifiedlldb/source/Core/IOHandlerCursesGUI.cpp
Commit af000197c4214926bd7d0862d86f89aed5f20da6 by huberjn
[OpenMP] Always inline the OpenMP outlined function

This patch adds the always inline attribute to the outlined functions generated
by OpenMP regions. Because there is only a single instance of this function and
it always has internal linkage it is safe to inline in every instance it is
created. This could potentially lead to performance degredation due to
inflated register counts in the parallel region.

Reviewed By: jdoerfert

Differential Revision: https://reviews.llvm.org/D106799
The file was modifiedclang/test/OpenMP/nvptx_target_parallel_reduction_codegen_tbaa_PR46146.cpp
The file was modifiedclang/lib/CodeGen/CGStmtOpenMP.cpp
Commit a48ee9f25581d0d6cbf2b1205777e7d53023797f by aheejin
[WebAssembly] Remove dominator dependency in WasmEHPrepare (NFC)

Dominator trees were previously used for an optimization related to
`wasm.lsda` but the optimization was removed in D97309. Currently
dominators are not doing anything in this pass. Also removes some
`include` lines without which it compiles.

Reviewed By: tlively

Differential Revision: https://reviews.llvm.org/D106811
The file was modifiedllvm/lib/CodeGen/WasmEHPrepare.cpp
Commit c658b472f3e61e1818e1909bf02f3d65470018a5 by Amara Emerson
[GlobalISel] Add a constant folding combine.

Use it AArch64 post-legal combiner. These don't always get folded because when
the instructions are created the constants are obscured by artifacts.

Differential Revision: https://reviews.llvm.org/D106776
The file was modifiedllvm/lib/Target/AArch64/AArch64Combine.td
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic-128.ll
The file was modifiedllvm/test/CodeGen/AArch64/fold-global-offsets.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/urem.i32.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i32.ll
The file was modifiedllvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
The file was modifiedllvm/include/llvm/Target/GlobalISel/Combine.td
The file was addedllvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-constant-fold.mir
Commit 8f41431654fedac4a5ad2751056a611bfc7751f0 by psteinfeld
[flang] Disallow BOZ literal constants as arguments of implicit interfaces

Since BOZ literal arguments are typeless, we cannot know how to pass them as
actual arguments to procedures with implicit interfaces.  This change avoids
the problem by emitting an error message in such situations.

This change stemmed from the following issue --
  https://github.com/flang-compiler/f18-llvm-project/issues/794

Differential Revision: https://reviews.llvm.org/D106831
The file was modifiedflang/test/Semantics/boz-literal-constants.f90
The file was modifiedflang/lib/Semantics/check-call.cpp
Commit c5d8bd5a35cbd325c6ccd42afa91bad06d261f07 by i
[llvm-objcopy] Fix section group flag read/write when operating on a cross-endian object file
The file was modifiedllvm/tools/llvm-objcopy/ELF/Object.cpp
Commit 172051a1f4b1a007a2dbc46f8efb5e650b016d3b by Amara Emerson
[AArch64][GlobalISel] Add identity combines to post-legal combiner.

We see some shifts of zero emitted during legalization.

Differential Revision: https://reviews.llvm.org/D106816
The file was modifiedllvm/test/CodeGen/AArch64/fold-global-offsets.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64Combine.td
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic-128.ll
The file was addedllvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-identity.mir
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/postlegalizercombiner-select.mir
Commit 1e1b5706c3f5e24b937878e592cf9907af368ec3 by arthur.j.odwyer
[libc++] Fix spacing in <vector>. NFCI.

Thanks to gAlfonso-bit for the patch!

Differential Revision: https://reviews.llvm.org/D106691
The file was modifiedlibcxx/include/vector
Commit 58aa3881bac60a497168449b9087e3ebef85a3d8 by jurahul
[MLIR][SCF][NFC] Fix typo in documentation of scf.while

- `scf.yield` in the "after" region supplies new arguments to the "before" region.

Differential Revision: https://reviews.llvm.org/D106806
The file was modifiedmlir/include/mlir/Dialect/SCF/SCFOps.td
Commit b50fb58695b4fa2b60e0003980b158a717638180 by leonardchan
[compiler-rt][hwasan][fuchsia] Define shadow bound globals

These are required by MemIsShadow for checking if an address actually is shadow memory.

Differential Revision: https://reviews.llvm.org/D105745
The file was modifiedcompiler-rt/lib/hwasan/hwasan_fuchsia.cpp
Commit 3c3269559ba9400224400b96c22b31812638de52 by mgorny
[lldb] [gdb-remote client] Avoid zero padding PID/TID in H packet

Change SetCurrentThread*() logic not to include the zero padding
in PID/TID that was a side effect of 02ef0f5ab483.  This should fix
problems caused by sending 64-bit integers to 32-bit servers.  Reported
by Ted Woodward.

Differential Revision: https://reviews.llvm.org/D106832
The file was modifiedlldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp
The file was modifiedlldb/unittests/Process/gdb-remote/GDBRemoteCommunicationClientTest.cpp
Commit a9b114c5dd68685e0e68dd9144454b44509c2f5f by rnk
Disable the new enum i128 test under ASan, it uncovers an existing leak

See llvm.org/pr51221
The file was modifiedclang/test/CodeGenCXX/debug-info-enum-i128.cpp
Commit 71af002d151ef9a162c8a776c22b46893f923af0 by leonardchan
[compiler-rt][hwasan][fuchsia] Implement InitializeOsSupport

This is empty for now, but we will add a check that TBI is enabled once the
tagged pointer ABI for zircon is finalized. This depends on D105667.

Differential Revision: https://reviews.llvm.org/D105668
The file was modifiedcompiler-rt/lib/hwasan/hwasan_fuchsia.cpp
Commit beff86e8ff429f11da6fe37efde86d22ea636ed5 by joker.eph
Build libSupport with -Werror=global-constructors (NFC)

Ensure that libSupport does not carry any static global initializer.
libSupport can be embedded in use cases where we don't want to load all
cl::opt unless we want to parse the command line.
ManagedStatic can be used to enable lazy-initialization of globals.

The -Werror=global-constructors is only added on platform that have
support for the flag and for which std::mutex does not have a global
destructor. This is ensured by having CMake trying to compile a file
with a global mutex before adding the flag to libSupport.
The file was modifiedllvm/lib/Support/CMakeLists.txt
Commit f9f56488e02d1c09a9cd4acde61ce1c712e71405 by rnk
[DebugInfo] Use per-enumerator signedness for DIEnumerator

Allegedly the DWARF backend ignores this field of DIEnumerator, but we
set it nonetheless in case we decide to use it in the future.
Alternatively, we could remove it, but it is simpler to pass down the
signed bit as it is in the AST for now.

Implemented to address comments on D106585
The file was modifiedclang/test/CodeGen/enum2.c
The file was modifiedclang/lib/CodeGen/CGDebugInfo.cpp
Commit 45951ad3231c213e7fae384dc9ce803bfaed8c77 by msd.ataei
[PowerPC] Add pwr7 and pwr10 support to IBM MASSV pass on AIX

Before MASSV only supported P8 and P9 on AIX ans Linux . This patch proposes
MASSV to add support of P7 and P10 only on AIX too.

Differential: https://reviews.llvm.org/D106678
The file was modifiedllvm/test/Transforms/LoopVectorize/PowerPC/massv-unsupported.ll
The file was modifiedllvm/test/CodeGen/PowerPC/lower-massv.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/PowerPC/massv-nobuiltin.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/PowerPC/widened-massv-call.ll
The file was modifiedllvm/test/CodeGen/PowerPC/pow_massv_075_025exp.ll
The file was modifiedllvm/lib/Target/PowerPC/PPCLowerMASSVEntries.cpp
The file was modifiedllvm/test/CodeGen/Generic/replace-intrinsics-with-veclib.ll
The file was modifiedllvm/test/CodeGen/PowerPC/lower-massv-attr.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/PowerPC/massv-altivec.ll
The file was modifiedllvm/test/Transforms/Util/add-TLI-mappings.ll
The file was modifiedllvm/test/CodeGen/PowerPC/powf_massv_075_025exp.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/PowerPC/massv-calls.ll
The file was modifiedllvm/include/llvm/Analysis/VecFuncs.def
Commit b49a3bf7c094d7c76eb8a4774ae9aded84dafa41 by leonardchan
[compiler-rt][hwasan][fuchsia] Implement TagMemoryAligned for fuchsia

This will just be a call into __sanitizer_fill_shadow defined in the fuchsia source tree. This depends on D105663.

Differential Revision: https://reviews.llvm.org/D105664
The file was modifiedcompiler-rt/lib/hwasan/hwasan_fuchsia.cpp
Commit 97e95fea53fc403c2a12e356dc835fc922123575 by jonathan_roelofs
[AArch64][GlobalISel] Legalize ctpop s128

Differential revision: https://reviews.llvm.org/D106494
The file was modifiedllvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
The file was modifiedllvm/test/CodeGen/AArch64/popcount.ll
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/legalize-ctpop.mir
Commit c7b3a91017d26266d7556b1ac7c49b06f0109b91 by tstellar
libclang.so: Make SONAME independent from LLVM version

Reviewed By: MaskRay

Differential Revision: https://reviews.llvm.org/D105527
The file was addedclang/tools/libclang/linker-script-to-export-list.py
The file was addedclang/test/LibClang/lit.local.cfg
The file was modifiedclang/test/CMakeLists.txt
The file was modifiedclang/test/lit.site.cfg.py.in
The file was addedclang/test/LibClang/symbols.test
The file was removedclang/tools/libclang/libclang.exports
The file was modifiedclang/tools/libclang/CMakeLists.txt
The file was addedclang/tools/libclang/libclang.map
Commit f82f39b9cfc9a807380ebb2348c1cf16610e1e87 by listmail
[SCEV] Add a comment about invariant in howManyLessThans
The file was modifiedllvm/lib/Analysis/ScalarEvolution.cpp
Commit 18526b0d661f28e79cb70bfd712cedf9e7085154 by albionapc
[PowerPC] Changed sema checking range for tdw td builtin

To match xlc behaviour and definition in the PowerPC ISA3.1,
it is a better idea to have ibm-clang produce an error when a
0 is passed to the builtin, which will match xlc's behaviour.
This patch changes the accepted range from 0 to 31 to 1 to 31.

Differential revision: https://reviews.llvm.org/D106817
The file was modifiedclang/lib/Sema/SemaChecking.cpp
The file was modifiedclang/test/CodeGen/builtins-ppc-xlcompat-error.c
Commit 69daca022ad71f5f697008e0b028c52023abe61b by tstellar
libclang.so: Fix version script to work with gold

The changes made in 0cf37a3b0617457daaed3224373ffa07724f8482 are not
compatible with gold, which does not seem to support a symbol version
with the name local.
The file was modifiedclang/tools/libclang/libclang.map
Commit 0a37163d1d855a2db41e1f46ddbc3f4570bd7ca6 by Jessica Paquette
[GlobalISel] Add scalar widening for G_MERGE_VALUES destination

This adds support for the case where

WideSize = DstSize + K * SrcSize

In this case, we can pad the G_MERGE_VALUES instruction with K extra undef
values with width SrcSize. Then the destination can be handled via
widenScalarDst.

Differential Revision: https://reviews.llvm.org/D106814
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/legalize-merge-values.mir
The file was modifiedllvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
Commit 0d7596c348842af2c34b13cfd9e5b3480e6c8b0e by tstellar
libclang: Add missing export to python script that generates export list

This script was added in 0cf37a3b0617457daaed3224373ffa07724f8482.
The file was modifiedclang/tools/libclang/linker-script-to-export-list.py
Commit f2e8e46d7863b41cc3d839e04da4c61a4ac28853 by jonathan_roelofs
Revert "[AArch64][GlobalISel] Legalize ctpop s128"

This reverts commit 97e95fea53fc403c2a12e356dc835fc922123575.

It broke test/CodeGen/Mips/GlobalISel/llvm-ir/ctpop.ll. Not sure why I didn't see that.
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/legalize-ctpop.mir
The file was modifiedllvm/test/CodeGen/AArch64/popcount.ll
The file was modifiedllvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
Commit d425f58939ad9ef88ee2d1578a87c25d4e121128 by jpienaar
[mlir] Make ValueShapeRange a new class

Retaining old interface and should be constructable as previous, change would have been NFC except it this doesn't implicitly work with OpAdaptor generated in C++14.

Differential Revision: https://reviews.llvm.org/D106772
The file was modifiedmlir/include/mlir/Interfaces/InferTypeOpInterface.h
The file was modifiedmlir/test/lib/Dialect/Test/TestDialect.cpp
The file was modifiedmlir/lib/Dialect/Tosa/IR/TosaOps.cpp
Commit 86778e8b3036d95e684edef469495110f1c2f121 by jurahul
[MLIR][NFC] Rework some comments.

Differential Revision: https://reviews.llvm.org/D106834
The file was modifiedmlir/include/mlir/Interfaces/ControlFlowInterfaces.h
The file was modifiedmlir/include/mlir/Analysis/AliasAnalysis/LocalAliasAnalysis.h
The file was modifiedmlir/include/mlir/Interfaces/ControlFlowInterfaces.td
The file was modifiedmlir/include/mlir/Analysis/DataFlowAnalysis.h
Commit c7b7638dfee54053553d9b22eeb8912ca42a06ec by jianzhouzh
[dfsan][NFC] Add compile flags and environment variables to doc

Reviewed By: gbalats

Differential Revision: https://reviews.llvm.org/D106833
The file was modifiedclang/docs/DataFlowSanitizer.rst
Commit 1a3bf2953a9209fdc4dbb6e99678e02a7fec019d by akhuang
[DebugInfo] Switch to using constructor homing (-debug-info-kind=constructor) by default when debug info is enabled

Constructor homing reduces the amount of class type info that is emitted
by emitting conmplete type info for a class only when a constructor for
that class is emitted.

This will mainly reduce the amount of duplicate debug info in object
files. In Chrome enabling ctor homing decreased total build directory sizes
by about 30%.

It's also expected that some class types (such as unused classes)
will no longer be emitted in the debug info. This is fine, since we wouldn't
expect to need these types when debugging.

In some cases (e.g. libc++, https://reviews.llvm.org/D98750), classes
are used without calling the constructor. Since this is technically
undefined behavior, enabling constructor homing should be fine.
However Clang now has an attribute
`__attribute__((standalone_debug))` that can be used on classes to
ignore ctor homing.

Bug: https://bugs.llvm.org/show_bug.cgi?id=46537

Differential Revision: https://reviews.llvm.org/D106084
The file was modifiedclang/test/Driver/myriad-toolchain.c
The file was modifiedclang/test/Driver/debug-options.c
The file was modifiedclang/test/Driver/debug-options-as.c
The file was modifiedclang/test/Driver/integrated-as.s
The file was modifiedclang/lib/Driver/ToolChains/Clang.cpp
The file was modifiedclang/test/Driver/clang-g-opts.c
The file was modifiedclang/test/Driver/cl-options.c
The file was modifiedlldb/test/Shell/SymbolFile/PDB/Inputs/ClassLayoutTest.cpp
The file was modifiedclang/include/clang/Basic/DebugInfoOptions.h
The file was modifiedclang/test/Driver/openmp-offload-gpu.c
The file was modifiedclang/test/Driver/split-debug.c
The file was modifiedclang/test/CodeGenCXX/debug-info-template-deduction-guide.cpp
The file was modifiedclang/test/Driver/cuda-dwarf-2.cu
Commit e69a8c42135606e60446d5e78144357a9e429c77 by jianzhouzh
[dfsan] Fix doc build errors
The file was modifiedclang/docs/DataFlowSanitizer.rst
Commit 9654cfd5bb20926bcaf601b5da1707bcd280e37f by lei
[PowerPC] Fix materialization of SP float values on Power10

All floating point values in registers are in double precision
representation. In order to materialize the correct single precision
value, we need to convert the APFloat that represents the value
to double precision first.

Reviewed By: amyk, NeHuang

Differential Revision: https://reviews.llvm.org/D106812
The file was modifiedllvm/test/CodeGen/PowerPC/p10-splatImm-CPload-pcrel.ll
The file was modifiedllvm/lib/Target/PowerPC/PPCInstrInfo.td
The file was modifiedllvm/test/CodeGen/PowerPC/constant-pool.ll
Commit c1b4632528cb405c9ef94cff90bf43afe688a899 by walter erquinigo
[trace] Add the definition of a TraceExporter plugin

Copying from the inline documentation:

```
Trace exporter plug-ins operate on traces, converting the trace data provided by an \a lldb_private::TraceCursor into a different format that can be digested by other tools, e.g. Chrome Trace Event Profiler.
Trace exporters are supposed to operate on an architecture-agnostic fashion, as a TraceCursor, which feeds the data, hides the actual trace technology being used.
```

I want to use this to make the code in https://reviews.llvm.org/D105741 a plug-in. I also imagine that there will be more and more exporters being implemented, as an exporter creates something useful out of trace data. And tbh I don't want to keep adding more stuff to the lldb/Target folder.

This is the minimal definition for a TraceExporter plugin. I plan to use this with the following commands:

- thread trace export <plug-in name> [plug-in specific args]
  - This command would support autocompletion of plug-in names
- thread trace export list
  - This command would list the available trace exporter plug-ins

I don't plan to create yet a "process trace export" because it's easier to start analyzing the trace of a given thread than of the entire process. When we need a process-level command, we can implement it.

I also don't plan to force each "export" command implementation to support multiple threads (for example, "thread trace start 1 2 3" or "thread trace start all" operate on many threads simultaneously). The reason is that the format used by the exporter might or might not support multiple threads, so I'm leaving this decision to each trace exporter plug-in.

Differential Revision: https://reviews.llvm.org/D106501
The file was addedlldb/include/lldb/Target/TraceExporter.h
The file was addedlldb/source/Plugins/TraceExporter/ctf/TraceExporterCTFOptions.td
The file was modifiedlldb/include/lldb/Core/PluginManager.h
The file was addedlldb/source/Plugins/TraceExporter/ctf/TraceExporterCTF.cpp
The file was modifiedlldb/include/lldb/lldb-forward.h
The file was modifiedlldb/source/Commands/CommandObjectThread.cpp
The file was modifiedlldb/source/Plugins/CMakeLists.txt
The file was addedlldb/source/Plugins/TraceExporter/ctf/TraceExporterCTF.h
The file was modifiedlldb/source/Core/PluginManager.cpp
The file was addedlldb/source/Plugins/TraceExporter/ctf/CommandObjectThreadTraceExportCTF.h
The file was addedlldb/source/Plugins/TraceExporter/ctf/CommandObjectThreadTraceExportCTF.cpp
The file was modifiedlldb/include/lldb/lldb-private-interfaces.h
The file was addedlldb/source/Target/TraceExporter.cpp
The file was addedlldb/source/Plugins/TraceExporter/CMakeLists.txt
The file was modifiedlldb/source/Target/CMakeLists.txt
The file was addedlldb/source/Plugins/TraceExporter/ctf/CMakeLists.txt
Commit 2f49eb47946ae1906b8d347fc3ee387bded5439a by joker.eph
Revert "Build libSupport with -Werror=global-constructors (NFC)"

This reverts commit beff86e8ff429f11da6fe37efde86d22ea636ed5.

The sanitizer-x86_64-linux bot is still broken.
The file was modifiedllvm/lib/Support/CMakeLists.txt
Commit 9563f3b571d1dc1f40a546a86c11904b1748ff86 by cjdb
[libcxx][NFC] adjusts 41b17c44 so it meets requested feedback

Feedback requested in D106735 applied in Diff 3 seem to have
reverted in Diff 4. This patch fixes that up.

Differential Revision: https://reviews.llvm.org/D106829
The file was modifiedlibcxx/include/__iterator/advance.h
Commit fbaa35e169474c5ad2e211fdc1ec74f8e56546ab by carl.ritson
[AMDGPU] Add SelectionDAG support for insert_subvector on v4f64

Enable custom insert_subvector for larger vector types.
This is necessary now that SelectionDAG can attempt v3f64 insert
to v4f64, etc.

Reviewed By: foad

Differential Revision: https://reviews.llvm.org/D105385
The file was modifiedllvm/lib/Target/AMDGPU/SIISelLowering.cpp
The file was addedllvm/test/CodeGen/AMDGPU/bug-v4f64-subvector.ll
Commit 0300e16eb0a8e7bd980b6b14b6a3bae38786651d by tstellar
libclang: Fixes for the python script that generates the export list

This script was added in 0cf37a3b0617457daaed3224373ffa07724f8482.
The file was modifiedclang/tools/libclang/linker-script-to-export-list.py
The file was modifiedclang/tools/libclang/CMakeLists.txt
Commit 494f1e6706481ec49942c07ebf48697872919612 by jianzhouzh
[dfsan][NFC] Fix doc format
The file was modifiedclang/docs/DataFlowSanitizer.rst
Commit e30293352c98e6985480d6d77b60675becbdc549 by thakis
[gn build] Kind of port c7b3a91017d2 (libclang version script)

libclang is only built as static library in the GN build at the
moment, which means we now generate a .exports file form a version
script and then link.exe and ld64 inputs from the .exports file
but don't use the version script, but hey.
The file was modifiedllvm/utils/gn/secondary/clang/tools/libclang/BUILD.gn
The file was modifiedllvm/utils/gn/secondary/clang/test/BUILD.gn
The file was modifiedllvm/utils/gn/build/symbol_exports.gni
Commit ebe817f98cbf836fc5f0abf70b7b04356026ca70 by joker.eph
Define the namespace for the Affine dialect in ODS (NFC)

This aligns the structure of the Affine dialect on all the other dialects.
In particular this makes the ODS C++ generated code independent of the
enclosing namespace.
The file was modifiedmlir/include/mlir/Dialect/Affine/IR/AffineOps.td
The file was modifiedmlir/include/mlir/Dialect/Affine/IR/AffineOps.h
Commit 8befd05aad9f425937182ac137d3509ddd4d47b3 by johannes
[Attributor][FIX] Track change status for AAIsDead properly

If we add a new live edge we need to indicate a change or otherwise the
new live block is not shown to users. Similarly, new known dead ends and
a changed `ToBeExploredFrom` set need to cause us to return CHANGED.
The file was modifiedllvm/lib/Transforms/IPO/AttributorAttributes.cpp
Commit e6f3e648c9caf84fca9d2039138b5b539b398f70 by johannes
[Attributor][FIX] Do not return CHANGED unconditionally

This caused us to rerun AAMemoryBehaviorFloating::updateImpl over and
over again. Unfortunately it turned out to be hard to reproduce the
behavior in a reasonable way.
The file was modifiedllvm/lib/Transforms/IPO/AttributorAttributes.cpp
Commit be2b569646984e4aac988afda3090c2225228752 by johannes
[OpenMP] Run rewriteDeviceCodeStateMachine in the Module not CGSCC pass

While rewriteDeviceCodeStateMachine should probably be folded into
buildCustomStateMachine, we at least need the optimization to happen.
This was not reliably the case in the CGSCC pass but in the Module pass
it seems to work reliably.

This also ports a test to the new kernel encoding (target_init/deinit),
and makes sure we cannot run the kernel in SPMD mode.

Differential Revision: https://reviews.llvm.org/D106345
The file was modifiedllvm/test/Transforms/OpenMP/gpu_state_machine_function_ptr_replacement.ll
The file was modifiedllvm/test/Transforms/OpenMP/custom_state_machines.ll
The file was modifiedllvm/lib/Transforms/IPO/OpenMPOpt.cpp
Commit e97e0a4fad091474131ad84d6f46009bf84c5b60 by tianshilei1992
[AbstractAttributor] Fold __kmpc_parallel_level if possible

Similar to D105787, this patch tries to fold `__kmpc_parallel_level` if possible.
Note that `__kmpc_parallel_level` doesn't take activeness into consideration,
based on current `deviceRTLs`, its return value can be such as 0, 1, 2, instead
of 0, 129, 130, etc. that also indicate activeness.

Reviewed By: jdoerfert

Differential Revision: https://reviews.llvm.org/D106154
The file was modifiedopenmp/libomptarget/deviceRTLs/interface.h
The file was modifiedllvm/lib/Transforms/IPO/OpenMPOpt.cpp
The file was modifiedopenmp/libomptarget/deviceRTLs/common/src/parallel.cu
The file was addedllvm/test/Transforms/OpenMP/parallel_level_fold.ll
Commit ae70b211ebb003b49c3aab480b882bc70d21a240 by 31459023+hctim
Revert "[GlobalISel] Add scalar widening for G_MERGE_VALUES destination"

This reverts commit 0a37163d1d855a2db41e1f46ddbc3f4570bd7ca6.

Reason: Broke the sanitizer msan bots. More details are available in the
original Phabricator review: https://reviews.llvm.org/D106814.
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/legalize-merge-values.mir
The file was modifiedllvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
The file was modifiedllvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h
Commit 25986a21ef6de4222f5bbd8b7f1e2c865b90431d by Lang Hames
[llvm-jitlink] Don't hardcode LLVM version number into the runtime path.

This should unbreak builders that were failing due to different patch numbers.
The file was modifiedllvm/tools/llvm-jitlink/llvm-jitlink.cpp
Commit 958dddf7dfd40bc01447b67b1b0a85e0c7c9941d by JunMa
[NFC][InstCombine] Fix typo
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
Commit 2ea9db0c49d7406de650be9e5cd72fc5687c66dd by craig.topper
[AArch64] Fix -Wparentheses warning with gcc 5.4. NFC
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp
Commit 531b19a49e66de5c4b35fc89eebc078c13eb9a85 by jianzhouzh
[dfsan][NFC] Fix doc format
The file was modifiedclang/docs/DataFlowSanitizer.rst
Commit 402461beb051b6a5c158f1e36d8e2c2b676e8804 by joker.eph
Build libSupport with -Werror=global-constructors (NFC)

Ensure that libSupport does not carry any static global initializer.
libSupport can be embedded in use cases where we don't want to load all
cl::opt unless we want to parse the command line.
ManagedStatic can be used to enable lazy-initialization of globals.

The -Werror=global-constructors is only added on platform that have
support for the flag and for which std::mutex does not have a global
destructor. This is ensured by having CMake trying to compile a file
with a global mutex before adding the flag to libSupport.
The file was modifiedllvm/lib/Support/CMakeLists.txt
The file was modifiedcompiler-rt/lib/sanitizer_common/symbolizer/scripts/build_symbolizer.sh
Commit adddd3dbdae074285f879c5eb7369a92fdd99117 by johannes
[Attributor] Introduce getPotentialCopiesOfStoredValue and use it

This patch introduces `getPotentialCopiesOfStoredValue` which uses
AAPointerInfo to determine all "aliases" or "potential copies" of a
value that is stored into memory. This operation can fail but if it
succeeds it means we can visit all "uses" of a value even if it is
temporarily stored in memory.

There are two users for the function:
  1) `Attributor::checkForAllUses` which will now ignore the value use
     in a store if all "potential copies" can be identified and instead
     be visited. This allows various AAs, including AAPointerInfo
     itself, to look through memory.
  2) `AANoCapture` which uses a custom use tracking through the
     CaptureTracker interface and therefore needs to be thought
     explicitly.

Differential Revision: https://reviews.llvm.org/D106185
The file was modifiedllvm/lib/Transforms/IPO/Attributor.cpp
The file was modifiedllvm/test/Transforms/Attributor/IPConstantProp/2009-09-24-byval-ptr.ll
The file was modifiedllvm/include/llvm/Transforms/IPO/Attributor.h
The file was modifiedllvm/test/Transforms/Attributor/nodelete.ll
The file was modifiedllvm/test/Transforms/OpenMP/spmdization.ll
The file was modifiedllvm/lib/Transforms/IPO/AttributorAttributes.cpp
The file was modifiedllvm/test/Transforms/Attributor/ArgumentPromotion/byval-2.ll
The file was modifiedllvm/test/Transforms/Attributor/value-simplify.ll
The file was modifiedllvm/test/Transforms/OpenMP/custom_state_machines.ll
The file was modifiedllvm/test/Transforms/Attributor/ArgumentPromotion/fp80.ll
Commit 41bd26dff9869a0d72f95ed750a82136f1bccc81 by johannes
[Attributor] Delete dead stores

D106185 allows us to determine if a store is needed easily. Using that
knowledge we can start to delete dead stores.

In AAIsDead we now track more state as an instruction can be dead (= the
old optimisitc state) or just "removable". A store instruction can be
removable while being very much alive, e.g., if it stores a constant
into an alloca or internal global. If we would pretend it was dead
instead of only removablewe we would ignore it when we determine what
values a load can see, so that is not what we want.

Differential Revision: https://reviews.llvm.org/D106188
The file was modifiedllvm/test/Transforms/Attributor/IPConstantProp/2009-09-24-byval-ptr.ll
The file was modifiedllvm/test/Transforms/Attributor/ArgumentPromotion/byval-2.ll
The file was modifiedllvm/test/Transforms/Attributor/nodelete.ll
The file was modifiedllvm/test/Transforms/Attributor/value-simplify.ll
The file was modifiedllvm/test/Transforms/Attributor/ArgumentPromotion/basictest.ll
The file was modifiedllvm/test/Transforms/Attributor/internal-noalias.ll
The file was modifiedllvm/lib/Transforms/IPO/AttributorAttributes.cpp
The file was modifiedllvm/test/Transforms/Attributor/ArgumentPromotion/live_called_from_dead_2.ll
The file was modifiedllvm/test/Transforms/Attributor/ArgumentPromotion/live_called_from_dead.ll
The file was modifiedllvm/test/Transforms/Attributor/misc_crash.ll
The file was modifiedllvm/test/Transforms/Attributor/ArgumentPromotion/alignment.ll
The file was modifiedllvm/include/llvm/Transforms/IPO/Attributor.h
The file was modifiedllvm/test/Transforms/Attributor/wrapper.ll
The file was modifiedllvm/test/Transforms/Attributor/ArgumentPromotion/byval.ll
The file was modifiedllvm/test/Transforms/Attributor/value-simplify-pointer-info.ll
The file was modifiedllvm/test/Transforms/Attributor/ArgumentPromotion/attrs.ll
The file was modifiedllvm/test/Transforms/Attributor/ArgumentPromotion/profile.ll
The file was modifiedllvm/test/Transforms/OpenMP/custom_state_machines.ll
The file was modifiedllvm/test/Transforms/Attributor/ArgumentPromotion/fp80.ll
The file was modifiedllvm/test/Transforms/Attributor/ArgumentPromotion/control-flow2.ll
The file was modifiedllvm/test/Transforms/Attributor/ArgumentPromotion/pr33641_remove_arg_dbgvalue.ll
The file was modifiedllvm/test/Transforms/OpenMP/spmdization.ll
Commit 25a3130d89f00f53a23f7fc38250d5dc43e29cfb by johannes
[Local] Do not introduce a new `llvm.trap` before `unreachable`

This is the second attempt to remove the `llvm.trap` insertion after
https://reviews.llvm.org/rGe14e7bc4b889dfaffb7180d176a03311df2d4ae6
reverted the first one. It is not clear what the exact issue was back
then and it might already be gone by now, it has been >5 years after
all.

Replaces D106299.

Differential Revision: https://reviews.llvm.org/D106308
The file was modifiedllvm/lib/Transforms/Coroutines/CoroSplit.cpp
The file was modifiedllvm/lib/Transforms/Utils/LoopUnroll.cpp
The file was modifiedllvm/lib/Transforms/Utils/LoopUtils.cpp
The file was modifiedllvm/lib/Transforms/IPO/Attributor.cpp
The file was modifiedllvm/lib/Transforms/IPO/PruneEH.cpp
The file was modifiedllvm/lib/Transforms/Coroutines/Coroutines.cpp
The file was modifiedllvm/test/Transforms/SimplifyCFG/trap-debugloc.ll
The file was modifiedllvm/test/Transforms/SimplifyCFG/trapping-load-unreachable.ll
The file was modifiedllvm/lib/Transforms/Scalar/SCCP.cpp
The file was modifiedllvm/lib/Transforms/Utils/InlineFunction.cpp
The file was modifiedllvm/unittests/Transforms/Utils/LocalTest.cpp
The file was modifiedllvm/lib/CodeGen/WinEHPrepare.cpp
The file was modifiedllvm/test/CodeGen/Thumb2/ifcvt-rescan-diamonds.ll
The file was modifiedllvm/test/Transforms/SimplifyCFG/invoke.ll
The file was modifiedllvm/lib/Transforms/Utils/Local.cpp
The file was modifiedllvm/test/CodeGen/Hexagon/swp-art-deps-rec.ll
The file was modifiedllvm/include/llvm/Transforms/Utils/Local.h
The file was modifiedllvm/test/CodeGen/ARM/vmul.ll
The file was modifiedllvm/lib/Transforms/Utils/LoopSimplify.cpp
Commit f0d41b58da4a102452af47c7b420577bd3d47a03 by wlei
[CSSPGO] Tweak ICP threshold in top-down inliner

This change slightly relaxed the current ICP threshold in top-down inliner, specifically always allow one ICP for it. It shows some perf improvements on SPEC and our internal benchmarks. Also renamed the previous flag. We can also try to turn off PGO ICP in the future.

Reviewed By: wenlei, hoy, wmi

Differential Revision: https://reviews.llvm.org/D106588
The file was modifiedllvm/lib/Transforms/IPO/SampleProfile.cpp
The file was modifiedllvm/test/Transforms/SampleProfile/csspgo-inline-icall.ll
Commit dbefcde6da1b58eb181dcbd8d7913175b2ec8350 by tstellar
Merge all the llvm-exegesis unit tests into a single binary

These tests access private symbols in the backends, so they cannot link
against libLLVM.so and must be statically linked.  Linking these tests
can be slow and with debug builds the resulting binaries use a lot of
disk space.

By merging them into a single test binary means we now only need to
statically link 1 test instead of 6, which helps reduce the build
times and saves disk space.

Reviewed By: courbet

Differential Revision: https://reviews.llvm.org/D106464
The file was modifiedllvm/unittests/tools/llvm-exegesis/ARM/CMakeLists.txt
The file was modifiedllvm/unittests/tools/llvm-exegesis/CMakeLists.txt
The file was modifiedllvm/unittests/tools/llvm-exegesis/X86/RegisterAliasingTest.cpp
The file was modifiedllvm/unittests/tools/llvm-exegesis/PowerPC/SnippetGeneratorTest.cpp
The file was modifiedllvm/unittests/tools/llvm-exegesis/PowerPC/AnalysisTest.cpp
The file was modifiedllvm/unittests/tools/llvm-exegesis/X86/SnippetGeneratorTest.cpp
The file was modifiedllvm/unittests/tools/llvm-exegesis/Mips/BenchmarkResultTest.cpp
The file was modifiedllvm/unittests/tools/llvm-exegesis/X86/CMakeLists.txt
The file was modifiedllvm/tools/llvm-exegesis/lib/BenchmarkResult.h
The file was modifiedllvm/unittests/tools/llvm-exegesis/X86/BenchmarkResultTest.cpp
The file was modifiedllvm/tools/llvm-exegesis/lib/BenchmarkResult.cpp
The file was modifiedllvm/unittests/tools/llvm-exegesis/AArch64/CMakeLists.txt
The file was modifiedllvm/unittests/tools/llvm-exegesis/X86/TargetTest.cpp
The file was modifiedllvm/unittests/tools/llvm-exegesis/X86/SchedClassResolutionTest.cpp
The file was modifiedllvm/unittests/tools/llvm-exegesis/Mips/CMakeLists.txt
The file was modifiedllvm/unittests/tools/llvm-exegesis/PowerPC/CMakeLists.txt
The file was modifiedllvm/unittests/tools/llvm-exegesis/Mips/SnippetGeneratorTest.cpp
The file was modifiedllvm/unittests/tools/llvm-exegesis/Mips/RegisterAliasingTest.cpp
Commit 0237dbfdd38053cc190f814b6f92e311ae3509c6 by yedeng.yd
[Coroutine] Record the elided coroutines

Reviewed By: lxfind

Differential Revision: https://reviews.llvm.org/D105606
The file was removedllvm/test/Transforms/Coroutines/coro-elide-count.ll
The file was addedllvm/test/Transforms/Coroutines/coro-elide-stat.ll
The file was modifiedllvm/lib/Transforms/Coroutines/CoroElide.cpp
Commit cdb4cfe8b3ce2b0c50d4855ec260eab07fe63611 by johannes
[Attributor][FIX] Update AMDGPU attributor test

The test contains UB and should be improved, for now we update the check
lines pass it.
The file was modifiedllvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa-call.ll
Commit 2aaf038efd8cb5db4e35f8b26a0b28b6ac1bb8b1 by johannes
[Attributor] Update check lines for all AMDGPU attributor tests

I thought there was only one when I pushed
cdb4cfe8b3ce2b0c50d4855ec260eab07fe63611, these should be all (in the
CodeGen/AMDGPU folder).
The file was modifiedllvm/test/CodeGen/AMDGPU/simple-indirect-call.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/direct-indirect-call.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/duplicate-attribute-indirect.ll
Commit 67ab875ff578588574a63d29d52f73fd25128c74 by johannes
[OpenMP] Prototype opt-in new GPU device RTL

The "old" OpenMP GPU device runtime (D14254) has served us well for many
years but modernizing it has caused some pain recently. This patch
introduces an alternative which is mostly written from scratch embracing
OpenMP 5.X, C++, LLVM coding style (where applicable), and conceptual
interfaces. This new runtime is opt-in through a clang flag (D106793).
The new runtime is currently only build for nvptx and has "-new" in its
name.

The design is tailored towards middle-end optimizations rather than
front-end code generation choices, a trend we already started in the old
runtime a while back. In contrast to the old one, state is organized in
a simple manner rather than a "smart" one. While this can induce costs
it helps optimizations. Our expectation is that the majority of codes
can be optimized and a "simple" design is therefore preferable. The new
runtime does also avoid users to pay for things they do not use,
especially wrt. memory. The unlikely case of nested parallelism is
supported but costly to make the more likely case use less resources.

The worksharing and reduction implementation have been taken from the
old runtime and will be rewritten in the future if necessary.

Documentation and debug features are still mostly missing and will be
added over time.

All external symbols start with `__kmpc` for legacy reasons but should
be renamed once we switch over to a single runtime. All internal symbols
are placed in appropriate namespaces (anonymous or `_OMP`) to avoid name
clashes with user symbols.

Differential Revision: https://reviews.llvm.org/D106803
The file was addedopenmp/libomptarget/DeviceRTL/include/Utils.h
The file was addedopenmp/libomptarget/DeviceRTL/src/Mapping.cpp
The file was addedopenmp/libomptarget/DeviceRTL/src/Reduction.cpp
The file was addedopenmp/libomptarget/DeviceRTL/CMakeLists.txt
The file was addedopenmp/libomptarget/DeviceRTL/include/Configuration.h
The file was addedopenmp/libomptarget/DeviceRTL/src/Tasking.cpp
The file was addedopenmp/libomptarget/DeviceRTL/src/Workshare.cpp
The file was addedopenmp/libomptarget/DeviceRTL/include/Interface.h
The file was addedopenmp/libomptarget/DeviceRTL/src/Synchronization.cpp
The file was addedopenmp/libomptarget/DeviceRTL/src/Misc.cpp
The file was addedopenmp/libomptarget/DeviceRTL/src/Utils.cpp
The file was addedopenmp/libomptarget/DeviceRTL/include/State.h
The file was modifiedopenmp/libomptarget/CMakeLists.txt
The file was addedopenmp/libomptarget/DeviceRTL/src/State.cpp
The file was addedopenmp/libomptarget/DeviceRTL/include/Types.h
The file was addedopenmp/libomptarget/DeviceRTL/src/Kernel.cpp
The file was addedopenmp/libomptarget/DeviceRTL/include/Debug.h
The file was addedopenmp/libomptarget/DeviceRTL/include/Mapping.h
The file was addedopenmp/libomptarget/DeviceRTL/src/Debug.cpp
The file was addedopenmp/libomptarget/DeviceRTL/include/generated_microtask_cases.gen
The file was addedopenmp/libomptarget/DeviceRTL/src/Parallelism.cpp
The file was addedopenmp/libomptarget/DeviceRTL/src/Configuration.cpp
The file was addedopenmp/libomptarget/DeviceRTL/include/Synchronization.h
Commit 75636868e2c96cb17fdfd1ed70e284ab19a15160 by johannes
[InstSimplify] Expose generic interface for replaced operand simplification

Users, especially the Attributor, might replace multiple operands at
once. The actual implementation of simplifyWithOpReplaced is able to
handle that just fine, the interface was simply not allowing to replace
more than one operand at a time. This is exposing a more generic
interface without intended changes for existing code.

Differential Revision: https://reviews.llvm.org/D106189
The file was modifiedllvm/lib/Analysis/InstructionSimplify.cpp
The file was modifiedllvm/include/llvm/Analysis/InstructionSimplify.h
Commit d4bfce552110086f198ba46f37acf63df8758921 by johannes
[Attributor] Utilize the InstSimplify interface to simplify instructions

When we simplify at least one operand in the Attributor simplification
we can use the InstSimplify to work on the simplified operands. This
allows us to avoid duplication of the logic.

Depends on D106189

Differential Revision: https://reviews.llvm.org/D106190
The file was modifiedllvm/test/Transforms/Attributor/willreturn.ll
The file was modifiedllvm/test/Transforms/Attributor/value-simplify.ll
The file was modifiedllvm/test/Transforms/Attributor/ArgumentPromotion/basictest.ll
The file was modifiedllvm/test/Transforms/Attributor/internalize.ll
The file was modifiedllvm/test/Transforms/Attributor/nonnull.ll
The file was modifiedllvm/test/Transforms/Attributor/value-simplify-pointer-info.ll
The file was modifiedllvm/test/Transforms/Attributor/depgraph.ll
The file was modifiedllvm/test/Transforms/Attributor/ArgumentPromotion/alignment.ll
The file was modifiedllvm/test/Transforms/Attributor/potential.ll
The file was modifiedllvm/test/Transforms/Attributor/internal-noalias.ll
The file was modifiedllvm/test/Transforms/Attributor/range.ll
The file was modifiedllvm/test/Transforms/Attributor/ArgumentPromotion/aggregate-promote.ll
The file was modifiedllvm/test/Transforms/Attributor/liveness.ll
The file was modifiedllvm/test/Transforms/Attributor/value-simplify-instances.ll
The file was modifiedllvm/test/Transforms/Attributor/IPConstantProp/return-argument.ll
The file was modifiedllvm/test/Transforms/Attributor/ArgumentPromotion/chained.ll
The file was modifiedllvm/lib/Transforms/IPO/AttributorAttributes.cpp
The file was modifiedllvm/test/Transforms/Attributor/IPConstantProp/PR16052.ll
The file was modifiedllvm/test/Transforms/Attributor/IPConstantProp/PR26044.ll
The file was modifiedllvm/test/Transforms/Attributor/ArgumentPromotion/invalidation.ll
The file was modifiedllvm/test/Transforms/Attributor/IPConstantProp/dangling-block-address.ll
The file was modifiedllvm/test/Transforms/Attributor/dereferenceable-1.ll
The file was modifiedllvm/test/Transforms/Attributor/lvi-after-jumpthreading.ll
Commit c55e18824d2e0711682c67b98653c38f8b0ac463 by johannes
[Attributor][FIX] Copy all members in the assignment operator

Also improve debug output slightly.
The file was modifiedllvm/test/Transforms/Attributor/ArgumentPromotion/X86/attributes.ll
The file was modifiedllvm/include/llvm/Transforms/IPO/Attributor.h
The file was modifiedllvm/test/Transforms/Attributor/IPConstantProp/2009-09-24-byval-ptr.ll
The file was modifiedllvm/test/Transforms/Attributor/internal-noalias.ll
The file was modifiedllvm/test/Transforms/Attributor/ArgumentPromotion/alignment.ll
The file was modifiedllvm/lib/Transforms/IPO/Attributor.cpp
The file was modifiedllvm/test/Transforms/Attributor/ArgumentPromotion/profile.ll
The file was modifiedllvm/test/Transforms/Attributor/ArgumentPromotion/2008-02-01-ReturnAttrs.ll
The file was modifiedllvm/test/Transforms/Attributor/value-simplify.ll
The file was modifiedllvm/test/Transforms/Attributor/ArgumentPromotion/X86/min-legal-vector-width.ll
The file was modifiedllvm/test/Transforms/Attributor/value-simplify-pointer-info.ll
The file was modifiedllvm/test/Transforms/Attributor/nodelete.ll
The file was modifiedllvm/test/Transforms/Attributor/ArgumentPromotion/basictest.ll
The file was modifiedllvm/test/Transforms/Attributor/ArgumentPromotion/control-flow2.ll
Commit 70b75f62fc617f1fa7e4859571a99137297146c6 by johannes
[OpenMP] Try to simplify all loads in device code

Eliminating loads/stores in the device code is worth the extra effort,
especially for the new device runtime.

At the same time we do not compute AAExecutionDomain for non-device code
anymore, there is no point.

Differential Revision: https://reviews.llvm.org/D106845
The file was modifiedllvm/include/llvm/Transforms/IPO/Attributor.h
The file was modifiedllvm/lib/Transforms/IPO/OpenMPOpt.cpp
Commit 2487db1f286222e2501c2fa8e8244eda13f6afc3 by Lang Hames
[ORC] Require ExecutorProcessControl when constructing an ExecutionSession.

Wrapper function call and dispatch handler helpers are moved to
ExecutionSession, and existing EPC-based tools are re-written to take an
ExecutionSession argument instead.

Requiring an ExecutorProcessControl instance simplifies existing EPC based
utilities (which only need to take an ES now), and should encourage more
utilities to use the EPC interface. It also simplifies process termination,
since the session can automatically call ExecutorProcessControl::disconnect
(previously this had to be done manually, and carefully ordered with the
rest of JIT tear-down to work correctly).
The file was modifiedllvm/tools/lli/lli.cpp
The file was modifiedllvm/unittests/ExecutionEngine/Orc/OrcTestCommon.h
The file was modifiedllvm/include/llvm/ExecutionEngine/Orc/EPCDebugObjectRegistrar.h
The file was modifiedllvm/include/llvm/ExecutionEngine/Orc/EPCEHFrameRegistrar.h
The file was modifiedllvm/examples/Kaleidoscope/BuildingAJIT/Chapter1/KaleidoscopeJIT.h
The file was modifiedllvm/include/llvm/ExecutionEngine/Orc/Core.h
The file was modifiedllvm/lib/ExecutionEngine/Orc/MachOPlatform.cpp
The file was modifiedllvm/include/llvm/ExecutionEngine/Orc/OrcRPCExecutorProcessControl.h
The file was modifiedllvm/unittests/ExecutionEngine/Orc/ObjectLinkingLayerTest.cpp
The file was addedllvm/unittests/ExecutionEngine/Orc/ExecutionSessionWrapperFunctionCallsTest.cpp
The file was modifiedllvm/include/llvm/ExecutionEngine/Orc/EPCDynamicLibrarySearchGenerator.h
The file was modifiedllvm/include/llvm/ExecutionEngine/Orc/ObjectLinkingLayer.h
The file was modifiedllvm/include/llvm/ExecutionEngine/Orc/ExecutorProcessControl.h
The file was modifiedllvm/examples/SpeculativeJIT/SpeculativeJIT.cpp
The file was modifiedllvm/examples/OrcV2Examples/LLJITWithTargetProcessControl/LLJITWithTargetProcessControl.cpp
The file was modifiedllvm/lib/ExecutionEngine/Orc/Core.cpp
The file was modifiedllvm/examples/Kaleidoscope/BuildingAJIT/Chapter2/KaleidoscopeJIT.h
The file was modifiedllvm/examples/Kaleidoscope/BuildingAJIT/Chapter3/KaleidoscopeJIT.h
The file was modifiedllvm/lib/ExecutionEngine/Orc/LLJIT.cpp
The file was modifiedllvm/include/llvm/ExecutionEngine/Orc/LLJIT.h
The file was modifiedllvm/lib/ExecutionEngine/Orc/OrcV2CBindings.cpp
The file was removedllvm/unittests/ExecutionEngine/Orc/ExecutorProcessControlTest.cpp
The file was modifiedllvm/unittests/ExecutionEngine/Orc/CMakeLists.txt
The file was modifiedllvm/examples/Kaleidoscope/include/KaleidoscopeJIT.h
The file was modifiedllvm/lib/ExecutionEngine/Orc/ObjectLinkingLayer.cpp
The file was modifiedllvm/examples/Kaleidoscope/BuildingAJIT/Chapter4/KaleidoscopeJIT.h
The file was modifiedllvm/lib/ExecutionEngine/Orc/EPCEHFrameRegistrar.cpp
The file was modifiedllvm/tools/llvm-jitlink/llvm-jitlink.h
The file was modifiedllvm/include/llvm/ExecutionEngine/Orc/MachOPlatform.h
The file was modifiedllvm/lib/ExecutionEngine/Orc/EPCDebugObjectRegistrar.cpp
The file was modifiedllvm/lib/ExecutionEngine/Orc/EPCDynamicLibrarySearchGenerator.cpp
The file was modifiedllvm/unittests/ExecutionEngine/Orc/RTDyldObjectLinkingLayerTest.cpp
The file was modifiedllvm/lib/ExecutionEngine/Orc/ExecutorProcessControl.cpp
The file was modifiedllvm/unittests/ExecutionEngine/Orc/CoreAPIsTest.cpp
The file was modifiedllvm/tools/llvm-jitlink/llvm-jitlink.cpp
Commit 66640aa5aeaf2d46040f6ae2d8ff5a4a35ecb8dc by llvmgnsyncbot
[gn build] Port 2487db1f2862
The file was modifiedllvm/utils/gn/secondary/llvm/unittests/ExecutionEngine/Orc/BUILD.gn
Commit 60426f33b1d417763ca1954fba5293c959c9623d by Jan Svoboda
[clang][driver] NFC: Move InputInfo.h from lib to include

Moving `InputInfo.h` from `lib/Driver/` into `include/Driver` to be able to expose it in an API consumed from outside of `clangDriver`.

Reviewed By: dexonsmith

Differential Revision: https://reviews.llvm.org/D106787
The file was modifiedclang/lib/Driver/ToolChains/Cuda.cpp
The file was modifiedclang/lib/Driver/ToolChains/AVR.cpp
The file was modifiedclang/lib/Driver/ToolChains/Ananas.cpp
The file was modifiedclang/lib/Driver/ToolChains/CommonArgs.h
The file was modifiedclang/lib/Driver/ToolChain.cpp
The file was modifiedclang/lib/Driver/ToolChains/CommonArgs.cpp
The file was modifiedclang/lib/Driver/ToolChains/BareMetal.cpp
The file was removedclang/lib/Driver/InputInfo.h
The file was modifiedclang/lib/Driver/ToolChains/AMDGPU.cpp
The file was modifiedclang/lib/Driver/ToolChains/AMDGPUOpenMP.cpp
The file was modifiedclang/lib/Driver/ToolChains/CloudABI.cpp
The file was modifiedclang/lib/Driver/ToolChains/Minix.cpp
The file was modifiedclang/lib/Driver/ToolChains/MinGW.cpp
The file was modifiedclang/lib/Driver/ToolChains/AVR.h
The file was modifiedclang/lib/Driver/ToolChains/RISCVToolchain.cpp
The file was modifiedclang/lib/Driver/ToolChains/NaCl.cpp
The file was modifiedclang/lib/Driver/Job.cpp
The file was modifiedclang/lib/Driver/ToolChains/Hexagon.cpp
The file was modifiedclang/lib/Driver/ToolChains/MSP430.cpp
The file was modifiedclang/lib/Driver/ToolChains/HIP.cpp
The file was modifiedclang/lib/Driver/ToolChains/Clang.cpp
The file was modifiedclang/lib/Driver/Driver.cpp
The file was modifiedclang/lib/Driver/Tool.cpp
The file was addedclang/include/clang/Driver/InputInfo.h
The file was modifiedclang/lib/Driver/ToolChains/MSP430.h
Commit b76c7c6faf06bb02b7b7b6bba3f6eb8a33edcdca by Jan Svoboda
[clang][driver] NFC: Expose InputInfo in Job instead of plain filenames

This patch exposes `InputInfo` in `Job` instead of plain filenames. This is useful in a follow-up patch that uses this to recognize `-cc1` commands interesting for Clang tooling.

Depends on D106787.

Reviewed By: dexonsmith

Differential Revision: https://reviews.llvm.org/D106788
The file was modifiedclang/include/clang/Driver/Job.h
The file was modifiedclang/lib/Driver/Job.cpp
The file was modifiedclang/unittests/Driver/ToolChainTest.cpp
Commit 14f6cfcf3cab34ec26474dc464a6a35589f582f7 by esme.yi
[Debug-Info][llvm-dwarfdump] Don't try to dump location
list for attributes that don't have the loclist class.

Summary: The overflow error occurs when we try to dump
location list for those attributes that do not have the
loclist class, like DW_AT_count and DW_AT_byte_size.
After re-reviewed the entire list, I sorted those
attributes into two parts, one for dumping location list
and one for dumping the location expression.

Reviewed By: probinson

Differential Revision: https://reviews.llvm.org/D105613
The file was modifiedllvm/include/llvm/DebugInfo/DWARF/DWARFAttribute.h
The file was modifiedllvm/lib/DWARFLinker/DWARFLinker.cpp
The file was modifiedllvm/lib/DebugInfo/DWARF/DWARFDie.cpp
The file was addedllvm/test/tools/llvm-dwarfdump/X86/formclass3.s

Summary

  1. Add missing closing quote to SVE 2 stage cmake options (details)
  2. [Zorg] Use ccache instead incremental build for openmp-offload-cuda-runtime. (details)
Commit 0b9e49366d6c3c39fabf7a20123cb37eac6297ca by david.spickett
Add missing closing quote to SVE 2 stage cmake options

Missing from 24c07902d058abcee3bcf908676bacaae1f3d448.
The file was modifiedbuildbot/osuosl/master/config/builders.py
Commit 2afbc972a9ca914efa903d3ffc987b5da80ec836 by llvm-project
[Zorg] Use ccache instead incremental build for openmp-offload-cuda-runtime.

Building with `LLVM_ENABLE_RUNTIMES=openmp` has the disadvantage that if clang changes, the runtime that was built with the previous clang is not rebuilt. That is, if the runtime is miscompiling due to a change in clang, this will only be detected in the next clean build.

For instance, commit rG1100e4aafea233bc8bbc307c5758a7d287ad3bae caused the libomptarget device runtime to miscompile, but the [[ https://lab.llvm.org/staging/#/builders/154/builds/1421 | openmp-offload-cuda-runtime builder ]] shows it as green. Tests only started failing with the [[ https://lab.llvm.org/staging/#/builders/154/builds/1427 | next clean build ]]. In production, this would have blamed the wrong commit.

In contrast, the openmp-offload-cuda-project builder started failing with the [[ https://lab.llvm.org/staging/#/builders/155/builds/1803 | expected commit ]].

Instead of building incrementally, use ccache to avoid this problem.

Reviewed By: gkistanova, tianshilei1992

Differential Revision: https://reviews.llvm.org/D106781
The file was modifiedbuildbot/osuosl/master/config/builders.py