Started 1 mo 24 days ago
Took 26 min

Build #44853 (Jun 24, 2022 1:45:06 PM)

Changes
  1. [RISCV] Replace two calls to getMinRVVVectorSizeInBits in fixed length lowering [nfc] (details)
  2. [RISCV] Simplify 16 bit index handling in lowerVECTOR_REVERSE [nfc] (details)

Started by an SCM change (5 times)

This run spent:

  • 40 min waiting;
  • 26 min build duration;
  • 1 hr 6 min total from scheduled to completion.
Revision: 24f77e8e0f993d3b0dc487a983caa21dc7f4ccaf
Repository: https://github.com/llvm/llvm-zorg.git
  • refs/remotes/origin/main
Revision: a0443dd47c84abd1ea7a4c3c4e6f14d38a08388a
Repository: http://labmaster3.local/git/llvm-project.git
  • refs/remotes/origin/main
Revision: 24f77e8e0f993d3b0dc487a983caa21dc7f4ccaf
Repository: http://labmaster3.local/git/llvm-zorg.git
  • refs/remotes/origin/main
Test Result (no failures)