SuccessChanges

Summary

  1. Revert "Add more historic DWARF vendor extensions" (details)
  2. [XCOFF] add C_FILE symbol at index 0 of symbol table. (details)
  3. [AArch64][GlobalISel][PostSelectOpt] Constrain reg operands after mutating instructions. (details)
  4. [HIP] Fix managed variable linkage (details)
Commit f14a14dd2564703db02f80c00db8ae492b594f77 by thakis
Revert "Add more historic DWARF vendor extensions"

This reverts commit c4a91444689455a35db1e7f50bcd876a3eb86126.
Breaks check-llvm everywhere, see https://reviews.llvm.org/D97242#2583716
The file was modifiedllvm/include/llvm/BinaryFormat/Dwarf.h (diff)
The file was modifiedllvm/include/llvm/BinaryFormat/Dwarf.def (diff)
Commit 71a39862475e1d192d41d335452267590103acfc by czhengsz
[XCOFF] add C_FILE symbol at index 0 of symbol table.

This is for XCOFF DWARF support.

Seems when DWARF debug is enable, symbol 0 has special usage
for AIX binder. At least, symbol 0 can not be the .text
section. Otherwise, we get some binding time error.

Add correct C_FILE symbol at index 0 here to make AIX binder
work.

Reviewed By: hubert.reinterpretcast

Differential Revision: https://reviews.llvm.org/D97117
The file was modifiedllvm/test/CodeGen/PowerPC/aix-xcoff-rodata.ll (diff)
The file was modifiedllvm/test/CodeGen/PowerPC/aix-xcoff-data-sections.ll (diff)
The file was modifiedllvm/test/CodeGen/PowerPC/aix-xcoff-explicit-section.ll (diff)
The file was modifiedllvm/test/CodeGen/PowerPC/aix-xcoff-lcomm.ll (diff)
The file was modifiedllvm/lib/MC/XCOFFObjectWriter.cpp (diff)
The file was modifiedllvm/test/CodeGen/PowerPC/aix-func-dsc-gen.ll (diff)
The file was modifiedllvm/test/CodeGen/PowerPC/aix-xcoff-reloc.ll (diff)
The file was modifiedllvm/test/CodeGen/PowerPC/aix-overflow-toc.py (diff)
The file was modifiedllvm/test/CodeGen/PowerPC/aix-weak.ll (diff)
The file was modifiedllvm/test/CodeGen/PowerPC/aix-xcoff-symbol-rename.ll (diff)
The file was modifiedllvm/test/CodeGen/PowerPC/aix-extern.ll (diff)
The file was modifiedllvm/test/CodeGen/PowerPC/aix-user-defined-memcpy.ll (diff)
The file was modifiedllvm/test/CodeGen/PowerPC/aix-llvm-intrinsic.ll (diff)
The file was modifiedllvm/test/CodeGen/PowerPC/aix-xcoff-data.ll (diff)
The file was modifiedllvm/test/CodeGen/PowerPC/aix-extern-weak.ll (diff)
Commit eb55203e009ec98351f2be6e5655b7178b604920 by Amara Emerson
[AArch64][GlobalISel][PostSelectOpt] Constrain reg operands after mutating instructions.

The non-flag setting variants of instructions may have different regclass
requirements. If so, we need to constrain them.

Differential Revision: https://reviews.llvm.org/D97343
The file was addedllvm/test/CodeGen/AArch64/GlobalISel/postselectopt-constrain-new-regop.mir
The file was modifiedllvm/lib/Target/AArch64/GISel/AArch64PostSelectOptimize.cpp (diff)
Commit a3ce7f5cd2ae236bec7752e343f4b63ddda7ebe7 by Yaxun.Liu
[HIP] Fix managed variable linkage

Currently managed variables are emitted as undefined symbols, which
causes difficulty for diagnosing undefined symbols for non-managed
variables.

This patch transforms managed variables in device compilation so that
they can be emitted as normal variables.

Reviewed by: Artem Belevich

Differential Revision: https://reviews.llvm.org/D96195
The file was modifiedclang/test/CodeGenCUDA/managed-var.cu (diff)
The file was modifiedllvm/lib/IR/ReplaceConstant.cpp (diff)
The file was modifiedclang/test/CodeGenCUDA/device-var-linkage.cu (diff)
The file was modifiedclang/lib/CodeGen/CGCUDARuntime.h (diff)
The file was modifiedclang/lib/CodeGen/CGCUDANV.cpp (diff)
The file was modifiedclang/lib/CodeGen/CodeGenModule.cpp (diff)