Changes

Summary

  1. [AMDGPU] Introduce never uniform bit field in tablegen (details)
  2. DAGCombiner: fix -Wunused-private-field. NFC (details)
  3. [RISCV] Add vendor-defined XTHeadBa (address-generation) extension (details)
  4. [RISCV] Add performMULcombine to perform strength-reduction (details)
  5. [RISCV] Add vendor-defined XTHeadBs (single-bit) extension (details)
  6. [RISCV] Add vendor-defined XTheadBb (basic bit-manipulation) extension (details)
  7. [RISCV] Fix comment for Zba tests. NFC. (details)
  8. Revert "[RISCV] Add vendor-defined XTheadBb (basic bit-manipulation) extension" (details)
  9. Revert "[RISCV] Add vendor-defined XTHeadBs (single-bit) extension" (details)
  10. Revert "[RISCV] Add performMULcombine to perform strength-reduction" (details)
  11. [compiler-rt][macOS]: Disable iOS support if iOS SDK is not found (details)
Commit cde2f330b36fc36760329be1d3c52e92da400663 by Yashwant.Singh
[AMDGPU] Introduce never uniform bit field in tablegen

IsNeverUniform can be set to 1 to mark instructions which are
inherently never-uniform/divergent. Enabling this bit in
Writelane instruction for now. To be extended to all required
instructions.

Reviewed By: arsenm, sameerds, #amdgpu

Differential Revision: https://reviews.llvm.org/D143154
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.h (diff)
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrFormats.td (diff)
The file was modifiedllvm/test/Analysis/DivergenceAnalysis/AMDGPU/MIR/never-uniform.mir (diff)
The file was modifiedllvm/lib/Target/AMDGPU/SIInstrInfo.cpp (diff)
The file was modifiedllvm/lib/Target/AMDGPU/VOP2Instructions.td (diff)
The file was modifiedllvm/lib/Target/AMDGPU/SIDefines.h (diff)
The file was modifiedllvm/test/Analysis/DivergenceAnalysis/AMDGPU/MIR/always-uniform.mir (diff)
Commit a13645cf8c9ac403d4fa8da29a74392a4777b245 by i
DAGCombiner: fix -Wunused-private-field. NFC
The file was modifiedllvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (diff)
Commit e25b30d90a69846650fa15a3e41a013ea20193ff by philipp.tomsich
[RISCV] Add vendor-defined XTHeadBa (address-generation) extension

The vendor-defined XTHeadBa (predating the standard Zba extension)
extension adds an address-generation instruction (th.addsl) with
similar semantics as sh[123]add from Zba.  It is supported by the C9xx
cores (e.g., found in the wild in the Allwinner D1) by Alibaba T-Head.

The current (as of this commit) public documentation for XTHeadBa is
available from:
  https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf

Support for these instructions has already landed in GNU Binutils:
  https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=8254c3d2c94ae5458095ea6c25446ba89134b9da

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D143029
The file was addedllvm/test/MC/RISCV/XTHeadBa-invalid.s
The file was addedllvm/test/CodeGen/RISCV/rv64xtheadba.ll
The file was modifiedllvm/docs/ReleaseNotes.rst (diff)
The file was modifiedllvm/docs/RISCVUsage.rst (diff)
The file was modifiedllvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp (diff)
The file was modifiedllvm/lib/Target/RISCV/RISCVFeatures.td (diff)
The file was addedllvm/test/CodeGen/RISCV/rv32xtheadba.ll
The file was addedllvm/test/MC/RISCV/XTHeadBa-valid.s
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td (diff)
The file was modifiedllvm/test/CodeGen/RISCV/attributes.ll (diff)
The file was modifiedllvm/lib/Support/RISCVISAInfo.cpp (diff)
Commit 3304d51b676ea511feca28089cb60eba3873132e by philipp.tomsich
[RISCV] Add performMULcombine to perform strength-reduction

The RISC-V backend thus far does not provide strength-reduction, which
causes a long (but not complete) list of 3-instruction patterns listed
to utilize the shift-and-add instruction from Zba and XTHeadBa in
strength-reduction.

This adds the logic to perform strength-reduction through the DAG
combine for ISD::MUL.  Initially, we wire this up for XTheadBa only,
until this has had some time to settle and get real-world test
exposure.

The following strength-reductions strategies are currently supported:
  - XTheadBa
    - C = (n + 1)           // th.addsl
    - C = (n + 1)k          // th.addsl, slli
    - C = (n + 1)(m + 1)    // th.addsl, th.addsl
    - C = (n + 1)(m + 1)k   // th.addsl, th.addsl, slli
    - C = ((n + 1)m + 1)    // th.addsl, th.addsl
    - C = ((n + 1)m + 1)k   // th.addslm th.addsl, slli
  - base ISA
    - C being 2 set-bits    // slli, slli, add
       (possibly slli, th.addsl)

Even though the slli+slli+add sequence would we supported without
XTheadBa, this currently is gated to avoid having to update a large
number of test cases (i.e., anything that has a multiplication with a
constant where only 2 bits are set) in this commit.

With the strength reduction now being performed in performMUL combine,
we drop the (now redundant) patterns from RISCVInstrInfoXTHead.td.

Depends on D143029

Differential Revision: https://reviews.llvm.org/D143394
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.cpp (diff)
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td (diff)
Commit 656188ddc4075eb50260607b3497589873f373d2 by philipp.tomsich
[RISCV] Add vendor-defined XTHeadBs (single-bit) extension

The vendor-defined XTHeadBs (predating the standard Zbs extension)
extension adds a bit-test instruction (th.tst) with similar semantics
as bexti from Zbs.  It is supported by the C9xx cores (e.g., found in
the wild in the Allwinner D1) by Alibaba T-Head.

The current (as of this commit) public documentation for XTHeadBs is
available from:
  https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf

Support for these instructions has already landed in GNU Binutils:
  https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=8254c3d2c94ae5458095ea6c25446ba89134b9da

Depends on D143394

Differential Revision: https://reviews.llvm.org/D143036
The file was modifiedllvm/docs/RISCVUsage.rst (diff)
The file was modifiedllvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp (diff)
The file was addedllvm/test/CodeGen/RISCV/rv32xtheadbs.ll
The file was addedllvm/test/MC/RISCV/rv32xtheadbs-valid.s
The file was addedllvm/test/MC/RISCV/rv64xtheadbs-invalid.s
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.cpp (diff)
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td (diff)
The file was modifiedllvm/test/CodeGen/RISCV/bittest.ll (diff)
The file was modifiedllvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp (diff)
The file was modifiedllvm/lib/Target/RISCV/RISCVFeatures.td (diff)
The file was addedllvm/test/MC/RISCV/rv32xtheadbs-invalid.s
The file was modifiedllvm/lib/Support/RISCVISAInfo.cpp (diff)
The file was addedllvm/test/CodeGen/RISCV/rv64xtheadbs.ll
The file was modifiedllvm/docs/ReleaseNotes.rst (diff)
The file was modifiedllvm/test/CodeGen/RISCV/attributes.ll (diff)
Commit 19a59099095b3cbc9846e5330de26fca0a44ccbe by philipp.tomsich
[RISCV] Add vendor-defined XTheadBb (basic bit-manipulation) extension

The vendor-defined XTHeadBb (predating the standard Zbb extension)
extension adds some bit-manipulation extensions with somewhat similar
semantics as some of the Zbb instructions.

It is supported by the C9xx cores (e.g., found in the wild in the
Allwinner D1) by Alibaba T-Head.

The current (as of this commit) public documentation for XTHeadBb is
available from:
  https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf

Support for these instructions has already landed in GNU Binutils:
  https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=8254c3d2c94ae5458095ea6c25446ba89134b9da

Depends on D143036

Differential Revision: https://reviews.llvm.org/D143439
The file was modifiedllvm/test/CodeGen/RISCV/rotl-rotr.ll (diff)
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td (diff)
The file was addedclang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-xtheadbb.c
The file was modifiedllvm/test/CodeGen/RISCV/imm.ll (diff)
The file was modifiedllvm/lib/Support/RISCVISAInfo.cpp (diff)
The file was addedllvm/test/CodeGen/RISCV/rv32xtheadbb.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVFeatures.td (diff)
The file was modifiedllvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp (diff)
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.cpp (diff)
The file was modifiedllvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll (diff)
The file was modifiedllvm/docs/RISCVUsage.rst (diff)
The file was addedllvm/test/CodeGen/RISCV/rv64xtheadbb.ll
The file was modifiedclang/include/clang/Basic/BuiltinsRISCV.def (diff)
The file was addedclang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c
The file was modifiedllvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp (diff)
The file was modifiedllvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp (diff)
Commit 94888161c7d9133bf6f32ae0d47a4fb0f41985f2 by philipp.tomsich
[RISCV] Fix comment for Zba tests. NFC.

The comments in the Zba tests were referring to the "bitmanip base"
extension (i.e., the Zbb).  Fix it.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D143534
The file was modifiedllvm/test/MC/RISCV/rv64zba-valid.s (diff)
The file was modifiedllvm/test/MC/RISCV/rv32zba-valid.s (diff)
Commit b0c3132226d521d6693608ee76fb3c0dc260ce89 by philipp.tomsich
Revert "[RISCV] Add vendor-defined XTheadBb (basic bit-manipulation) extension"

This reverts commit 19a59099095b3cbc9846e5330de26fca0a44ccbe.
The file was modifiedllvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp (diff)
The file was modifiedllvm/docs/RISCVUsage.rst (diff)
The file was removedllvm/test/CodeGen/RISCV/rv64xtheadbb.ll
The file was modifiedllvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp (diff)
The file was modifiedllvm/lib/Target/RISCV/RISCVFeatures.td (diff)
The file was removedllvm/test/CodeGen/RISCV/rv32xtheadbb.ll
The file was modifiedllvm/lib/Support/RISCVISAInfo.cpp (diff)
The file was modifiedllvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll (diff)
The file was modifiedllvm/test/CodeGen/RISCV/imm.ll (diff)
The file was modifiedclang/include/clang/Basic/BuiltinsRISCV.def (diff)
The file was modifiedllvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp (diff)
The file was removedclang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-xtheadbb.c
The file was removedclang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-xtheadbb.c
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.cpp (diff)
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td (diff)
The file was modifiedllvm/test/CodeGen/RISCV/rotl-rotr.ll (diff)
Commit 0bda199285954dea3b36539a17ea4a0a5bfa6cb1 by philipp.tomsich
Revert "[RISCV] Add vendor-defined XTHeadBs (single-bit) extension"

This reverts commit 656188ddc4075eb50260607b3497589873f373d2.
The file was removedllvm/test/CodeGen/RISCV/rv32xtheadbs.ll
The file was modifiedllvm/test/CodeGen/RISCV/attributes.ll (diff)
The file was removedllvm/test/CodeGen/RISCV/rv64xtheadbs.ll
The file was modifiedllvm/docs/ReleaseNotes.rst (diff)
The file was removedllvm/test/MC/RISCV/rv64xtheadbs-invalid.s
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.cpp (diff)
The file was removedllvm/test/MC/RISCV/rv32xtheadbs-invalid.s
The file was removedllvm/test/MC/RISCV/rv32xtheadbs-valid.s
The file was modifiedllvm/lib/Support/RISCVISAInfo.cpp (diff)
The file was modifiedllvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp (diff)
The file was modifiedllvm/lib/Target/RISCV/RISCVFeatures.td (diff)
The file was modifiedllvm/docs/RISCVUsage.rst (diff)
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td (diff)
The file was modifiedllvm/test/CodeGen/RISCV/bittest.ll (diff)
The file was modifiedllvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp (diff)
Commit b4431b2d945b6fc19b1a55ac6ce969a8e06e1e93 by philipp.tomsich
Revert "[RISCV] Add performMULcombine to perform strength-reduction"

This reverts commit 3304d51b676ea511feca28089cb60eba3873132e.
The file was modifiedllvm/lib/Target/RISCV/RISCVISelLowering.cpp (diff)
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td (diff)
Commit 78fb02107ae5819501af2600b0bebd48c1900a9b by tobias
[compiler-rt][macOS]: Disable iOS support if iOS SDK is not found

If you are missing the iOS SDK on your macOS (for example you don't have
full Xcode but just CommandLineTools) then CMake currently errors
out without a helpful message. This patch disables iOS support in
compiler-rt if the iOS SDK is not found. This can be overriden by
passing -DCOMPILER_RT_ENABLE_IOS=ON.

Reviewed By: delcypher, thetruestblue

Differential Revision: https://reviews.llvm.org/D133273
The file was modifiedcompiler-rt/cmake/base-config-ix.cmake (diff)