Commit
3e98b88797e52914ca67aa173aad97595fa61c73
by lebedev.ri[NFC][SimplifyCFG] Fix tests to use FileCheck instead of grep
|
 | llvm/test/Transforms/SimplifyCFG/branch-phi-thread.ll |
| llvm/test/Transforms/SimplifyCFG/hoist-common-code.ll |
| llvm/test/Transforms/SimplifyCFG/branch-cond-prop.ll |
| llvm/test/Transforms/SimplifyCFG/PhiEliminate.ll |
| llvm/test/Transforms/SimplifyCFG/iterative-simplify.ll |
| llvm/test/Transforms/SimplifyCFG/dbginfo.ll |
| llvm/test/Transforms/SimplifyCFG/duplicate-phis.ll |
| llvm/test/Transforms/SimplifyCFG/2008-05-16-PHIBlockMerge.ll |
| llvm/test/Transforms/SimplifyCFG/BrUnwind.ll |
| llvm/test/Transforms/SimplifyCFG/2008-12-16-DCECond.ll |
| llvm/test/Transforms/SimplifyCFG/EqualPHIEdgeBlockMerge.ll |
| llvm/test/Transforms/SimplifyCFG/branch-fold-test.ll |
| llvm/test/Transforms/SimplifyCFG/return-merge.ll |
| llvm/test/Transforms/SimplifyCFG/branch-cond-merge.ll |
| llvm/test/Transforms/SimplifyCFG/PhiNoEliminate.ll |
| llvm/test/Transforms/SimplifyCFG/2009-05-12-externweak.ll |
| llvm/test/Transforms/SimplifyCFG/PhiBlockMerge2.ll |
| llvm/test/Transforms/SimplifyCFG/UncondBranchToReturn.ll |
Commit
4cf74469a0f58c01a7fcf140a028b2a68f71df58
by lebedev.ri[NFC][SimplifyCFG] Add basic test for debuginfo preservation of `ret` tail merging
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| llvm/test/Transforms/SimplifyCFG/return-merge.ll |
Commit
2bfe0536e5143caad80f7a9691fa775cf451317b
by jdenny.ornl[UpdateCCTestChecks] Fix --replace-value-regex across RUN lines
Without this patch, llvm/utils/update_cc_test_checks.py fails to
perform `--replace-value-regex` replacements when two RUN lines
produce the same output and use the same single FileCheck prefix. The
problem is that replacements in a RUN line's output are not performed
until after comparing against previous RUN lines' output, where
replacements have already been performed. This patch fixes that.
Reviewed By: MaskRay
Differential Revision: https://reviews.llvm.org/D104566
|
 | clang/test/utils/update_cc_test_checks/replace-value-regex-across-runs.test |
| llvm/utils/UpdateTestChecks/common.py |
| clang/test/utils/update_cc_test_checks/Inputs/replace-value-regex-across-runs.c |
| clang/test/utils/update_cc_test_checks/Inputs/replace-value-regex-across-runs.c.expected |
Commit
3996311ee1b0a3c29a3ffcf9400e12ca76a846d9
by Jinsong Ji[DAGCombine] reassoc flag shouldn't enable contract
According to IR LangRef, the FMF flag:
contract
Allow floating-point contraction (e.g. fusing a multiply followed by an
addition into a fused multiply-and-add).
reassoc
Allow reassociation transformations for floating-point instructions.
This may dramatically change results in floating-point.
My understanding is that these two flags shouldn't imply each other,
as we might have a SDNode that can be reassociated with others, but
not contractble.
eg: We may want following fmul/fad/fsub to freely reassoc, but don't
want fma being generated here.
%F = fmul reassoc double %A, %B ; <double> [#uses=1]
%G = fmul reassoc double %C, %D ; <double> [#uses=1]
%H = fadd reassoc double %F, %G ; <double> [#uses=1]
%I = fsub reassoc double %H, %E ; <double> [#uses=1]
Before https://reviews.llvm.org/D45710, `reassoc` flag actually
did not imply isContratable either.
The current implementation also only check the flag in fadd node,
ignoring fmul node, this patch update that as well.
Reviewed By: spatel, qiucf
Differential Revision: https://reviews.llvm.org/D104247
|
| llvm/test/CodeGen/PowerPC/fma-negate.ll |
| llvm/test/CodeGen/AMDGPU/fmuladd.f32.ll |
| llvm/test/CodeGen/PowerPC/fmf-propagation.ll |
| llvm/test/CodeGen/PowerPC/fma-aggr-FMF.ll |
| llvm/test/CodeGen/PowerPC/register-pressure-reduction.ll |
| llvm/test/CodeGen/AArch64/fadd-combines.ll |
| llvm/test/CodeGen/AMDGPU/fmuladd.v2f16.ll |
| llvm/test/CodeGen/PowerPC/fma-combine.ll |
| llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp |
| llvm/test/CodeGen/PowerPC/fma-precision.ll |
| llvm/test/CodeGen/PowerPC/machine-combiner.ll |
| llvm/test/CodeGen/PowerPC/repeated-fp-divisors.ll |
| llvm/test/CodeGen/PowerPC/fdiv.ll |
| llvm/test/CodeGen/PowerPC/recipest.ll |
| llvm/test/CodeGen/X86/machine-combiner.ll |
| llvm/test/CodeGen/AMDGPU/fmuladd.f64.ll |
| llvm/test/CodeGen/PowerPC/combine-fneg.ll |
| llvm/test/CodeGen/PowerPC/fma-assoc.ll |
| llvm/test/CodeGen/AMDGPU/fmuladd.f16.ll |
| llvm/test/CodeGen/PowerPC/fma-mutate.ll |
| llvm/test/CodeGen/X86/sqrt-fastmath.ll |
Commit
c618692218d16e88fa20df56b29a8dd09c9e9db7
by i[AArch64][X86] Allow 64-bit label differences lower to IMAGE_REL_*_REL32
`IMAGE_REL_ARM64_REL64/IMAGE_REL_AMD64_REL64` do not exist and `.quad a - .` is
currently not representable.
For instrumentation, `.quad a - .` is useful representing a cross-section
reference in a metadata section, to allow ELF medium/large code models. The COFF
limitation makes such generic instrumentations inconvenient. I plan to make a
PGO/coverage metadata section field relative in D104556.
Differential Revision: https://reviews.llvm.org/D104564
|
| llvm/test/MC/AArch64/coff-relocations.s |
| llvm/test/MC/COFF/cross-section-relative.s |
| llvm/lib/Target/X86/MCTargetDesc/X86WinCOFFObjectWriter.cpp |
| llvm/test/MC/COFF/cross-section-relative-err.s |
| llvm/lib/Target/AArch64/MCTargetDesc/AArch64WinCOFFObjectWriter.cpp |
Commit
bf0d0671a1062aec973c14522d6accf0c438b92e
by efriedma[ARM] Make sure we don't transform unaligned store to stm on Thumb1.
This isn't likely to come up in practice; the combination of compiler
flags required to hit this issue should be rare. Found by inspection.
|
| llvm/lib/Target/ARM/ARMISelLowering.cpp |
| llvm/test/CodeGen/Thumb/ldm-stm-postinc.ll |
Commit
8c68eb83065cc531fde28fc743a7278190f9eb65
by xur[SampleFDO] Make FSDiscriminator flag part of function parameters
Add a parameter of IsFSDiscriminator to function
getBaseDiscriminatorFromDiscriminator().
This function currently checks the internal flag of
--enable-fs-discriminator. This is not good because we might
change the default value of the internal flag.
Note that we have a default parameter. This is just
because create_afdo_tool has a call-site to it.
I will remove the default parameter in a later patch.
Differential Revision: https://reviews.llvm.org/D104584
|
| llvm/include/llvm/IR/DebugInfoMetadata.h |
| llvm/include/llvm/Transforms/Utils/SampleProfileLoaderBaseImpl.h |
| llvm/tools/llvm-profgen/ProfiledBinary.cpp |
Commit
759e7977679299296a0074bc3aba693d3386eb1c
by browneee[DFSan][NFC] Refactor Origin Address Alignment code.
Reviewed By: stephan.yichao.zhao
Differential Revision: https://reviews.llvm.org/D104565
|
| compiler-rt/lib/dfsan/dfsan.cpp |
Commit
8ace12130526f450c822ca232d1f865b247d7434
by ndesaulniers[IR] convert warn-stack-size from module flag to fn attr
Otherwise, this causes issues when building with LTO for object files
that use different values.
Link: https://github.com/ClangBuiltLinux/linux/issues/1395
Reviewed By: dblaikie, MaskRay
Differential Revision: https://reviews.llvm.org/D104342
|
| llvm/lib/IR/Module.cpp |
| llvm/test/Verifier/invalid-warn-stack-size.ll |
| clang/lib/CodeGen/CodeGenModule.cpp |
| llvm/test/CodeGen/X86/warn-stack.ll |
| llvm/lib/CodeGen/PrologEpilogInserter.cpp |
 | llvm/test/Linker/warn-stack-frame.ll |
| llvm/test/CodeGen/ARM/warn-stack.ll |
| llvm/include/llvm/IR/Module.h |
| llvm/docs/LangRef.rst |
| clang/lib/CodeGen/CodeGenFunction.cpp |
| clang/test/Frontend/fwarn-stack-size.c |
| llvm/lib/IR/Verifier.cpp |
Commit
4181bfe6888fdc6f24dc42d4ebb295920826de2b
by gclaytonClarify the "env" launch configuration setting.
A few users recently were trying to set environment values when using lldb-vscode and were unsure of the format of the "env" launch configuration setting. Clarify the exact format as when users add the "env" launch config setting, they can see this help string in the IDE.
Differential Revision: https://reviews.llvm.org/D104578
|
| lldb/tools/lldb-vscode/package.json |
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