Changes

Summary

[mlir][tosa] Enable tosa.div for TosaMakeBroadcastable (details)
[ScalarEvolution] Ensure backedge-taken counts are not pointers. (details)
[NFC] Add getUnderlyingObjects test (details)
Rename MachineMemOperand::getOrdering -> getSuccessOrdering. (details)

Commit ad1a9d629b759f43c8c1ea5d4c710c5c5b4b1e6b by rob.suderman [mlir][tosa] Enable tosa.div for TosaMakeBroadcastable TosaMakeBroadcastable needs to include tosa.div, which was added later in the specification. Reviewed By: sjarus, NatashaKnk Differential Revision: https://reviews.llvm.org/D104157
	mlir/lib/Dialect/Tosa/Transforms/TosaMakeBroadcastable.cpp
Commit 8f3d16905d75b07a933d01dc29677fe5867c1b3e by efriedma [ScalarEvolution] Ensure backedge-taken counts are not pointers. A backedge-taken count doesn't refer to memory; returning a pointer type is nonsense. So make sure we always return an integer. The obvious way to do this would be to just convert the operands of the icmp to integers, but that doesn't quite work out at the moment: isLoopEntryGuardedByCond currently gets confused by ptrtoint operations. So we perform the ptrtoint conversion late for lt/gt operations. The test changes are mostly innocuous. The most interesting changes are more complex SCEV expressions of the form "(-1 * (ptrtoint i8* %ptr to i64)) + %ptr)". This is expected: we can't fold this to zero because we need to preserve the pointer base. The call to isLoopEntryGuardedByCond in howFarToZero is less precise because of ptrtoint operations; this shows up in the function pr46786_c26_char in ptrtoint.ll. Fixing it here would require more complex refactoring. It should eventually be fixed by future improvements to isImpliedCond. See https://bugs.llvm.org/show_bug.cgi?id=46786 for context. Differential Revision: https://reviews.llvm.org/D103656
	llvm/test/Transforms/LoopVectorize/pointer-induction.ll
	llvm/test/Transforms/LoopVectorize/pr45259.ll
	llvm/lib/Analysis/ScalarEvolution.cpp
	llvm/test/Transforms/PhaseOrdering/scev-custom-dl.ll
	llvm/test/Analysis/ScalarEvolution/max-backedge-taken-count-guard-info.ll
	llvm/test/Analysis/ScalarEvolution/nsw.ll
	llvm/test/Transforms/IndVarSimplify/eliminate-exit-no-dl.ll
	llvm/test/Transforms/LoopReroll/ptrindvar.ll
	llvm/test/Transforms/IndVarSimplify/2011-11-01-lftrptr.ll
	llvm/test/Transforms/LoopVectorize/X86/cost-model-assert.ll
	llvm/test/Analysis/ScalarEvolution/ptrtoint.ll
	llvm/test/Analysis/ScalarEvolution/no-wrap-symbolic-becount.ll
	llvm/test/Transforms/LoopIdiom/memset-debugify-remarks.ll
Commit ac15a128d8756074b150bb5cb11bfd93a1a5c30c by Vitaly Buka [NFC] Add getUnderlyingObjects test Reviewed By: lebedev.ri Differential Revision: https://reviews.llvm.org/D104585
	llvm/test/Analysis/LoopAccessAnalysis/underlying-objects-2.ll
Commit 74909e4b6e9bc0da6c197cf6c4419991a8dc335f by efriedma Rename MachineMemOperand::getOrdering -> getSuccessOrdering. Since this method can apply to cmpxchg operations, make sure it's clear what value we're actually retrieving. This will help ensure we don't accidentally ignore the failure ordering of cmpxchg in the future. We could potentially introduce a getOrdering() method on AtomicSDNode that asserts the operation isn't cmpxchg, but not sure that's worthwhile. Differential Revision: https://reviews.llvm.org/D103338
	llvm/lib/CodeGen/MachineFunction.cpp
	llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
	llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
	llvm/lib/CodeGen/MachineOperand.cpp
	llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp
	llvm/lib/Target/X86/X86ISelLowering.cpp
	llvm/lib/CodeGen/GlobalISel/LegalizerInfo.cpp
	llvm/lib/Target/ARM/ARMISelLowering.cpp
	llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
	llvm/lib/Target/XCore/XCoreISelLowering.cpp
	llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
	llvm/lib/CodeGen/MachineStableHash.cpp
	llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
	llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
	llvm/include/llvm/CodeGen/SelectionDAGNodes.h
	llvm/lib/Target/ARM/ARMInstrInfo.td
	llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
	llvm/lib/Target/Sparc/SparcISelLowering.cpp
	llvm/include/llvm/CodeGen/MachineMemOperand.h
	llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
	llvm/lib/CodeGen/MIRVRegNamerUtils.cpp