Changes

Summary

[mlir][linalg] ComprehensiveBufferize: Do not copy InitTensorOp results (details)
[LV] Min/max intrinsic reduction test cases. (details)
[NVPTX] NFC: Remove unused imm type intrinsic arg (details)
[OpenCL] Supports optional image types in C++ for OpenCL 2021 (details)
[MIPS] Remove unused tblgen template args. NFC (details)
[X86] combineX86ShuffleChain - ensure we only peek through bitcasts to vectors (PR51858) (details)
[LV] Recognize intrinsic min/max reductions (details)

Commit 934e2f695e18033fdf740ab45bb5b0dfdf453c19 by springerm [mlir][linalg] ComprehensiveBufferize: Do not copy InitTensorOp results E.g.: ``` %2 = memref.alloc() {alignment = 128 : i64} : memref<256x256xf32> %3 = memref.alloc() {alignment = 128 : i64} : memref<256x256xf32> // ... (%3 is not written to) linalg.copy(%3, %2) : memref<256x256xf32>, memref<256x256xf32> vector.transfer_write %11, %2[%c0, %c0] {in_bounds = [true, true]} : vector<256x256xf32>, memref<256x256xf32> ``` Avoid copies of %3 if %3 came directly from an InitTensorOp. Differential Revision: https://reviews.llvm.org/D109742
	mlir/lib/Dialect/Linalg/Transforms/ComprehensiveBufferize.cpp
Commit bddfbf91ed14ef5ace9dcfc33f624300442c5198 by david.green [LV] Min/max intrinsic reduction test cases.
	llvm/test/Transforms/LoopVectorize/minmax_reduction.ll
Commit 18655140d6226ce35ef9e80e93f01d3aa4f44c01 by cullen.rhodes [NVPTX] NFC: Remove unused imm type intrinsic arg Identified in D109359. Reviewed By: tra Differential Revision: https://reviews.llvm.org/D109755
	llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
Commit 3b9470a6c46d0ecdb586a5a1e9223ea0c832337c by Justas.Janickas [OpenCL] Supports optional image types in C++ for OpenCL 2021 Adds support for a feature macro `__opencl_c_images` in C++ for OpenCL 2021 enabling a respective optional core feature from OpenCL 3.0. This change aims to achieve compatibility between C++ for OpenCL 2021 and OpenCL 3.0. Differential Revision: https://reviews.llvm.org/D109002
	clang/test/SemaOpenCL/unsupported-image.cl
	clang/lib/Sema/SemaType.cpp
Commit 533471ff2f82a5dd46ea59d5894ffe9b694c5ed9 by simon [MIPS] Remove unused tblgen template args. NFC Identified in D109359.
	llvm/lib/Target/Mips/MicroMips32r6InstrFormats.td
	llvm/lib/Target/Mips/Mips16InstrInfo.td
	llvm/lib/Target/Mips/MipsEVAInstrInfo.td
	llvm/lib/Target/Mips/MipsDSPInstrInfo.td
	llvm/lib/Target/Mips/Mips32r6InstrInfo.td
	llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td
	llvm/lib/Target/Mips/MicroMipsDSPInstrInfo.td
	llvm/lib/Target/Mips/MipsMSAInstrInfo.td
	llvm/lib/Target/Mips/MicroMipsInstrInfo.td
Commit dcba99418438ec1d624ad207674234bd2e9e3394 by llvm-dev [X86] combineX86ShuffleChain - ensure we only peek through bitcasts to vectors (PR51858) When searching for hidden identity shuffles (added at rG41146bfe82aecc79961c3de898cda02998172e4b), only peek through bitcasts to the source operand if it is a vector type as well.
	llvm/test/CodeGen/X86/vector-reduce-mul.ll
	llvm/lib/Target/X86/X86ISelLowering.cpp
Commit 61cc873a8ef1f3c77114b5322cf1f9f551c74978 by david.green [LV] Recognize intrinsic min/max reductions This extends the reduction logic in the vectorizer to handle intrinsic versions of min and max, both the floating point variants already created by instcombine under fastmath and the integer variants from D98152. As a bonus this allows us to match a chain of min or max operations into a single reduction, similar to how add/mul/etc work. Differential Revision: https://reviews.llvm.org/D109645
	llvm/include/llvm/Analysis/IVDescriptors.h
	llvm/test/Transforms/LoopVectorize/minmax_reduction.ll
	llvm/lib/Analysis/IVDescriptors.cpp