Commit
242524741f3582d93e4fac8052d0bfc40f4c1ac4
by tejohnson[MemProf] Fix format warnings
Fix the warnings that show up with -Wformat in this file.
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 | compiler-rt/lib/memprof/memprof_allocator.cpp |
Commit
94a2f9cdb6f9ef9843057030159ee69f76722121
by Ahmed Bougacha[GlobalISel] Fix CombinerHelper::isPredecessor for same def/use MI.
The doc comment for isPredecessor says: Returns true if \p DefMI precedes \p UseMI or they are the same instruction. And dominates relies on that behavior for its own: Returns true if \p DefMI dominates \p UseMI. By definition an instruction dominates itself.
Make both statements correct by fixing isPredecessor. Found by inspection.
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 | llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp |
Commit
e159d3cbfc250115d1244f3a6219436a52f90f86
by Ahmed Bougacha[AArch64][GlobalISel] Use MI::getIntrinsicID in more spots. NFC.
There's technically a difference in the logic used by these findIntrinsicID and MachineInstr::getIntrinsicID, but it shouldn't be a meaningful difference here, with G_INTRINSIC instructions. getIntrinsicID's "first non-def" logic should be correct for those.
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 | llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp |
 | llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp |
Commit
c8b3d7d6d6de37af68b2f379d0e37304f78e115f
by Jessica Paquette[AArch64][GlobalISel] Ensure atomic loads always get assigned GPR destinations
The default register bank selection code for G_LOAD assumes that we ought to use a FPR when the load is casted to a float/double.
For atomics, this isn't true; we should always use GPRs.
Without this patch, we crash in the following example:
https://godbolt.org/z/MThjas441
Also make the code a little more stylistically consistent while we're here.
Also test some other weird cast combinations as well.
Differential Revision: https://reviews.llvm.org/D109771
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 | llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll |
 | llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp |