Changes

Summary

  1. [UpdateCCTestChecks] Fix --replace-value-regex across RUN lines (details)
  2. [DAGCombine] reassoc flag shouldn't enable contract (details)
  3. [AArch64][X86] Allow 64-bit label differences lower to IMAGE_REL_*_REL32 (details)
  4. [ARM] Make sure we don't transform unaligned store to stm on Thumb1. (details)
  5. [SampleFDO] Make FSDiscriminator flag part of function parameters (details)
  6. [DFSan][NFC] Refactor Origin Address Alignment code. (details)
  7. [IR] convert warn-stack-size from module flag to fn attr (details)
  8. Clarify the "env" launch configuration setting. (details)
  9. [mlir][tosa] Enable tosa.div for TosaMakeBroadcastable (details)
  10. [ScalarEvolution] Ensure backedge-taken counts are not pointers. (details)
  11. [NFC] Add getUnderlyingObjects test (details)
Commit 2bfe0536e5143caad80f7a9691fa775cf451317b by jdenny.ornl
[UpdateCCTestChecks] Fix --replace-value-regex across RUN lines

Without this patch, llvm/utils/update_cc_test_checks.py fails to
perform `--replace-value-regex` replacements when two RUN lines
produce the same output and use the same single FileCheck prefix.  The
problem is that replacements in a RUN line's output are not performed
until after comparing against previous RUN lines' output, where
replacements have already been performed.  This patch fixes that.

Reviewed By: MaskRay

Differential Revision: https://reviews.llvm.org/D104566
The file was modifiedllvm/utils/UpdateTestChecks/common.py
The file was addedclang/test/utils/update_cc_test_checks/Inputs/replace-value-regex-across-runs.c
The file was addedclang/test/utils/update_cc_test_checks/replace-value-regex-across-runs.test
The file was addedclang/test/utils/update_cc_test_checks/Inputs/replace-value-regex-across-runs.c.expected
Commit 3996311ee1b0a3c29a3ffcf9400e12ca76a846d9 by Jinsong Ji
[DAGCombine] reassoc flag shouldn't enable contract

According to IR LangRef, the FMF flag:

contract
Allow floating-point contraction (e.g. fusing a multiply followed by an
addition into a fused multiply-and-add).

reassoc
Allow reassociation transformations for floating-point instructions.
This may dramatically change results in floating-point.

My understanding is that these two flags shouldn't imply each other,
as we might have a SDNode that can be reassociated with others, but
not contractble.

eg: We may want following fmul/fad/fsub to freely reassoc, but don't
want fma being generated here.

   %F = fmul reassoc double %A, %B         ; <double> [#uses=1]
   %G = fmul reassoc double %C, %D         ; <double> [#uses=1]
   %H = fadd reassoc double %F, %G         ; <double> [#uses=1]
   %I = fsub reassoc double %H, %E         ; <double> [#uses=1]

Before https://reviews.llvm.org/D45710, `reassoc` flag actually
did not imply isContratable either.

The current implementation also only check the flag in fadd node,
ignoring fmul node, this patch update that as well.

Reviewed By: spatel, qiucf

Differential Revision: https://reviews.llvm.org/D104247
The file was modifiedllvm/test/CodeGen/PowerPC/repeated-fp-divisors.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/fmuladd.f16.ll
The file was modifiedllvm/test/CodeGen/PowerPC/combine-fneg.ll
The file was modifiedllvm/test/CodeGen/PowerPC/fma-negate.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/fmuladd.f32.ll
The file was modifiedllvm/test/CodeGen/PowerPC/machine-combiner.ll
The file was modifiedllvm/test/CodeGen/AArch64/fadd-combines.ll
The file was modifiedllvm/test/CodeGen/X86/machine-combiner.ll
The file was modifiedllvm/test/CodeGen/PowerPC/recipest.ll
The file was modifiedllvm/test/CodeGen/PowerPC/register-pressure-reduction.ll
The file was modifiedllvm/test/CodeGen/PowerPC/fmf-propagation.ll
The file was modifiedllvm/test/CodeGen/PowerPC/fma-assoc.ll
The file was modifiedllvm/test/CodeGen/PowerPC/fma-mutate.ll
The file was modifiedllvm/test/CodeGen/X86/sqrt-fastmath.ll
The file was modifiedllvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
The file was modifiedllvm/test/CodeGen/AMDGPU/fmuladd.v2f16.ll
The file was modifiedllvm/test/CodeGen/PowerPC/fma-aggr-FMF.ll
The file was modifiedllvm/test/CodeGen/AMDGPU/fmuladd.f64.ll
The file was modifiedllvm/test/CodeGen/PowerPC/fma-precision.ll
The file was modifiedllvm/test/CodeGen/PowerPC/fma-combine.ll
The file was modifiedllvm/test/CodeGen/PowerPC/fdiv.ll
Commit c618692218d16e88fa20df56b29a8dd09c9e9db7 by i
[AArch64][X86] Allow 64-bit label differences lower to IMAGE_REL_*_REL32

`IMAGE_REL_ARM64_REL64/IMAGE_REL_AMD64_REL64` do not exist and `.quad a - .` is
currently not representable.

For instrumentation, `.quad a - .` is useful representing a cross-section
reference in a metadata section, to allow ELF medium/large code models. The COFF
limitation makes such generic instrumentations inconvenient. I plan to make a
PGO/coverage metadata section field relative in D104556.

Differential Revision: https://reviews.llvm.org/D104564
The file was modifiedllvm/test/MC/COFF/cross-section-relative-err.s
The file was modifiedllvm/test/MC/COFF/cross-section-relative.s
The file was modifiedllvm/lib/Target/X86/MCTargetDesc/X86WinCOFFObjectWriter.cpp
The file was modifiedllvm/lib/Target/AArch64/MCTargetDesc/AArch64WinCOFFObjectWriter.cpp
The file was modifiedllvm/test/MC/AArch64/coff-relocations.s
Commit bf0d0671a1062aec973c14522d6accf0c438b92e by efriedma
[ARM] Make sure we don't transform unaligned store to stm on Thumb1.

This isn't likely to come up in practice; the combination of compiler
flags required to hit this issue should be rare. Found by inspection.
The file was modifiedllvm/test/CodeGen/Thumb/ldm-stm-postinc.ll
The file was modifiedllvm/lib/Target/ARM/ARMISelLowering.cpp
Commit 8c68eb83065cc531fde28fc743a7278190f9eb65 by xur
[SampleFDO] Make FSDiscriminator flag part of function parameters

Add a parameter of IsFSDiscriminator to function
getBaseDiscriminatorFromDiscriminator().

This function currently checks the internal flag of
--enable-fs-discriminator. This is not good because we might
change the default value of the internal flag.

Note that we have a default parameter. This is just
because create_afdo_tool has a call-site to it.
I will remove the default parameter in a later patch.

Differential Revision: https://reviews.llvm.org/D104584
The file was modifiedllvm/include/llvm/Transforms/Utils/SampleProfileLoaderBaseImpl.h
The file was modifiedllvm/include/llvm/IR/DebugInfoMetadata.h
The file was modifiedllvm/tools/llvm-profgen/ProfiledBinary.cpp
Commit 759e7977679299296a0074bc3aba693d3386eb1c by browneee
[DFSan][NFC] Refactor Origin Address Alignment code.

Reviewed By: stephan.yichao.zhao

Differential Revision: https://reviews.llvm.org/D104565
The file was modifiedcompiler-rt/lib/dfsan/dfsan.cpp
Commit 8ace12130526f450c822ca232d1f865b247d7434 by ndesaulniers
[IR] convert warn-stack-size from module flag to fn attr

Otherwise, this causes issues when building with LTO for object files
that use different values.

Link: https://github.com/ClangBuiltLinux/linux/issues/1395

Reviewed By: dblaikie, MaskRay

Differential Revision: https://reviews.llvm.org/D104342
The file was modifiedllvm/lib/IR/Module.cpp
The file was addedllvm/test/Verifier/invalid-warn-stack-size.ll
The file was addedclang/test/Frontend/fwarn-stack-size.c
The file was removedllvm/test/Linker/warn-stack-frame.ll
The file was modifiedllvm/test/CodeGen/ARM/warn-stack.ll
The file was modifiedllvm/docs/LangRef.rst
The file was modifiedllvm/test/CodeGen/X86/warn-stack.ll
The file was modifiedllvm/lib/CodeGen/PrologEpilogInserter.cpp
The file was modifiedllvm/lib/IR/Verifier.cpp
The file was modifiedclang/lib/CodeGen/CodeGenFunction.cpp
The file was modifiedllvm/include/llvm/IR/Module.h
The file was modifiedclang/lib/CodeGen/CodeGenModule.cpp
Commit 4181bfe6888fdc6f24dc42d4ebb295920826de2b by gclayton
Clarify the "env" launch configuration setting.

A few users recently were trying to set environment values when using lldb-vscode and were unsure of the format of the "env" launch configuration setting. Clarify the exact format as when users add the "env" launch config setting, they can see this help string in the IDE.

Differential Revision: https://reviews.llvm.org/D104578
The file was modifiedlldb/tools/lldb-vscode/package.json
Commit ad1a9d629b759f43c8c1ea5d4c710c5c5b4b1e6b by rob.suderman
[mlir][tosa] Enable tosa.div for TosaMakeBroadcastable

TosaMakeBroadcastable needs to include tosa.div, which was added later in the
specification.

Reviewed By: sjarus, NatashaKnk

Differential Revision: https://reviews.llvm.org/D104157
The file was modifiedmlir/lib/Dialect/Tosa/Transforms/TosaMakeBroadcastable.cpp
Commit 8f3d16905d75b07a933d01dc29677fe5867c1b3e by efriedma
[ScalarEvolution] Ensure backedge-taken counts are not pointers.

A backedge-taken count doesn't refer to memory; returning a pointer type
is nonsense. So make sure we always return an integer.

The obvious way to do this would be to just convert the operands of the
icmp to integers, but that doesn't quite work out at the moment:
isLoopEntryGuardedByCond currently gets confused by ptrtoint operations.
So we perform the ptrtoint conversion late for lt/gt operations.

The test changes are mostly innocuous. The most interesting changes are
more complex SCEV expressions of the form "(-1 * (ptrtoint i8* %ptr to
i64)) + %ptr)". This is expected: we can't fold this to zero because we
need to preserve the pointer base.

The call to isLoopEntryGuardedByCond in howFarToZero is less precise
because of ptrtoint operations; this shows up in the function
pr46786_c26_char in ptrtoint.ll. Fixing it here would require more
complex refactoring.  It should eventually be fixed by future
improvements to isImpliedCond.

See https://bugs.llvm.org/show_bug.cgi?id=46786 for context.

Differential Revision: https://reviews.llvm.org/D103656
The file was modifiedllvm/test/Transforms/LoopVectorize/pr45259.ll
The file was modifiedllvm/test/Analysis/ScalarEvolution/max-backedge-taken-count-guard-info.ll
The file was modifiedllvm/test/Analysis/ScalarEvolution/ptrtoint.ll
The file was modifiedllvm/test/Analysis/ScalarEvolution/nsw.ll
The file was modifiedllvm/test/Transforms/LoopIdiom/memset-debugify-remarks.ll
The file was modifiedllvm/lib/Analysis/ScalarEvolution.cpp
The file was modifiedllvm/test/Transforms/IndVarSimplify/2011-11-01-lftrptr.ll
The file was modifiedllvm/test/Analysis/ScalarEvolution/no-wrap-symbolic-becount.ll
The file was modifiedllvm/test/Transforms/LoopReroll/ptrindvar.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/pointer-induction.ll
The file was modifiedllvm/test/Transforms/LoopVectorize/X86/cost-model-assert.ll
The file was modifiedllvm/test/Transforms/IndVarSimplify/eliminate-exit-no-dl.ll
The file was modifiedllvm/test/Transforms/PhaseOrdering/scev-custom-dl.ll
Commit ac15a128d8756074b150bb5cb11bfd93a1a5c30c by Vitaly Buka
[NFC] Add getUnderlyingObjects test

Reviewed By: lebedev.ri

Differential Revision: https://reviews.llvm.org/D104585
The file was modifiedllvm/test/Analysis/LoopAccessAnalysis/underlying-objects-2.ll

Summary

  1. Fix SpecCPU2017's dependency from timeit-target to build-timeit-target (details)
Commit 3e88eaf3f0f1f65cf8df4aef2df5ff47cb10e7c8 by aqjune
Fix SpecCPU2017's dependency from timeit-target to build-timeit-target

Building SpecCPU2017 using cmake raises this error:

```
CMake Error at External/SPEC/SpecCPU2017.cmake:263 (add_dependencies):
  The dependency target "timeit-target" of target "imagevalidate_525-target"
  does not exist.
Call Stack (most recent call first):
  External/SPEC/CINT2017rate/525.x264_r/CMakeLists.txt:24 (speccpu2017_validate_image)
```

I think `timeit-target` should be `build-timeit-target` instead because cmake's progress output has this line:

```
[  3%] Built target build-timeit-target
```

Fixing this resolves the dependency error.

Reviewed By: MaskRay

Differential Revision: https://reviews.llvm.org/D100734
The file was modifiedExternal/SPEC/SpecCPU2017.cmake (diff)