SuccessChanges

Summary

  1. [LLDB] Set lit arg -j4 for Arm/AArch64 Linux buildbots (details)
Commit 2ba285961959af1928e9d9535c869f3334a2030e by omair.javaid
[LLDB] Set lit arg -j4 for Arm/AArch64 Linux buildbots

We have started seeing some sporadic test failures on LLDB Arm/AArch64
Linux buildbots. This patch reduces no of parallel tests to 4 so
to provide some bandwidth for the timing critical and load dependent
test cases.
The file was modifiedbuildbot/osuosl/master/config/builders.py (diff)

Summary

  1. [Clang][AArch64] Inline assembly support for the ACLE type 'data512_t' (details)
  2. [AArch64] Add a Machine Value Type for 8 consecutive registers (details)
  3. [AArch64] Legalize MVT::i64x8 in DAG isel lowering (details)
  4. [MLIR] NFC Clean up doc comments on memref replacement utility (details)
Commit 29b263a34f1afbae9c95bf48eab7e8aac8132a80 by alexandros.lamprineas
[Clang][AArch64] Inline assembly support for the ACLE type 'data512_t'

In LLVM IR terms the ACLE type 'data512_t' is essentially an aggregate
type { [8 x i64] }. When emitting code for inline assembly operands,
clang tries to scalarize aggregate types to an integer of the equivalent
length, otherwise it passes them by-reference. This patch adds a target
hook to tell whether a given inline assembly operand is scalarizable
so that clang can emit code to pass/return it by-value.

Differential Revision: https://reviews.llvm.org/D94098
The file was addedclang/test/CodeGen/aarch64-ls64-inline-asm.c
The file was modifiedclang/lib/CodeGen/CGStmt.cpp
The file was modifiedclang/lib/CodeGen/TargetInfo.h
The file was modifiedclang/lib/CodeGen/TargetInfo.cpp
The file was modifiedclang/lib/Basic/Targets/AArch64.cpp
Commit 3094e5389b3dfb046eebcb549f7f4b814258863e by alexandros.lamprineas
[AArch64] Add a Machine Value Type for 8 consecutive registers

Adds MVT::i64x8, a Machine Value Type needed for lowering inline assembly
operands which materialize a sequence of eight general purpose registers.

Differential Revision: https://reviews.llvm.org/D94096
The file was modifiedllvm/utils/TableGen/CodeGenTarget.cpp
The file was modifiedllvm/include/llvm/CodeGen/ValueTypes.td
The file was modifiedllvm/include/llvm/Support/MachineValueType.h
The file was modifiedllvm/lib/CodeGen/ValueTypes.cpp
Commit 7d940432c46be83b8fcb5dbefee439585fa820cd by alexandros.lamprineas
[AArch64] Legalize MVT::i64x8 in DAG isel lowering

This patch legalizes the Machine Value Type introduced in D94096 for loads
and stores. A new target hook named getAsmOperandValueType() is added which
maps i512 to MVT::i64x8. GlobalISel falls back to DAG for legalization.

Differential Revision: https://reviews.llvm.org/D94097
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.cpp
The file was addedllvm/test/CodeGen/AArch64/ls64-inline-asm.ll
The file was modifiedllvm/lib/Target/AArch64/AArch64ISelLowering.h
The file was modifiedllvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h
The file was modifiedllvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64RegisterInfo.td
The file was modifiedllvm/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll
The file was modifiedllvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp
The file was modifiedllvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
The file was modifiedllvm/lib/Target/AArch64/AArch64InstrInfo.td
The file was modifiedllvm/include/llvm/CodeGen/TargetLowering.h
The file was modifiedllvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
Commit bf6c46d9173b973fa30ebb03e4204f87a1af6b2d by uday
[MLIR] NFC Clean up doc comments on memref replacement utility

NFC. Clean up stale doc comments on memref replacement utility and some
variable renaming in it to avoid confusion.

Differential Revision: https://reviews.llvm.org/D107144
The file was modifiedmlir/include/mlir/Transforms/Utils.h
The file was modifiedmlir/lib/Transforms/Utils/Utils.cpp