Changes

Summary

  1. Reland: [clang driver] Move default module cache from system temporary directory (details)
  2. Fix unused type alias warning. NFC. (details)
  3. [X86] Add AVX tests buildvec-insertvec.ll (details)
  4. [X86] Add PR46461 test case (details)
  5. [DAG] reduceBuildVecExtToExtBuildVec - don't combine if it would break a splat. (details)
  6. FileCollector.h - reduce Twine.h include to forward declaration. NFC. (details)
  7. [clang-format] [PR462254] fix indentation of default and break correctly in whitesmiths style (details)
  8. ThreadPool.h - remove unused BitVector.h include. NFC. (details)
  9. Revert "[Docs] Fix typo and test git commit access. NFC." (details)
  10. [clang-format] NFC 1% improvement in the overall clang-formatted status (details)
  11. [X86][AVX] SimplifyDemandedVectorEltsForTargetNode - reduce width of X86ISD::VPERMILPV (details)
  12. [X86][AVX] SimplifyDemandedVectorEltsForTargetNode - reduce width of X86ISD::VPERMIL2 (details)
  13. Update polly tests to use -disable-basicaa to -disable-basic-aa (details)
  14. [Analysis] isDereferenceableAndAlignedPointer(): don't crash on `bitcast <1 x ???*> to ???*` (details)
  15. [RISCV] Assemble/Disassemble v-ext instructions. (details)
  16. [RISCV] Support experimental v extensions. (details)
  17. [X86] SimplifyDemandedVectorEltsForTargetNode - merge shuffle/pack lower demanded elements handling. (details)
Commit dab859d1bf250c4d0299ac505e2a6773c56b6503 by dave
Reland: [clang driver] Move default module cache from system temporary directory

This fixes a unit test. Otherwise here is the original commit:

1) Shared writable directories like /tmp are a security problem.
2) Systems provide dedicated cache directories these days anyway.
3) This also refines LLVM's cache_directory() on Darwin platforms to use
   the Darwin per-user cache directory.

Reviewers: compnerd, aprantl, jakehehrlich, espindola, respindola, ilya-biryukov, pcc, sammccall

Reviewed By: compnerd, sammccall

Subscribers: hiraditya, llvm-commits, cfe-commits

Tags: #clang, #llvm

Differential Revision: https://reviews.llvm.org/D82362
The file was modifiedclang/include/clang/Driver/Driver.h
The file was modifiedclang/test/Driver/modules-cache-path.m
The file was modifiedclang/unittests/Driver/ModuleCacheTest.cpp
The file was modifiedllvm/lib/Support/Unix/Path.inc
The file was modifiedllvm/unittests/Support/Path.cpp
The file was modifiedclang/docs/ReleaseNotes.rst
The file was modifiedclang/lib/Driver/ToolChains/Clang.cpp
Commit b392fb33761e983a8edb5946734427779e25bbe2 by llvm-dev
Fix unused type alias warning. NFC.

The "using InsertPointTy" line is an unnecessary copy + paste from other builder tests.
The file was modifiedllvm/unittests/Frontend/OpenMPIRBuilderTest.cpp
Commit 5883f6f977a9b90913451e3e3dc13e14d7cddaac by llvm-dev
[X86] Add AVX tests buildvec-insertvec.ll
The file was modifiedllvm/test/CodeGen/X86/buildvec-insertvec.ll
Commit 878a24d369ea4d627fb48f7af5edc28fd079a0c0 by llvm-dev
[X86] Add PR46461 test case
The file was modifiedllvm/test/CodeGen/X86/buildvec-insertvec.ll
Commit 6bdb3ce4529ffbaad0354b052f2e9f06b4431085 by llvm-dev
[DAG] reduceBuildVecExtToExtBuildVec - don't combine if it would break a splat.

reduceBuildVecExtToExtBuildVec was breaking a splat(zext(x)) pattern into buildvector(x, 0, x, 0, ..) resulting in much more complex insert+shuffle codegen.

We already go to some lengths to avoid this in SimplifyDemandedVectorElts etc. when we encounter splat buildvectors.

It should be OK to fold all splat(aext(x)) patterns - we might need to tighten this if we find a case where we mustn't introduce a buildvector(x, undef, x, undef, ..) but I can't find one.

Fixes PR46461.
The file was modifiedllvm/test/CodeGen/X86/buildvec-insertvec.ll
The file was modifiedllvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
The file was modifiedllvm/test/CodeGen/X86/broadcastm-lowering.ll
Commit 892df9e706e43c48854be8bf544c41a146611607 by llvm-dev
FileCollector.h - reduce Twine.h include to forward declaration. NFC.
The file was modifiedllvm/include/llvm/Support/FileCollector.h
The file was modifiedllvm/lib/Support/FileCollector.cpp
Commit eb50838ba08d4149182828b96956a57ec6f5f658 by mydeveloperday
[clang-format] [PR462254] fix indentation of default and break correctly in whitesmiths style

Summary:
https://bugs.llvm.org/show_bug.cgi?id=46254

Reviewed By: curdeius, jbcoe

Differential Revision: https://reviews.llvm.org/D8201
The file was modifiedclang/lib/Format/UnwrappedLineParser.cpp
The file was modifiedclang/lib/Format/UnwrappedLineFormatter.cpp
The file was modifiedclang/unittests/Format/FormatTest.cpp
Commit 8b9e9753ea6875fb954a5bcdfed132dd75d63d29 by llvm-dev
ThreadPool.h - remove unused BitVector.h include. NFC.
The file was modifiedllvm/include/llvm/Support/ThreadPool.h
Commit 43e3c39327f9c32bea73b2629b718e9f5fd678d1 by 1585086582
Revert "[Docs] Fix typo and test git commit access. NFC."

This reverts commit c19e82c6b38b74c56d595cb69582b7c3727762b5.
The file was modifiedclang-tools-extra/docs/clang-tidy/checks/readability-make-member-function-const.rst
Commit a43b99a1e38e2beffb68a6db93f216f511e7fd41 by mydeveloperday
[clang-format] NFC 1% improvement in the overall clang-formatted status
The file was modifiedclang/docs/ClangFormattedStatus.rst
Commit d56c6475a60aa44b040983fe4fd355399cc4c42d by llvm-dev
[X86][AVX] SimplifyDemandedVectorEltsForTargetNode - reduce width of X86ISD::VPERMILPV

If we don't need the elements of the upper lanes, reduce the width of the X86ISD::VPERMILPV node.
The file was modifiedllvm/test/CodeGen/X86/var-permute-256.ll
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
Commit e855efe42407dd67f6a513927d0669cb7a66f448 by llvm-dev
[X86][AVX] SimplifyDemandedVectorEltsForTargetNode - reduce width of X86ISD::VPERMIL2

If we don't need the elements of the upper lanes, reduce the width of the X86ISD::VPERMIL2 node.
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp
The file was modifiedllvm/test/CodeGen/X86/var-permute-256.ll
Commit 74dc081ef2d830a7fbff68b230176f874f741897 by llvm-dev
Update polly tests to use -disable-basicaa to -disable-basic-aa

These were missed in rG4cd19a6e15120cb
The file was modifiedpolly/test/Isl/Ast/alias_simple_1.ll
The file was modifiedpolly/test/Isl/CodeGen/multidim-non-matching-typesize.ll
The file was modifiedpolly/test/Isl/CodeGen/multidim-non-matching-typesize-2.ll
The file was modifiedpolly/test/ScopDetect/base_pointer.ll
The file was modifiedpolly/test/ScopDetect/base_pointer_setNewAccessRelation.ll
The file was modifiedpolly/test/ScopInfo/Alias-4.ll
The file was modifiedpolly/test/Isl/Ast/alias_simple_2.ll
The file was modifiedpolly/test/Isl/Ast/alias_simple_3.ll
Commit f0634100cdc832605bff355330d2ccdb7f43842f by lebedev.ri
[Analysis] isDereferenceableAndAlignedPointer(): don't crash on `bitcast <1 x ???*> to ???*`
The file was addedllvm/test/Transforms/SimplifyCFG/1elt-ptr-vec-alignment-crash.ll
The file was modifiedllvm/lib/Analysis/Loads.cpp
Commit 66da87dcbaf91fa3393ce80c687e9c2d133ee3ca by kai.wang
[RISCV] Assemble/Disassemble v-ext instructions.

Assemble/disassemble RISC-V V extension instructions according to
latest version spec in https://github.com/riscv/riscv-v-spec/.

I have tested this patch using GNU toolchain. The encoding is aligned
to GNU assembler output. In this patch, there is a test case for each
instruction at least.

The V register definition is just for assemble/disassemble. Its type
is not important in this stage. I think it will be reviewed and modified
as we want to do codegen for scalable vector types.

This patch does not include Zvamo, Zvlsseg, and Zvediv.

Differential revision: https://reviews.llvm.org/D69987
The file was addedllvm/lib/Target/RISCV/RISCVInstrInfoV.td
The file was addedllvm/test/MC/RISCV/rvv/sub.s
The file was modifiedllvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
The file was addedllvm/test/MC/RISCV/rvv/clip.s
The file was addedllvm/test/MC/RISCV/rvv/add.s
The file was addedllvm/test/MC/RISCV/rvv/store.s
The file was addedllvm/test/MC/RISCV/rvv/invalid.s
The file was addedllvm/test/MC/RISCV/rvv/snippet.s
The file was modifiedllvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h
The file was modifiedllvm/lib/Target/RISCV/RISCV.td
The file was modifiedllvm/lib/Target/RISCV/RISCVSchedRocket64.td
The file was modifiedllvm/lib/Target/RISCV/RISCVRegisterInfo.td
The file was addedllvm/test/MC/RISCV/rvv/freduction.s
The file was addedllvm/test/MC/RISCV/rvv/mv.s
The file was addedllvm/test/MC/RISCV/rvv/reduction.s
The file was addedllvm/test/MC/RISCV/rvv/or.s
The file was modifiedllvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
The file was modifiedllvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
The file was addedllvm/test/MC/RISCV/rvv/convert.s
The file was modifiedllvm/lib/Target/RISCV/RISCVSubtarget.h
The file was addedllvm/test/MC/RISCV/rvv/fmul.s
The file was addedllvm/test/MC/RISCV/rvv/fmv.s
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrFormats.td
The file was modifiedllvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h
The file was addedllvm/test/MC/RISCV/rvv/fmacc.s
The file was addedllvm/test/MC/RISCV/rvv/shift.s
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfo.h
The file was addedllvm/test/MC/RISCV/rvv/mask.s
The file was addedllvm/test/MC/RISCV/rvv/macc.s
The file was modifiedllvm/lib/Target/RISCV/RISCVInstrInfo.td
The file was addedllvm/test/MC/RISCV/rvv/fdiv.s
The file was addedllvm/test/MC/RISCV/rvv/fcompare.s
The file was addedllvm/lib/Target/RISCV/RISCVInstrFormatsV.td
The file was addedllvm/test/MC/RISCV/rvv/fothers.s
The file was modifiedllvm/lib/Target/RISCV/RISCVSystemOperands.td
The file was addedllvm/test/MC/RISCV/rvv/xor.s
The file was modifiedllvm/lib/Target/RISCV/RISCVSchedRocket32.td
The file was addedllvm/test/MC/RISCV/rvv/fsub.s
The file was addedllvm/test/MC/RISCV/rvv/mul.s
The file was addedllvm/test/MC/RISCV/rvv/div.s
The file was addedllvm/test/MC/RISCV/rvv/fminmax.s
The file was addedllvm/test/MC/RISCV/rvv/sign-injection.s
The file was addedllvm/test/MC/RISCV/rvv/compare.s
The file was addedllvm/test/MC/RISCV/rvv/fadd.s
The file was addedllvm/test/MC/RISCV/rvv/others.s
The file was addedllvm/test/MC/RISCV/rvv/vsetvl.s
The file was addedllvm/test/MC/RISCV/rvv/minmax.s
The file was modifiedllvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
The file was modifiedllvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
The file was addedllvm/test/MC/RISCV/rvv/and.s
The file was addedllvm/test/MC/RISCV/rvv/load.s
Commit d698ff92a59c0632aa6a88b72890eb401bd64faa by kai.wang
[RISCV] Support experimental v extensions.

This follows the design as discussed on the mailing lists in the
following RFC:
http://lists.llvm.org/pipermail/llvm-dev/2020-January/138364.html

Support for the vector 'v' extension v0.8.

Differential revision: https://reviews.llvm.org/D81188
The file was modifiedclang/test/Driver/riscv-arch.c
The file was modifiedclang/lib/Driver/ToolChains/Arch/RISCV.cpp
Commit 393b4bd1362f6634a972157e7c2f3936f51f7356 by llvm-dev
[X86] SimplifyDemandedVectorEltsForTargetNode - merge shuffle/pack lower demanded elements handling.

Generalize the vector operand extraction code for shuffle/pack ops - we can assume that the vector operands are the same width as the result, and any non-vector values can be reused directly in the smaller width op.
The file was modifiedllvm/lib/Target/X86/X86ISelLowering.cpp