Changes

Summary

Remove some non-determinism from the `Darwin/duplicate_os_log_reports.cpp` test. (details)
[Driver] Fix BooleanFFlag identifiers to use 'f' 'fno_' prefixes instead of suffixes (details)
[X86] Add pseudo instructions to use MULX with a single destination when the low result isn't used. (details)
[llvm-objdump] Simplify reportError() and prepend outs().flush() (details)
[llvm-objdump] Move llvm:: to llvm::objdump:: and qualifying definitions with objdump:: (details)
[llvm-objdump] Delete unneeeded namespace llvm {} (details)
[ELF][docs] Update supported targets (details)
[X86] Move MMX_SET0 pattern into the instruction definition. NFC (details)
[X86] Autogenerate complete checks. NFC (details)
[X86] Fix a place where we created MOVQ2DQ with a DstVT other than v2i64. (details)
[X86] Teach computeKnownBitsForTargetNode that the upper half of X86ISD::MOVQ2DQ is all zero. (details)
[DAGCombiner] Move debug message and statistic update into CommitTargetLoweringOpt. (details)
[X86] Add DAG combine to turn (v2i64 (scalar_to_vector (i64 (bitconvert (mmx))))) to MOVQ2DQ. Remove unneeded isel patterns. (details)
[X86] Remove unneeded bitconverts from isel patterns. NFC (details)
AMDGPU: Add setTruncStoreAction for vector i64 types made legal recently (details)
[AMDGPU] Precommit tests for D80813 (details)
[AMDGPU] Propagate fast-math flags when lowering FSIN and FCOS (details)

Commit fc532c1a0dc66bf23cac60f5363f180c6cbfefbc by Dan Liew Remove some non-determinism from the `Darwin/duplicate_os_log_reports.cpp` test. The test read from an uninitialized buffer which could cause the output to be unpredictable. The test is currently disabled so this won't actually change anything until the test is re-enabled.
	compiler-rt/test/asan/TestCases/Darwin/duplicate_os_log_reports.cpp
Commit 1b6d29e06b07e518025b6f06445ad3275d6f5684 by maskray [Driver] Fix BooleanFFlag identifiers to use 'f' 'fno_' prefixes instead of suffixes
	clang/include/clang/Driver/Options.td
Commit 07e8a780d81bb58a0c7bd4da6cc0b9beaec3c788 by craig.topper [X86] Add pseudo instructions to use MULX with a single destination when the low result isn't used. The instruction is defined to only produce high result if both destinations are the same. We can exploit this to avoid unnecessarily clobbering a register. In order to hide this from register allocation we use a pseudo instruction and expand the result during MCInst creation. Differential Revision: https://reviews.llvm.org/D80500
	llvm/lib/Target/X86/X86InstrArithmetic.td
	llvm/test/CodeGen/X86/i128-mul.ll
	llvm/test/CodeGen/X86/pr35636.ll
	llvm/lib/Target/X86/X86MCInstLower.cpp
	llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
	llvm/test/CodeGen/X86/atomic-unordered.ll
Commit a23d1e9aff4d8cb752e227b3e16f887cf49c15d4 by maskray [llvm-objdump] Simplify reportError() and prepend outs().flush() As noticed by dblaikie. I don't know what code paths using reportError can cause stdout output to be interleaved with stderr, so no test is added now. Also drop an unneeded use of errs().fflush() in reportWarning(). I requested this in D64165.
	llvm/tools/llvm-objdump/llvm-objdump.cpp
Commit 439d27d79f58282b618881142244bbdcb1f28345 by maskray [llvm-objdump] Move llvm:: to llvm::objdump:: and qualifying definitions with objdump:: Or adding `static`. Qualifying definitions with `objdump::` comforms to the coding standards https://llvm.org/docs/CodingStandards.html#use-namespace-qualifiers-to-implement-previously-declared-functions
	llvm/tools/llvm-objdump/COFFDump.cpp
	llvm/tools/llvm-objdump/llvm-objdump.cpp
	llvm/tools/llvm-objdump/llvm-objdump.h
Commit d04eb253c710aec30707e404cfc9dc672082d3a2 by maskray [llvm-objdump] Delete unneeeded namespace llvm {}
	llvm/tools/llvm-objdump/llvm-objdump.cpp
Commit ce1fadca608ffaf214732b843e084a75e55fcb50 by maskray [ELF][docs] Update supported targets PowerPC, PowerPC64 and x86-32 have production quality. Mention Hexagon, RISC-V and SPARC V9.
	lld/docs/index.rst
Commit 8857822452c758805e8bb33ecc877d8d0cce1660 by craig.topper [X86] Move MMX_SET0 pattern into the instruction definition. NFC
	llvm/lib/Target/X86/X86InstrMMX.td
Commit efc5857b0b121ffd0b74fcd7aa8c48419a3fe4fc by craig.topper [X86] Autogenerate complete checks. NFC
	llvm/test/CodeGen/X86/pr23246.ll
Commit 1ecf39d607acdb04c2bb5155e5f7265db2484511 by craig.topper [X86] Fix a place where we created MOVQ2DQ with a DstVT other than v2i64. The type profile and isel pattern have this type declared as being MVT::v2i64. But isel skips the explicit type check due to the type profile.
	llvm/lib/Target/X86/X86ISelLowering.cpp
Commit af1accdd860d4e1768a1f56a8651ae4d13445e14 by craig.topper [X86] Teach computeKnownBitsForTargetNode that the upper half of X86ISD::MOVQ2DQ is all zero.
	llvm/test/CodeGen/X86/mmx-cvt.ll
	llvm/test/CodeGen/X86/vec_insert-7.ll
	llvm/lib/Target/X86/X86ISelLowering.cpp
Commit a4dd45b7d09d8c12b87eaa0e6d1a92ce2b0defe0 by craig.topper [DAGCombiner] Move debug message and statistic update into CommitTargetLoweringOpt. This code was repeated in two callers of CommitTargetLoweringOpt. But CommitTargetLoweringOpt is also called from TargetLowering. We should print a message for those calls to. So sink the repeated code into CommitTargetLoweringOpt to catch those calls.
	llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Commit 7c3b8077cc3feed2de3de6f3efb0627d619d1434 by craig.topper [X86] Add DAG combine to turn (v2i64 (scalar_to_vector (i64 (bitconvert (mmx))))) to MOVQ2DQ. Remove unneeded isel patterns. We already had a DAG combine for (mmx (bitconvert (i64 (extractelement v2i64)))) to MOVDQ2Q. Remove patterns for MMX_MOVQ2DQrr/MMX_MOVDQ2Qrr that use scalar_to_vector/extractelement involving i64 scalar type with v2i64 and x86mmx.
	llvm/lib/Target/X86/X86ISelLowering.cpp
	llvm/lib/Target/X86/X86InstrMMX.td
Commit dbda87186ec1b28a98d7a91a651b5a47c6f06d40 by craig.topper [X86] Remove unneeded bitconverts from isel patterns. NFC The types already match so TableGen is removing the bitconvert.
	llvm/lib/Target/X86/X86InstrMMX.td
Commit 234eba90f4f346a4b0d260cdd61a9aae647b2b48 by changpeng.fang AMDGPU: Add setTruncStoreAction for vector i64 types made legal recently Reviewers: rampitec, arsenm Differential Revision: https://reviews.llvm.org/D80853
	llvm/lib/Target/AMDGPU/SIISelLowering.cpp
	llvm/test/CodeGen/AMDGPU/trunc-store-i64.ll
Commit d4751f35560321dfb38cd77b924e715b9ebf9203 by jay.foad [AMDGPU] Precommit tests for D80813
	llvm/test/CodeGen/AMDGPU/llvm.sin.ll
Commit 2768edfff19a170faca35a8c63163c8bb1b67382 by jay.foad [AMDGPU] Propagate fast-math flags when lowering FSIN and FCOS Differential Revision: https://reviews.llvm.org/D80813
	llvm/lib/Target/AMDGPU/SIISelLowering.cpp
	llvm/test/CodeGen/AMDGPU/llvm.sin.ll