Changes

Summary

  1. [NFC][InstCombine] Fix inconsistent comments (details)
  2. [llvm-profgen] Fix a bug of assertion (details)
  3. [llvm-profgen] Fix an out-of-range error during unwinding (details)
  4. [llvm-profgen] Fix a dangling vector reference in CS line number based generator (details)
  5. [RISCV] Update mir tests. (details)
Commit 10a5632550abb318c8012a80ae753f606263712a by gusrb406
[NFC][InstCombine] Fix inconsistent comments
The file was modifiedllvm/lib/Transforms/InstCombine/InstCombineVectorOps.cpp
Commit c2be2d3284d2b0d76eacbe3e3999fb0843ef65a6 by wlei
[llvm-profgen] Fix a bug of assertion

The assertion should work on the entire context.

Reviewed By: hoy, wenlei

Differential Revision: https://reviews.llvm.org/D110268
The file was modifiedllvm/tools/llvm-profgen/ProfiledBinary.cpp
Commit 686cc0006793b06fd15d08cc0188b071f49ae990 by wlei
[llvm-profgen] Fix an out-of-range error during unwinding

It happened that the LBR entry target can be the first address of text section which causes an out-of-range crash. So here add a boundary check.

Reviewed By: hoy, wenlei

Differential Revision: https://reviews.llvm.org/D110271
The file was modifiedllvm/tools/llvm-profgen/PerfReader.cpp
Commit 1ed69bb86eb188ab23f62c266d2d23846588e768 by wlei
[llvm-profgen] Fix a dangling vector reference in CS line number based generator

It seems we missed one spot to persist `SampleContextFrameVector` into the global table (CSProfileGenerator::populateFunctionBoundarySamples:340) which causes a crash.

This change tried to fix it in a centralized way i. e. where we generate the `FunctionSamples`.

Reviewed By: hoy, wenlei

Differential Revision: https://reviews.llvm.org/D110275
The file was modifiedllvm/tools/llvm-profgen/ProfileGenerator.cpp
The file was modifiedllvm/tools/llvm-profgen/ProfileGenerator.h
Commit ebc5feb4ed6b1f59a000669030f9639bf1763403 by kai.wang
[RISCV] Update mir tests.
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir
The file was modifiedllvm/test/CodeGen/RISCV/rvv/emergency-slot.mir
The file was modifiedllvm/test/CodeGen/RISCV/rvv/mask-reg-alloc.mir
The file was modifiedllvm/test/CodeGen/RISCV/rvv/reg-coalescing.mir
The file was modifiedllvm/test/CodeGen/RISCV/rvv/zvlsseg-copy.mir
The file was modifiedllvm/test/CodeGen/RISCV/rvv/commuted-op-indices-regression.mir
The file was modifiedllvm/test/CodeGen/RISCV/rvv/zvlsseg-spill.mir
The file was modifiedllvm/test/CodeGen/RISCV/rvv/addi-scalable-offset.mir
The file was modifiedllvm/test/CodeGen/RISCV/rvv/frameindex-addr.ll
The file was modifiedllvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir
The file was modifiedllvm/test/CodeGen/RISCV/rvv/get-vlen-debugloc.mir
The file was modifiedllvm/test/CodeGen/RISCV/rvv/tail-agnostic-impdef-copy.mir