Changes

Summary

[NFC][InstCombine] Fix inconsistent comments (details)
[llvm-profgen] Fix a bug of assertion (details)
[llvm-profgen] Fix an out-of-range error during unwinding (details)
[llvm-profgen] Fix a dangling vector reference in CS line number based generator (details)
[RISCV] Update mir tests. (details)
[NFC] Remove redundant setOperationAction. (details)
[MLIR] [Python] Make Attribute and Type hashable (details)
[X86][FP16] Change the order of the operands in complex FMA intrinsics to allow swap between the mul operands. (details)
[demangle] Support for ISO/IEC TS 18661 binary floating point type (details)

Commit 10a5632550abb318c8012a80ae753f606263712a by gusrb406 [NFC][InstCombine] Fix inconsistent comments
	llvm/lib/Transforms/InstCombine/InstCombineVectorOps.cpp
Commit c2be2d3284d2b0d76eacbe3e3999fb0843ef65a6 by wlei [llvm-profgen] Fix a bug of assertion The assertion should work on the entire context. Reviewed By: hoy, wenlei Differential Revision: https://reviews.llvm.org/D110268
	llvm/tools/llvm-profgen/ProfiledBinary.cpp
Commit 686cc0006793b06fd15d08cc0188b071f49ae990 by wlei [llvm-profgen] Fix an out-of-range error during unwinding It happened that the LBR entry target can be the first address of text section which causes an out-of-range crash. So here add a boundary check. Reviewed By: hoy, wenlei Differential Revision: https://reviews.llvm.org/D110271
	llvm/tools/llvm-profgen/PerfReader.cpp
Commit 1ed69bb86eb188ab23f62c266d2d23846588e768 by wlei [llvm-profgen] Fix a dangling vector reference in CS line number based generator It seems we missed one spot to persist `SampleContextFrameVector` into the global table (CSProfileGenerator::populateFunctionBoundarySamples:340) which causes a crash. This change tried to fix it in a centralized way i. e. where we generate the `FunctionSamples`. Reviewed By: hoy, wenlei Differential Revision: https://reviews.llvm.org/D110275
	llvm/tools/llvm-profgen/ProfileGenerator.h
	llvm/tools/llvm-profgen/ProfileGenerator.cpp
Commit ebc5feb4ed6b1f59a000669030f9639bf1763403 by kai.wang [RISCV] Update mir tests.
	llvm/test/CodeGen/RISCV/rvv/reg-coalescing.mir
	llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir
	llvm/test/CodeGen/RISCV/rvv/tail-agnostic-impdef-copy.mir
	llvm/test/CodeGen/RISCV/rvv/mask-reg-alloc.mir
	llvm/test/CodeGen/RISCV/rvv/zvlsseg-spill.mir
	llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir
	llvm/test/CodeGen/RISCV/rvv/commuted-op-indices-regression.mir
	llvm/test/CodeGen/RISCV/rvv/get-vlen-debugloc.mir
	llvm/test/CodeGen/RISCV/rvv/emergency-slot.mir
	llvm/test/CodeGen/RISCV/rvv/addi-scalable-offset.mir
	llvm/test/CodeGen/RISCV/rvv/frameindex-addr.ll
	llvm/test/CodeGen/RISCV/rvv/zvlsseg-copy.mir
Commit 13207a21a64d3a0f1537cc99efe91d757d51f46c by freddy.ye [NFC] Remove redundant setOperationAction. [FROUND,FROUNDEVEN][f32, f64, f128] are set Expand twice. Differential Revision: https://reviews.llvm.org/D110302
	llvm/lib/CodeGen/TargetLoweringBase.cpp
Commit 47cc166bc023b497bdffe0964d80f15eaee8b7da by john.demme [MLIR] [Python] Make Attribute and Type hashable Enables putting types and attributes in sets and in dicts as keys. Reviewed By: stellaraccident Differential Revision: https://reviews.llvm.org/D110301
	mlir/lib/Bindings/Python/IRCore.cpp
	mlir/test/python/ir/builtin_types.py
	mlir/test/python/ir/attributes.py
Commit ebec077e07f5d35a870f075fb665c006978d49ea by pengfei.wang [X86][FP16] Change the order of the operands in complex FMA intrinsics to allow swap between the mul operands. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D109658
	llvm/test/CodeGen/X86/avx512cfmulsh-instrinsics.ll
	llvm/test/CodeGen/X86/stack-folding-fp-avx512fp16vl.ll
	llvm/lib/Target/X86/X86InstrFragmentsSIMD.td
	llvm/lib/Target/X86/X86ISelLowering.cpp
	llvm/test/CodeGen/X86/stack-folding-fp-avx512fp16.ll
	llvm/test/CodeGen/X86/avx512fp16-combine-vfmulc-fadd.ll
	llvm/test/CodeGen/X86/avx512cfma-intrinsics.ll
	llvm/lib/Target/X86/X86InstrAVX512.td
	llvm/lib/Target/X86/X86IntrinsicsInfo.h
	llvm/test/CodeGen/X86/avx512cfmul-intrinsics.ll
	clang/lib/Headers/avx512vlfp16intrin.h
	llvm/lib/Target/X86/X86InstrInfo.cpp
	clang/lib/Headers/avx512fp16intrin.h
	llvm/test/CodeGen/X86/avx512fp16-combine-xor-vfmulc-fadd.ll
Commit 1873f3be78a5255df8c36c195f4c778f9f47fc5c by pengfei.wang [demangle] Support for ISO/IEC TS 18661 binary floating point type Reviewed By: #libc_abi, ldionne Differential Revision: https://reviews.llvm.org/D105278
	libcxxabi/src/demangle/ItaniumDemangle.h
	libcxxabi/test/test_demangle.pass.cpp
	llvm/include/llvm/Demangle/ItaniumDemangle.h