Commit
772bd8a7d99b8db899f594d393986e4b6cd85aa1
by Yaxun.LiuRevert "[CUDA][HIP] Defer overloading resolution diagnostics for host device functions"
This reverts commit 7f1f89ec8d9944559042bb6d3b1132eabe3409de.
This reverts commit 40df06cdafc010002fc9cfe1dda73d689b7d27a6.
|
 | clang/utils/TableGen/ClangDiagnosticsEmitter.cpp |
 | clang/include/clang/Basic/DiagnosticAnalysis.h |
 | clang/lib/Sema/SemaTemplateInstantiate.cpp |
 | clang/lib/Sema/AnalysisBasedWarnings.cpp |
 | clang/test/SemaCUDA/deferred-oeverload.cu |
 | clang/include/clang/Basic/DiagnosticFrontend.h |
 | clang/lib/Frontend/CompilerInvocation.cpp |
 | clang/include/clang/Basic/DiagnosticAST.h |
 | clang/include/clang/Basic/DiagnosticSerialization.h |
 | clang/include/clang/Basic/DiagnosticDriver.h |
 | clang/include/clang/Driver/Options.td |
 | clang/lib/Sema/SemaCUDA.cpp |
 | clang/lib/Sema/SemaTemplateVariadic.cpp |
 | clang/test/TableGen/deferred-diag.td |
 | clang/lib/Sema/SemaOpenMP.cpp |
 | clang/include/clang/Basic/DiagnosticSemaKinds.td |
 | clang/lib/Sema/SemaStmtAsm.cpp |
 | clang/lib/Sema/SemaStmt.cpp |
 | clang-tools-extra/clangd/Diagnostics.cpp |
 | clang/lib/Driver/ToolChains/Cuda.cpp |
 | clang/include/clang/Basic/DiagnosticCrossTU.h |
 | clang/lib/Sema/SemaType.cpp |
 | clang/include/clang/Basic/Diagnostic.td |
 | clang/include/clang/Basic/DiagnosticSema.h |
 | clang/include/clang/Basic/DiagnosticComment.h |
 | clang/lib/Basic/DiagnosticIDs.cpp |
 | clang/lib/Sema/SemaAttr.cpp |
 | clang/include/clang/Sema/Sema.h |
 | clang/include/clang/Basic/DiagnosticIDs.h |
 | clang/lib/Sema/SemaOverload.cpp |
 | clang/lib/Sema/SemaSYCL.cpp |
 | clang/lib/Sema/SemaDecl.cpp |
 | clang/tools/diagtool/DiagnosticNames.cpp |
 | clang/include/clang/Basic/DiagnosticLex.h |
 | clang/include/clang/Basic/DiagnosticRefactoring.h |
 | clang/lib/Sema/SemaExprObjC.cpp |
 | clang/lib/Driver/ToolChains/HIP.cpp |
 | clang/test/TableGen/DiagnosticBase.inc |
 | clang/lib/Sema/Sema.cpp |
 | clang/lib/Sema/SemaTemplateInstantiateDecl.cpp |
 | clang/include/clang/Basic/DiagnosticParse.h |
 | clang/include/clang/Basic/LangOptions.def |
Commit
829d14ee0a6aa79c89f7f3d9fcd9d27d3efd2b91
by Yaxun.LiuRevert "[NFC] Refactor DiagnosticBuilder and PartialDiagnostic"
This reverts commit ee5519d323571c4a9a7d92cb817023c9b95334cd.
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 | clang/include/clang/AST/TemplateName.h |
 | clang/lib/Basic/Diagnostic.cpp |
 | clang/include/clang/AST/ASTContext.h |
 | clang/include/clang/AST/Decl.h |
 | clang/include/clang/Basic/PartialDiagnostic.h |
 | clang/include/clang/Sema/Ownership.h |
 | clang/lib/AST/DeclCXX.cpp |
 | clang/include/clang/AST/Attr.h |
 | clang/lib/AST/TemplateName.cpp |
 | clang/include/clang/AST/NestedNameSpecifier.h |
 | clang/include/clang/AST/Type.h |
 | clang/include/clang/AST/CanonicalType.h |
 | clang/include/clang/AST/DeclarationName.h |
 | clang/include/clang/AST/DeclCXX.h |
 | clang/include/clang/Basic/Diagnostic.h |
 | clang/include/clang/Sema/ParsedAttr.h |
 | clang/lib/AST/ASTContext.cpp |
 | clang/lib/AST/TemplateBase.cpp |
 | clang/include/clang/Sema/Sema.h |
 | clang/include/clang/AST/TemplateBase.h |
Commit
296e97ae8f7183c2f8737b9e6e68df4904dbfadf
by uday[MLIR] Support for return values in Affine.For yield
Add support for return values in affine.for yield along the same lines as scf.for and affine.parallel.
Signed-off-by: Abhishek Varma <abhishek.varma@polymagelabs.com>
Differential Revision: https://reviews.llvm.org/D87437
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 | mlir/include/mlir/Dialect/Affine/IR/AffineOps.td |
 | mlir/lib/Dialect/Affine/EDSC/Builders.cpp |
 | mlir/lib/Dialect/Affine/IR/AffineOps.cpp |
 | mlir/test/EDSC/builder-api-test.cpp |
 | mlir/test/Dialect/Affine/invalid.mlir |
 | mlir/test/Dialect/Affine/ops.mlir |
 | mlir/include/mlir/Dialect/Affine/EDSC/Builders.h |
Commit
0602e8f77f8662c85155b8cf02937a2e71c01e12
by uday[MLIR][Affine] Add parametric tile size support for affine.for tiling
Add support to tile affine.for ops with parametric sizes (i.e., SSA values). Currently supports hyper-rectangular loop nests with constant lower bounds only. Move methods
- moveLoopBody(*) - getTileableBands(*) - checkTilingLegality(*) - tilePerfectlyNested(*) - constructTiledIndexSetHyperRect(*)
to allow reuse with constant tile size API. Add a test pass -test-affine -parametric-tile to test parametric tiling.
Differential Revision: https://reviews.llvm.org/D87353
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 | mlir/test/lib/Transforms/TestAffineLoopParametricTiling.cpp |
 | mlir/test/Dialect/Affine/loop-tiling-parametric.mlir |
 | mlir/lib/Dialect/Affine/Transforms/LoopTiling.cpp |
 | mlir/include/mlir/Transforms/LoopUtils.h |
 | mlir/test/lib/Transforms/CMakeLists.txt |
 | mlir/tools/mlir-opt/mlir-opt.cpp |
 | mlir/lib/Transforms/Utils/LoopUtils.cpp |
Commit
3783d3bc7b3dd966ac3b9436b73f16f855d12ff2
by craig.topper[X86] Don't match x87 register inline asm constraints unless the VT is floating point or its a clobber
The register class picked will be the RFP80 register class which has a f80 VT. The code in SelectionDAGBuilder that generates copies around inline assembly doesn't know how to handle an integer and floating point type of different bit widths.
The test case is derived from this https://godbolt.org/z/sEa659 which gcc accepts but clang crashes on. This patch just gives a more graceful error. I'm not sure if the single element struct case is special in gcc. Adding another field to the struct makes gcc reject it. If we want to support this correctly I think we need a change in the frontend to give us the true element type. Right now the frontend just realizes the constraint can take a memory argument so creates an integer type of the same size and bitcasts.
Differential Revision: https://reviews.llvm.org/D87485
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 | llvm/lib/Target/X86/X86ISelLowering.cpp |
 | llvm/test/CodeGen/X86/asm-reject-x87-int.ll |
Commit
48a23bccf3732e1480ad169bd4a08a68bb100bfa
by spatel[VectorCombine] limit load+insert transform to one-use
As discussed in: https://llvm.org/PR47558 ...there are several potential fixes/follow-ups visible in the test case, but this is the quickest and safest fix of the perf regression.
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 | llvm/test/Transforms/VectorCombine/X86/load.ll |
 | llvm/lib/Transforms/Vectorize/VectorCombine.cpp |
Commit
bea7749d0364a8c694f236a97d58167a33efdb9e
by Amara Emerson[AArch64][GlobalISel] Make <8 x s16> and <16 x s8> legal for shifts.
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 | llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp |
 | llvm/test/CodeGen/AArch64/GlobalISel/legalize-shift.mir |
Commit
7d5b10348371644c69041965b9864886e9961ddd
by Amara Emerson[AArch64][GlobalISel] Widen G_EXTRACT_VECTOR_ELT element types if < 8b.
In order to not unnecessarily promote the source vector to greater than our native vector size of 128b, I've added some cascading rules to widen based on the number of elements.
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 | llvm/test/CodeGen/AArch64/GlobalISel/legalize-extract-vector-elt.mir |
 | llvm/test/CodeGen/AArch64/GlobalISel/regbank-extract-vector-elt.mir |
 | llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp |
Commit
1e5b7e91aa64c267e495cb4bd8351b1840694437
by rnk[PDB] Split TypeServerSource and extend type index map lifetime
Extending the lifetime of these type index mappings does increase memory usage (+2% in my case), but it decouples type merging from symbol merging. This is a pre-requisite for two changes that I have in mind: - parallel type merging: speeds up slow type merging - defered symbol merging: avoid heap allocating (relocating) all symbols
This eliminates CVIndexMap and moves its data into TpiSource. The maps are also split into a SmallVector and ArrayRef component, so that the ipiMap can alias the tpiMap for /Z7 object files, and so that both maps can simply alias the PDB type server maps for /Zi files.
Splitting TypeServerSource establishes that all input types to be merged can be identified with two 32-bit indices: - The index of the TpiSource object - The type index of the record This is useful, because this information can be stored in a single 64-bit atomic word to enable concurrent hashtable insertion.
One last change is that now all object files with debugChunks get a TpiSource, even if they have no type info. This avoids some null checks and special cases.
Differential Revision: https://reviews.llvm.org/D87736
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 | lld/COFF/InputFiles.cpp |
 | lld/COFF/DebugTypes.cpp |
 | lld/COFF/PDB.cpp |
 | lld/COFF/DebugTypes.h |
 | lld/COFF/TypeMerger.h |
Commit
a35c7f30769b4bc3745796af58c932f303a014e1
by mcinally[SVE][WIP] Implement lowering for fixed length VSELECT to Scalable
Map fixed length VSELECT to its Scalable equivalent.
Differential Revision: https://reviews.llvm.org/D85364
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 | llvm/test/CodeGen/AArch64/sve-fixed-length-fp-select.ll |
 | llvm/test/CodeGen/AArch64/sve-fixed-length-int-select.ll |
 | llvm/lib/Target/AArch64/AArch64ISelLowering.cpp |
 | llvm/lib/Target/AArch64/AArch64ISelLowering.h |
Commit
7e4c6fb854660318dc31ecb9842f6cfebb18c8e0
by andrew_litteken[IRSim] Adding IR Instruction Mapper
This introduces the IRInstructionMapper, and the associated wrapper for instructions, IRInstructionData, that maps IR level Instructions to unsigned integers.
Mapping is done mainly by using the "isSameOperationAs" comparison between two instructions. If they return true, the opcode, result type, and operand types of the instruction are used to hash the instruction with an unsigned integer. The mapper accepts instruction ranges, and adds each resulting integer to a list, and each wrapped instruction to a separate list.
At present, branches, phi nodes are not mapping and exception handling is illegal. Debug instructions are not considered.
The different mapping schemes are tested in unittests/Analysis/IRSimilarityIdentifierTest.cpp
Recommit of: b04c1a9d3127730c05e8a22a0e931a12a39528df
Differential Revision: https://reviews.llvm.org/D86968
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 | llvm/include/llvm/Analysis/IRSimilarityIdentifier.h |
 | llvm/lib/Analysis/IRSimilarityIdentifier.cpp |
 | llvm/lib/Analysis/CMakeLists.txt |
 | llvm/unittests/Analysis/CMakeLists.txt |
 | llvm/unittests/Analysis/IRSimilarityIdentifierTest.cpp |
Commit
667762c64e0b2925112037c197709402b4f2221d
by llvmgnsyncbot[gn build] Port 7e4c6fb8546
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 | llvm/utils/gn/secondary/llvm/unittests/Analysis/BUILD.gn |
 | llvm/utils/gn/secondary/llvm/lib/Analysis/BUILD.gn |
Commit
c145a1ca2593e3b8b79687d5ba8c3230c41b5130
by Jon RoelofsAArch64::ArchKind's underlying type is uint64_t
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 | clang/lib/Driver/ToolChains/Arch/AArch64.cpp |
 | llvm/include/llvm/Support/AArch64TargetParser.h |
 | llvm/unittests/Support/TargetParserTest.cpp |
 | llvm/lib/Support/AArch64TargetParser.cpp |
Commit
5813fca1076089c835de737834955a0fe7eb3898
by Vitaly Buka[Lsan] Use fp registers to search for pointers
X86 can use xmm registers for pointers operations. e.g. for std::swap. I don't know yet if it's possible on other platforms.
NT_X86_XSTATE includes all registers from NT_FPREGSET so the latter used only if the former is not available. I am not sure how reasonable to expect that but LLD has such fallback in NativeRegisterContextLinux_x86_64::ReadFPR.
Reviewed By: morehouse
Differential Revision: https://reviews.llvm.org/D87754
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 | compiler-rt/lib/sanitizer_common/sanitizer_stoptheworld_linux_libcdep.cpp |
 | compiler-rt/test/lsan/TestCases/use_registers.cpp |
 | compiler-rt/test/lsan/TestCases/use_registers_extra.cpp |
Commit
a4bb71b1c0d9952208ad32bc4992cc211d43c5bb
by wei.huangDisable hoisting MI to hotter basic blocks when using pgo
This is a follow up patch for https://reviews.llvm.org/D63676 to enable the feature when using pgo.
Differential Revision: https://reviews.llvm.org/D85240
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 | llvm/lib/CodeGen/MachineLICM.cpp |
 | llvm/test/CodeGen/ARM/O3-pipeline.ll |
 | llvm/test/CodeGen/X86/opt-pipeline.ll |
 | llvm/test/CodeGen/AArch64/O3-pipeline.ll |
Commit
51973a607dfa4681037aff43e295f3ea1fb0f3f4
by flo[SCEV] Add test cases for max BTC with loop guard info.
This adds test cases for PR40961 and PR47247. They illustrate cases in which the max backedge-taken count can be improved by information from the loop guards.
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 | llvm/test/Analysis/ScalarEvolution/max-backedge-taken-count-guard-info.ll |
Commit
59855b9d3bacc4321e3dd22ccf09bd9d177fdb6f
by nikita.ppv[GVN] Add additional assume tests (NFC)
The other assume tests seem to be dealing with equalities in particular. Test implication for the condition itself, especially the negated case from PR47496.
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 | llvm/test/Transforms/GVN/assume.ll |
Commit
91ce8e121b7f24ef68fad0ab07f6ab7e1ee06855
by nikita.ppv[GVN] Use that assume(!X) implies X==false (PR47496)
We already use that assume(X) implies X==true, do the same for assume(!X) implying X==false. This fixes PR47496.
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 | llvm/test/Transforms/GVN/assume.ll |
 | llvm/lib/Transforms/Scalar/GVN.cpp |
Commit
1cee33e9dbb6c30ff1dd30453a263696bfccfd8a
by whitneyt[LoopUnrollAndJam] Allow unroll and jam loops forced by user.
Summary: Allow unroll and jam loops forced by user. LoopUnrollAndJamPass is still disabled by default in the NPM pipeline, and can be controlled by -enable-npm-unroll-and-jam.
Reviewed By: Meinersbur, dmgreen
Differential Revision: https://reviews.llvm.org/D87786
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 | llvm/lib/Transforms/Scalar/LoopUnrollAndJamPass.cpp |
 | llvm/test/Transforms/LoopUnrollAndJam/pragma-explicit.ll |
Commit
05d4c4ebc2fb006b8a2bd05b24c6aba10dd2eef8
by nikita.ppv[InstCombine] Canonicalize SPF_ABS to abs intrinc
Enable canonicalization of SPF_ABS and SPF_NABS to the abs intrinsic.
To be conservative, the one-use check on the comparison is retained, this may be relaxed if all goes well.
It's pretty likely that this will uncover places that missing handling for the abs() intrinsic. Please report any seen performance regressions.
Differential Revision: https://reviews.llvm.org/D87188
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 | llvm/test/Transforms/InstCombine/abs_abs.ll |
 | llvm/test/Transforms/InstCombine/sub-of-negatible.ll |
 | llvm/test/Transforms/InstCombine/abs-1.ll |
 | llvm/test/Transforms/PhaseOrdering/X86/vector-reductions.ll |
 | clang/test/CodeGen/builtins-wasm.c |
 | llvm/test/Transforms/InstCombine/select_meta.ll |
 | llvm/test/Transforms/PhaseOrdering/min-max-abs-cse.ll |
 | llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp |
 | llvm/test/Transforms/InstCombine/icmp.ll |
 | llvm/test/Transforms/InstCombine/max-of-nots.ll |
 | llvm/test/Transforms/InstCombine/call-callconv.ll |
 | llvm/test/Transforms/InstCombine/cttz-abs.ll |
Commit
53ba045f488f7ef7d4894926fad8de0b76f1e20a
by alexshap[llvm-install-name-tool] Update the command-line guide
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 | llvm/docs/CommandGuide/llvm-install-name-tool.rst |
Commit
179a22e807a40ae5821920cec3c1933eef4dc30c
by aeubanks[NewPM] Fix pr45927.ll under NPM
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 | llvm/test/Analysis/MemorySSA/pr45927.ll |
Commit
a0017c2bc258690146f18491317144e487ddb101
by flo[MemorySSA] Be more conservative when traversing MemoryPhis.
I think we need to be even more conservative when traversing memory phis, to make sure we catch any loop carried dependences.
This approach updates fillInCurrentPair to use unknown sizes for locations when we walk over a phi, unless the location is guaranteed to be loop-invariant for any possible loop. Using an unknown size for locations should ensure we catch all memory accesses to locations after the given memory location, which includes loop-carried dependences.
Reviewed By: asbirlea
Differential Revision: https://reviews.llvm.org/D87778
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 | llvm/test/Analysis/MemorySSA/phi-translation.ll |
 | llvm/include/llvm/Analysis/MemorySSA.h |
Commit
0ff28fa6a75617d61b1aeea77463d6a1684c3c89
by dschuffSupport dwarf fission for wasm object files
Initial support for dwarf fission sections (-gsplit-dwarf) on wasm. The most interesting change is support for writing 2 files (.o and .dwo) in the wasm object writer. My approach moves object-writing logic into its own function and calls it twice, swapping out the endian::Writer (W) in between calls. It also splits the import-preparation step into its own function (and skips it when writing a dwo).
Differential Revision: https://reviews.llvm.org/D85685
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 | llvm/include/llvm/MC/MCWasmObjectWriter.h |
 | llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp |
 | llvm/lib/MC/MCAsmBackend.cpp |
 | llvm/test/DebugInfo/WebAssembly/fission-sections.ll |
 | llvm/lib/MC/MCObjectFileInfo.cpp |
 | llvm/test/DebugInfo/WebAssembly/fission-cu.ll |
 | clang/lib/Driver/ToolChains/Clang.cpp |
 | clang/test/Driver/split-debug.c |
 | llvm/lib/MC/WasmObjectWriter.cpp |
Commit
99e865b618f31c69776273a60addbd88917a29d9
by qcolombet[TargetRegisterInfo] Add a couple of target hooks for the greedy register allocator
Before this patch, the last chance recoloring and deferred spilling techniques were solely controled by command line options. This patch adds target hooks for these two techniques so that it is easier for backend writers to override the default behavior.
The default behavior of the hooks preserves the default values of the related command line options.
NFC
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 | llvm/lib/CodeGen/RegAllocGreedy.cpp |
 | llvm/include/llvm/CodeGen/TargetRegisterInfo.h |
Commit
f2f0474c93ee67421fae007528ae4be20ae384f8
by aeubanks[test] Fix FullUnroll.ll
I believe the intention of this test added in https://reviews.llvm.org/D71687 was to test LoopFullUnrollPass with clang's -fno-unroll-loops, not its interaction with optnone. Loop unrolling passes don't run under optnone/-O0.
Also added back unintentionally removed -disable-loop-unrolling from https://reviews.llvm.org/D85578.
Reviewed By: echristo
Differential Revision: https://reviews.llvm.org/D86485
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 | llvm/test/Transforms/LoopUnroll/FullUnroll.ll |
Commit
b04c181ed776c344e6f5e2653a22bc6e5746834a
by listmail[AArch64] Enable implicit null check transformation
This change enables the generic implicit null transformation for the AArch64 target. As background for those unfamiliar with our implicit null check support:
An implicit null check is the use of a signal handler to catch and redirect to a handler a null pointer. Specifically, it's replacing an explicit conditional branch with such a redirect. This is only done for very cold branches under frontend control w/appropriate metadata. FAULTING_OP is used to wrap the faulting instruction. It is modelled as being a conditional branch to reflect the fact it can transfer control in the CFG. FAULTING_OP does not need to be an analyzable branch to achieve it's purpose. (Or at least, that's the x86 model. I find this slightly questionable.) When lowering to MC, we convert the FAULTING_OP back into the actual instruction, record the labels, and lower the original instruction.
As can be seen in the test changes, currently the AArch64 backend does not eliminate the unconditional branch to the fallthrough block. I've tried two approaches, neither of which worked. I plan to return to this in a separate change set once I've wrapped my head around the interactions a bit better. (X86 handles this via AllowModify on analyzeBranch, but adding the obvious code causing BranchFolding to crash. I haven't yet figured out if it's a latent bug in BranchFolding, or something I'm doing wrong.)
Differential Revision: https://reviews.llvm.org/D87851
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 | llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp |
 | llvm/test/CodeGen/AArch64/implicit-null-check.ll |
 | llvm/lib/CodeGen/BranchRelaxation.cpp |
 | llvm/lib/CodeGen/ImplicitNullChecks.cpp |
 | llvm/lib/Target/AArch64/AArch64InstrInfo.cpp |
 | llvm/lib/Target/AArch64/AArch64InstrInfo.h |
Commit
1c466477ad468d8a18c43b738df7b7fc6213e9a8
by zhaoshiz[RISCV] Support Shadow Call Stack
Currenlty assume x18 is used as pointer to shadow call stack. User shall pass flags:
"-fsanitize=shadow-call-stack -ffixed-x18"
Runtime supported is needed to setup x18.
If SCS is desired, all parts of the program should be built with -ffixed-x18 to maintain inter-operatability.
There's no particuluar reason that we must use x18 as SCS pointer. Any register may be used, as long as it does not have designated purpose already, like RA or passing call arguments.
Differential Revision: https://reviews.llvm.org/D84414
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 | llvm/lib/Target/RISCV/RISCVFrameLowering.cpp |
 | clang/test/Driver/sanitizer-ld.c |
 | clang/lib/Driver/ToolChain.cpp |
 | clang/test/CodeGen/shadowcallstack-attr.c |
 | clang/lib/Driver/SanitizerArgs.cpp |
 | llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h |
 | llvm/test/CodeGen/RISCV/shadowcallstack.ll |
 | llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.cpp |
Commit
8069844577d47f503cb71644f2e58e0237d5b539
by jurahul[MLIR][TableGen] Automatic detection and elimination of redundant methods
- Change OpClass new method addition to find and eliminate any existing methods that are made redundant by the newly added method, as well as detect if the newly added method will be redundant and return nullptr in that case. - To facilitate that, add the notion of resolved and unresolved parameters, where resolved parameters have each parameter type known, so that redundancy checks on methods with same name but different parameter types can be done. - Eliminate existing code to avoid adding conflicting/redundant build methods and rely on this new mechanism to eliminate conflicting build methods.
Fixes https://bugs.llvm.org/show_bug.cgi?id=47095
Differential Revision: https://reviews.llvm.org/D87059
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 | mlir/tools/mlir-tblgen/OpDefinitionsGen.cpp |
 | mlir/include/mlir/TableGen/OpClass.h |
 | mlir/lib/TableGen/OpClass.cpp |
 | mlir/test/mlir-tblgen/op-attribute.td |
 | mlir/tools/mlir-tblgen/OpFormatGen.cpp |
 | mlir/test/mlir-tblgen/op-result.td |
Commit
b4013f9c7febe70bddca16fb80a2e99623528871
by listmail[MemorySSA] Fix an unused variable warning [NFC]
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 | llvm/include/llvm/Analysis/MemorySSA.h |
Commit
2c3bc918db35913437e9302b77b11c08eb3ea6e4
by amy.kwan1[PowerPC] Implement Vector Count Mask Bits builtins in LLVM/Clang
This patch implements the vec_cntm function prototypes in altivec.h in order to utilize the vector count mask bits instructions introduced in Power10.
Differential Revision: https://reviews.llvm.org/D82726
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 | clang/lib/Headers/altivec.h |
 | clang/include/clang/Basic/BuiltinsPPC.def |
 | clang/test/CodeGen/builtins-ppc-p10vector.c |
 | llvm/test/CodeGen/PowerPC/p10-vector-mask-ops.ll |
 | llvm/include/llvm/IR/IntrinsicsPowerPC.td |
 | llvm/lib/Target/PowerPC/PPCInstrPrefix.td |
Commit
6f3c0991bf9be48bd18a324c90e4cfcd37f82b96
by amy.kwan1[PowerPC] Add Set Boolean Condition Instruction Definitions and MC Tests
This patch adds the instruction definitions and assembly/disassembly tests for the set boolean condition instructions. This also includes the negative, and reverse variants of the instruction.
Differential Revision: https://reviews.llvm.org/D86252
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 | llvm/lib/Target/PowerPC/PPCInstrPrefix.td |
 | llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ISA31.txt |
 | llvm/test/MC/PowerPC/ppc64-encoding-ISA31.s |
Commit
196e2f97b714bb535a39a2daa949e523c21c0269
by Amara Emerson[AArch64][GlobalISel] clang-format AArch64LegalizerInfo.cpp. NFC.
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 | llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp |
Commit
f5898f8c2def7a1897559a7454086243b7e9ebb6
by Amara Emerson[AArch64][GlobalISel] Make G_STORE <8 x s8> legal.
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 | llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp |
 | llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir |
Commit
4926a5ee63017396e1c55b1505f9fd2bed858218
by Vedant Kumar[lldb] Clarify docstring for SBBlock::IsInlined, NFC
Previously, there was a little ambiguity about whether IsInlined should return true for an inlined lexical block, since technically the lexical block would not represent an inlined function (it'd just be contained within one).
Edit suggested by Jim Ingham.
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 | lldb/bindings/interface/SBBlock.i |
Commit
bae63742057785e03732f58d6ed1ec7bda090cc1
by silvasean[mlir][shape] Add `shape.cstr_require %bool`
This op is a catch-all for creating witnesses from various random kinds of constraints. In particular, I when dealing with extents directly, which are of `index` type, one can directly use std ops for calculating the predicates, and then use cstr_require for the final conversion to a witness.
Differential Revision: https://reviews.llvm.org/D87871
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 | mlir/include/mlir/Dialect/Shape/IR/ShapeOps.td |
 | mlir/test/Dialect/Shape/canonicalize.mlir |
 | mlir/test/Dialect/Shape/ops.mlir |
 | mlir/lib/Dialect/Shape/IR/Shape.cpp |
Commit
ea237e2c8e5d082715effb9cb64158d7c6894e27
by jurahul[MLIR] Fix build failure due to https://reviews.llvm.org/D87059.
- Remove spurious ; - Make comparison object invokable as const.
Differential Revision: https://reviews.llvm.org/D87872
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 | mlir/include/mlir/TableGen/OpClass.h |
Commit
27f34540ea56207f527dba6bbb9cd25a57be3f62
by mcgrathr[scudo/standalone] Don't define test main function for Fuchsia
Fuchsia's unit test library provides the main function by default.
Reviewed By: cryptoad
Differential Revision: https://reviews.llvm.org/D87809
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 | compiler-rt/lib/scudo/standalone/tests/scudo_unit_test_main.cpp |
Commit
03358becbf22a221d6d965ec8f3f7068668f7d29
by Vitaly Buka[NFC][Lsan] Fix zero-sized array compilation error
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 | clang/lib/Tooling/Syntax/Synthesis.cpp |
 | compiler-rt/lib/sanitizer_common/sanitizer_stoptheworld_linux_libcdep.cpp |
Commit
55edf7039e22312790ac950305746262d2856d97
by Vitaly Buka[NFC] clang-format one line
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 | clang/lib/Tooling/Syntax/Synthesis.cpp |